JPH0378003B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to latch circuits, and more particularly to CMOS latch circuits.

[Conventional technology]

Conventionally, a CMOS latch circuit consists of two N-channel MOS FETQ ₂₀ as shown in FIG.
and Q ₂₁ , two P-channel MOS FETs Q ₂₅ and Q ₂₆ , and two N-channel MOS FETs Q ₂₃ and Q _24.
and a second C MOS inverter composed of two P-channel MOS FETs Q ₂₇ and Q ₂₈ , and an inverter ₁₀ ,
The sources of MOS FET Q 20 and MOS FET Q ₂₈ are connected to the power supply terminal Vcc, the sources of MOS FET Q ₂₀ and MOS FET Q ₂₃ are grounded, and the sources of MOS FET Q ₂₀ and MOS FET
The gate of Q ₂₆ is the data input terminal (data input D)
connected to MOS FET Q ₂₁ and MOS FET Q ₂₇
The gate of is connected to the first gate input terminal (first gate input G), and the gate of MOS FET Q ₂₅ and MOS
The gate of FET Q ₂₄ is connected to the second gate input terminal (second gate input), and the four MOS
The drains of FETs Q ₂₁ , Q ₂₄ , Q ₂₅ , and Q ₂₇ are all connected to the input terminal of the inverter 10, and the MOS
The gates of FET Q ₂₃ and MOS FET Q ₂₈ and the output terminal of inverter 10 are connected to a data output terminal (data output Q).

Now, when the first gate input G is "H" and the second gate input is "L", when the data input D is taken in, the data input D becomes the opposite phase after passing through the first CMOS inverter. The signals are returned to the same phase through the inverter 10 and output as data output Q. Next, the first gate input G is “L”
, the second gate input becomes “H”,
Both MOS FET Q ₂₄ and MOS FET Q ₂₇ are turned on, and since positive feedback is applied to MOS FET Q ₂₃ and MOS FET Q ₂₈ by the inverter 10, the data output Q is maintained as is.

[Problem that the invention seeks to solve]

The conventional CMOS latch circuit described above is composed of nine elements, and the number of elements is large.
The disadvantage is that the chip area becomes large when used in large numbers in VLSI.

[Means for solving problems]

The CNOS latch circuit of the present invention has a data input terminal D.
, first and second gate input terminals G to which mutually opposite phase signals are input, first and second power supply terminals, data output terminal Q, one end of which is connected to the first power supply terminal; A first FET Q1 of one conductivity type is connected to the data input terminal, and a second FET of one conductivity type has one end connected to the other end of the first FET and a gate connected to the first gate input terminal G. FET Q2 and one end connected to the second
At the other end of the FET, a third FET Q3 of the opposite conductivity type is connected to the second gate input terminal G of the gate, one end is connected to the other end of the third FET, the gate is connected to the data input terminal, and the other end is connected to the second gate input terminal G. A fourth FET Q4 of opposite conductivity type connected to the second power supply terminal, and a fourth FET of one conductivity type having one end connected to the first power supply line and the gate connected to the data output terminal or the second gate input terminal. A fifth FET Q5,
A sixth FET Q6 of one conductivity type whose one end is connected to the other end of the fifth FET and whose gate is connected to the second gate input terminal or data output terminal;
The other end of the FET is a reverse conductivity type FET whose gate is connected to the data output end and the other end is connected to the second power supply end.
Q7, an inverting circuit 1 whose input terminal is connected to the connection point of the second and third FETs, and the connection point of the sixth and seventh FETs, and whose output is connected to the data output terminal. Features.

Figures 4a and 4b show C of the conventional example and the example of the present invention, respectively.
FIG. 3 is a diagram showing the layout of a chip using a MOS latch circuit, particularly the state of gate input wiring and the size of the chip.

In the conventional example, the first gate input wiring is an N-channel MOS FET Q ₂₁ and a P-channel MOS FET.
Q ₂₇ and the second gate input wiring connects P channel MOS FET Q ₂₅ and N channel MOS FET
Q ₂₄ , one first gate input wiring and one second gate input wiring are required for each of the P-channel MOS region and N-channel MOS region on the chip. ). on the other hand,
In this embodiment, the first gate input wiring is N
Since the input is only to the gate of the P-channel MOS FET Q ₂ , the first gate input wiring is not required in the P-channel MOS FET area on the chip, and the second gate input is connected to the P-channel MOS FET Q ₃ and the N-channel MOS Because it is connected to FET Q ₆ or Q ₅ ,
On the chip, there is a second
In addition to providing one gate input wiring for
The MOS area can be appropriately extended inside the chip (Figure 4b).

Therefore, by using the circuit of the present invention in a chip in which a large number of circuits of this type are used, the area occupied by the wiring can be greatly reduced compared to the conventional example.

As described above, the CMOS latch circuit of the present invention has one fewer element than the conventional CMOS latch circuit, and the wiring of the gate input circuit is also simplified, resulting in a smaller chip area.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the CMOS latch circuit of the present invention, FIG. 2 is a timing chart of input/output signals in the embodiment shown in FIG.
The figure is an input/output characteristic diagram of the inverter 1 in FIG. 1.

In this embodiment, the data input terminal (data input D)
, first and second gate input terminals (first and second gate input G,), a data output terminal (data output Q), and a power supply terminal (power supply voltage Vcc),
N-channel MOS FET Q ₁ whose source is grounded and whose gate is connected to the data input terminal; N-channel MOS FET Q ₅ whose source is grounded and whose gate is connected to the data output terminal; and
N-channel whose drain and gate are connected to the first gate input terminal of MOS FET Q ₁
MOS FET Q ₂ , an N-channel MOS FET Q ₆ whose source is connected to the drain of MOS FET Q ₅ , and whose gate is connected to the second gate input terminal;
There are two P-channel MOS FETs Q ₄ and Q ₇ whose sources are connected to the power supply terminal, and whose gates are connected to the data input terminal and data output terminal respectively, and a second P-channel MOS FET whose source is connected to the drain of MOS FET Q ₄ and whose gate is connected to the data input terminal and data output terminal, respectively. P channels connected to each gate input terminal
MOS FET Q ₃ and the input terminal is MOS FET Q ₂ ,
It has an inverter 1 connected to the drains of Q ₃ , Q ₆ , and Q ₇ and whose output terminal is connected to a data output terminal.

Next, the operation of this embodiment will be explained with reference to FIGS. 1 and 2.

Initially, assume that data input D is at "H" level and data output Q is at "L" level. At this time, MOS
FET Q ₇ is on and MOS FET Q ₅ is off. At time t ₁ , the first gate input G is “H” and the second
When the gate input of the MOS FET becomes “L”, the MOS FET
Q ₁ is on, MOS FETs Q ₂ and Q ₃ are also on,
MOS FET Q ₄ is turned off and current flows through MOS FET Q ₇ to MOS FETs Q ₁ and Q ₂ . Therefore, set the total on-resistance value of MOS FET Q ₁ and MOS FET Q ₂ to approximately 1/of the on-resistance value of MOS FET Q ₇ .
3 or less, at time _t2 , the input of inverter 1 becomes lower than the input voltage V _I at which the output voltage is inverted, as shown by the input/output characteristic curve in Figure 3, so the output data output from inverter 1 Q is inverted and becomes "H", MOS FET Q ₇ is turned off, the input of inverter 1 drops to O[V] (ground potential), and data output Q is held. the first at time t ₃
When the data input G of the gate is inverted to “L” and the second gate input is inverted to “H”, MOS FET Q ₂ and Q ₃ are turned off, MOS FET Q ₆ is turned on, and MOS FET Q ₅ is turned on.
is on, so the input of inverter 1 is O[V]
continue to hold. Next, even if the data input D is inverted to "L" at time _t4 , the MOS FETs _Q6 and _Q5 do not change and the data output Q is held as is. Next, when the data input D is "L" and the first gate input G becomes "H" and the second gate input G becomes "L" again at time _t5 , MOS FET Q ₄ turns on.
MOS FET Q ₁ off, MOS FET Q ₂ and Q ₃
is on, MOS FET Q ₆ is off, so MOS
Power supply voltage Vcc is applied through FET Q ₄ and Q ₃ , and the potential of the input of inverter 1 rises to “H”.
At time t ₆ , the data output Q of inverter 1 is inverted to “L”, MOS FET Q ₇ is turned on, and MOS
FET Q ₅ is turned off. Input of inverter 1 is Vcc
[V] and the data output Q holds 0 [V]. Next, at time _t7 , the first gate input G is “L”,
When the second gate input becomes “H”, the MOS
FET Q ₂ and Q ₃ are off, MOS FET Q ₆ is on but MOS FET Q ₅ is off, MOS FET Q ₇
Since it remains on, the input potential of inverter 1 is
Vcc [V], the data output Q continues to be held at 0 [V].

Note that the second gate input input to the gates of MOS FET Q ₆ and MOS FET Q ₅ and the feedback signal of data output Q may be exchanged, or the data output may be taken out from the input point of inverter 1. Alternatively, an additional inverter may be added as a buffer to extract the Q output from the input point of the inverter 1. Also,
In this example, MOS FETs Q ₁ , Q ₂ , Q ₅ ,
Although Q ₆ has been described as an N-channel type and MOS FETs Q ₃ , Q ₄ , and Q ₇ as a P-channel type, the former group may be a P-channel type and the latter group may be an N-channel type. When power supply voltage Vcc is applied to inverter 1 via MOS FETs Q ₃ and Q ₄ ,
Since MOS FET Q ₆ is turned off, MOS FET
The elements of Q ₃ and Q ₄ can be made smaller, and the input capacitance is also reduced.

〔Effect of the invention〕

As explained above, by adopting the circuit configuration of the claims, the number of circuit elements is reduced by one compared to the conventional one, and the C of the present invention
A chip that uses many MOS latch circuits has an N-channel MOS FET area and a P-channel MOS
Only three gate input wirings are required in the FET area, which occupies a smaller wiring area than the conventional one which required four, and both reduce the chip size in VLSI, which uses many latch circuits. In addition, since the capacitance of the first gate input is also reduced, faster C
This has the effect that a MOS latch circuit can achieve.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing an embodiment of the CMOS latch circuit of the present invention, Fig. 2 is a timing chart of the embodiment of Fig. 1, Fig. 3 is an input/output characteristic diagram of inverter 1, and Fig. 4 a. , b are explanatory diagrams showing the state of gate input wiring and the size of chips in the layouts of the conventional CMOS latch circuit and the present invention, respectively, and FIG. 5 is a circuit diagram of the conventional CMOS latch circuit. Q ₁ , Q ₂ , Q ₅ , Q ₆ ...N channel MOS FET,
Q ₃ , Q ₄ , Q ₇ ...P channel MOS FET, 1...
Inverter, D...Data input, G...First gate input,...Second gate input, Q...Data output, Vcc...Power supply voltage.

Claims (1)

[Claims] 1. A data input terminal D, and a first and second terminal to which signals having mutually opposite phases are input.
a gate input terminal G, a first and a second power supply terminal, a data output terminal Q, and a first FET of one conductivity type whose one end is connected to the first power supply terminal and whose gate is connected to the data input terminal. Q1, and a second FET of one conductivity type whose one end is connected to the other end of the first FET and whose gate is connected to the first gate input terminal G.
Q2, and a third transistor of the opposite conductivity type, one end of which is connected to the other end of the second FET and the second gate input terminal of the gate.
FET Q3, a fourth FET Q4 of opposite conductivity type, one end of which is connected to the other end of the third FET, a gate of which is connected to the data input terminal, and the other end of which is connected to the second power supply terminal; A fifth FET Q5 of one conductivity type whose gate is connected to the data output terminal or the second gate input terminal is connected to the power supply line, and one end is connected to the other end of the fifth FET and the gate is connected to the second gate input terminal. or a sixth conductivity type connected to the data output terminal.
FET Q6, opposite conductivity type FET Q7 whose one end is connected to the other end of the sixth FET, its gate to the data output terminal, and the other end to the second power supply terminal, and the second and third FETs. connection point and the 6th and 7th
1. A CMOS latch circuit comprising an inverting circuit 1 whose input end is connected to a connection point of a FET, and whose output is connected to a data output end.