JPH0378717B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sequential access control circuit for a semiconductor memory device having a serial access function.

[Conventional technology]

FIG. 8 is a circuit diagram showing an example of a conventional sequential access control circuit for a semiconductor memory device.
1 to RG4 are data registers, I0 is a data line,
Q1 to Q4 are transfer gates between the data register and data line, SR5 to SR8 are each unit circuit of the shift register, OUT1 to OUT4 are output signals from each unit circuit SR5 to SR8 of the shift register, φ1,
φ2 is a drive signal for the shift register that is applied alternately, and in this specification, φ1 is tentatively referred to as a first drive signal, and φ2 is referred to as a second drive signal. AD5～AD
8 is an address decoder, and SP5 to SP8 are outputs from the address decoder. data register
RG, shift register SR, address decoder AD
Each has a predetermined number of unit circuits connected in an array, but only a part of them is shown in FIG.

When the output signals OUT1 to OUT4 are sequentially set to logic "1" in the order of arrangement, Q1 to Q4 are sequentially turned on, and the data registers RG1 to RG4 are sequentially accessed from the IO. Which data register is accessed first in such serial access depends on which output among outputs SP5 to SP8 from the address decoder is at the "H" level. FIG. 9 is an operation time chart showing the operation of the circuit in FIG. 8, in which φ0 is the basic clock, t0 to t8 are each cycle number,
Other symbols indicate the same signals as the same symbols in FIG. In the example shown in Figure 9, the address decoder AD5
The output SP5 from is a logical ``1'' and therefore
The case where logic "1" signals are sequentially output from OUT1 to OUT4 is shown.

FIG. 10 is a circuit diagram showing the connection of each unit circuit SR5 to SR8 of the shift register shown in FIG. 8. In the figure, the same symbols as in FIG.
-Q20 are MOS transistors, N5 is an input node, N7 is an output node, and N8 is a node corresponding to N6 at the next stage when these shift registers are connected in series.

The drain of transistor Q13 is connected to input node N
5, the source of Q13 is connected to the drain of Q14 and the gate of Q15, and the gate of Q13 is connected to φ1.
, the gate of Q14 is connected to the output node N7, and the gate of Q15 is connected to the output node N7.
The drain of Q15 is connected to φ2, the source of Q15 is connected to the drain of Q16 and the drain of Q17, the gate of Q16 is connected to φ1, the source of Q17 is connected to the drain of Q18 and the gate of Q19, the gate of Q18 is connected to N8
, the drain of Q19 is connected to φ1, the source of Q19 is connected to the output node N7 and the drain of Q20, and the source of Q19 is connected to the drain of Q20.
The gate of 0 is connected to φ2, Q14, Q16, Q18,
The sources of Q20 are each connected to ground potential.

FIG. 11 is an operation time chart showing the operation of the circuit of FIG. 10, in which the same symbols as in FIG. 9 indicate the same signals, and represent the case where an "H" level signal is applied to input node N5. Regarding Figure 11, 1st
The operation of the circuit shown in Figure 0 will be explained. φ in t0 cycle
1 becomes “H” level and the “H” level of N5 becomes Q
13 to the drain of Q14 and the gate of Q15. Next, in the t1 cycle, when φ2 becomes "H", the node N6 becomes "H" and passes through Q17.
Gate 19 becomes "H". When φ1 becomes "H" in the next t2 cycle, node N7 becomes "H" due to Q19, turning on Q14 and grounding the gate of Q15. If N5 corresponds to SP5 in FIG. 9, N7 corresponds to OUT1 in FIG.
Since N7 is also connected to N5 of the next stage shift register, the gate of Q15 of the next stage shift register becomes "H" level at the time of t2 cycle, and after t3 cycle when φ2 becomes "H" level. φ
At cycle t4 (not shown in FIG. 11) when 1 becomes "H", the output node N7 of the next stage shift register becomes "H" level. In this way, OUT1, OUT2, OUT3, OUT in Figure 8
4 becomes "H" level one after another.

[Problem that the invention seeks to solve]

A conventional sequential access control circuit in a semiconductor memory device having a serial access function is configured as described above, and requires an address decoder corresponding to the number of stages of the shift register. For example, an address consists of an 8-bit binary signal,
Assuming that the shift register consists of 2 ⁸ = 256 stages of shift registers, the address decoder has 8 stages.
A bit binary signal is input and one of the 256 output signal lines (corresponding to each output such as SP5 and SP6 in Figure 8) is selected by the input address.
The address decoder must be used to bring the signal on the output signal line to the "H" level, and configuring this address decoder has the problem of increasing the area on the chip. Furthermore, as shown in FIG. 9, it takes two cycles to advance the shift register by one stage (for example, from OUT1 to OUT2 corresponds to t2 cycle, t3 cycle, and t4 cycle), making it difficult to increase the speed. There was a problem.

The present invention has been made to solve the above-mentioned problems, and aims to reduce the area of an address decoder on a chip and provide a semiconductor memory device that can be easily increased in speed.

[Means for solving problems]

In this invention, unit circuits in odd-numbered stages of a shift register and unit circuits in even-numbered stages following this odd-numbered stage are combined into one unit circuit.
The entire shift register is divided into a plurality of unit circuit pairs, and an address decoder selects a pair of unit circuits from all the unit circuit pairs. The shift register drive signal φ1 determines whether to select or even number stages.
The determination was made depending on which of φ2 is added first.

[Effect]

Using the numerical example explained earlier, if the address signal is 8 binary bits and the shift register has 256 stages, divide it into 128 pairs and remove the LSB (least significant bit) of the address signal. Since an address decoder is used that inputs a 7-bit signal and sets the signal logic to "1" on one signal line selected by the input 7 bits out of 128 output signal lines, the 8-bit signal outputs 256 The chip area can be formed much smaller than that of an address decoder that selects one of two output signal lines.
Furthermore, since the shift register can be advanced by one stage in one cycle, speeding up is possible.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of the present invention, where the same reference numerals as in FIG. pair,
SR3 and SR4 constitute the next pair of unit circuits. AD1, AD3 are address registers, SP1,
SP3 is the output of AD1 and AD3, respectively, and SP
1 is the output signal that selects the unit circuit pair of shift registers SR1 and SR2, SP3 is the shift register SR
3. This is an output signal for selecting the unit circuit pair of SR4.

FIG. 4 is a circuit diagram showing the connection of odd-numbered stage unit circuits (referred to as first type unit circuits in this specification) SR1 and SR3. In the figure, φ1 and φ2 are the same as φ1 and φ2 in FIG. Q5 to Q8 are MOS transistors, N1 is an input node, and in the case of SR1, output SP1 is input to input node N1, and SR3
In this case, the output SP3 is input to the input node N1. N2 is the output node, and in the case of SR1, the signal
Outputs OUT1, and in the case of SR3, outputs signal OUT3. Further, the output node N2 is connected to the input node N1 of the next stage shift register. Further, N3 indicates a connection from the output node of the next stage shift register. Further, in this specification, transistor Q7 is referred to as an output transistor.

FIG. 5 is an operation time chart showing the operation of each part of the circuit shown in FIG. 4. t0, t1, t2 are cycles corresponding to the same symbols in FIG. 9, and the same symbols as in FIG. 4 are the same signals. shows.

Assuming that a high level signal is given to N1 via SP1 in Figure 1, Q in cycle t0.
An "H" level signal is taken into the gate of Q7 through Q7. At this point, φ2 is at the "L" level and Q6 is in the off state. When φ2 goes to “H” level in the next t1 cycle, N2
becomes “H” level.

Figure 6 shows a unit circuit of an even number of stages of a shift register (referred to as a second type of unit circuit in this specification).
This is a circuit diagram showing the connection of SR2 or SR4. In the figure, the same symbols as in Fig. 4 indicate the same parts or the same signals, Q9 to Q12 are MOS transistors, and N
2 is the input node of SR2 connected to the output node of SR1 (or the SR connected to the output node of SR3
4 input node), N3 is the output node, N
4 is the output node of the next stage transistor. In the case of SR2, the output SP1 is input to the input node N2, and in the case of SR4, the output SP3 is input. Output node N3 outputs output OUT2 in case of SR2, outputs output OUT4 in case of SR4, and
This becomes the input node of the next stage shift register. Further, in this specification, the transistor Q11 is referred to as an output transistor.

FIG. 7 is an operation time chart showing the operation of each part of the circuit shown in FIG. 6, and t1 and t2 are t in FIG.
1 and t2, t3 is the cycle following t2, φ1 and φ2 are the same signals as the same symbols in FIG. 6, and N2 and N3 are the signals at points N2 and N3 in FIG. 6.

As shown in FIG. 5, node N2 is at "H" level in cycle t1, and φ2 is applied to the gate of Q9.
When is applied, the "H" level of N2 is applied to the gate of Q11 through Q9. At this point φ
1 is at the "L" level, and Q10 is in the off state. Next, when φ1 is added in the t2 cycle, an "H" level signal is output to N3 through Q11.

In the examples shown in Figures 5 and 7, RG1 is selected as the start position for serial access, so SR1,
The unit circuit pair of SR2 is the output SR of the address decoder.
1 and the first drive signal φ1 is added at the first cycle t0.
When the second drive signal φ2 is applied at 0, RG2 is selected as the start position. In other words, t in Fig. 7
If 1, t2, and t3 are regarded as t0, t1, and t2, respectively, then in the t0 cycle, the input node N2 has an output.
Since the “H” level signal of SP1 is applied, the “H” level signal is applied to the gate of Q11 in the t0 cycle, and the “H” level output OUT2 is output to N2 in the next t1 cycle, and the RG2 is accessed.

2 and 3 are operation time charts showing the operation of the circuit in FIG. 1, respectively. In these drawings, the same symbols as in FIG. 1 indicate the same signals, φ0 represents the basic clock, and t0 to t4. represents each cycle.

In FIG. 2, in the first cycle t0, the drive signal φ1
FIG. 3 shows the case where the drive signal φ2 is added in the first cycle t0.

If the address input specifies the start of serial access from RG1, φ1 is added in the t0 cycle as shown in Figure 2, and as shown in Figure 5,
As shown in Figure 7, in t1 cycle OUT1, t
OUT2 in 2 cycles, OUT in the same way
3, OUT4 is output.

If the address input specifies the start of serial access from RG2, as shown in Figure 3, φ2 is added in the t0 cycle, OUT2 is output in the t1 cycle, and OUT3,
When the shift register is configured with 256 stages, the output node of SR256 is connected to the input node of SR1, and the output is output in the order of OUT4.
OUT1 is output.

In the above embodiment, the shift register is N.
Although the case is shown in which it is configured with MOS transistors, it may also be configured with PMOS transistors or CMOS transistors.

〔Effect of the invention〕

As described above, according to the present invention, data can be accessed consecutively by the output of the address decoder that decodes the upper address excluding the least significant bit of the address signal that specifies the start position of serial access to the semiconductor memory device. Select a pair of unit circuits made up of two stages of unit circuits, and decide which unit circuit to start from after the pair of unit circuits depending on which drive signal of the shift register drive signal is applied first. I made it so that I could select it,
This has the effect that the area of the address decoder can be reduced and speeding up can be easily achieved.

[Brief explanation of drawings]

1 is a circuit diagram showing one embodiment of the present invention, FIGS. 2 and 3 are operation time charts showing the operation of the circuit in FIG. 1, and FIG. 4 is a first shift register of the shift register in FIG. 5 is an operation time chart showing the operation of the circuit in FIG. 4, and FIG. 6 is a circuit diagram showing the connection of the second type of unit circuit of the shift register in FIG. 1. Circuit diagram shown,
FIG. 7 is an operation time chart showing the operation of the circuit in FIG. 6, FIG. 8 is a circuit diagram showing a conventional device, and FIG.
The figure is an operation time chart showing the operation of the circuit in Fig. 8, Fig. 10 is a circuit diagram showing the connection of each unit circuit of the shift register shown in Fig. 8, and Fig.
An operation time chart showing the operation of the circuit shown in the figure. RG1 to RG4 are data registers, Q1 to Q4
are transfer gates, SR1 to SR4 are each unit circuit of the shift register, SR1 and SR2, SR3 and SR4 are each a pair of unit circuits, φ1 is the first drive signal, φ2 is the second drive signal, AD1 and AD3 are address decoders , Q7, and Q11 are output transistors. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A shift register configured by cascading multiple stages of unit circuits that hold "H" level or "L" level signals, to which a first drive signal and a second drive signal are applied alternately. means for shifting the signal held by each unit circuit of the shift register to the next stage unit circuit;
While controlling the signal held by only one unit circuit among the signals held by all the unit circuits of the shift register to be at the "H" level and the signals held by the other unit circuits to be at the "L" level, the "H" In a semiconductor memory device that has a function of serially accessing a storage element by sequentially shifting level signals within the shift register, the upper bits of the address signal specifying the start position of the serial access, except for the lowest one bit. An address decoder that decodes the address decoder, which constitutes a pair of unit circuits by two consecutive stages of unit circuits in the shift register, and the output of the address decoder is selected from among all the unit circuit pairs constituting the shift register. means for selecting one specified pair of unit circuits as a pair of unit circuits at a starting position; and means for transmitting the first drive signal or the second drive signal to the shift register according to the logic of the least significant bit of the address signal. A semiconductor memory device comprising: means for initially adding a drive signal. 2. The shift register is composed of a plurality of cascaded pairs of unit circuits in which a first type of unit circuit and a second type of unit circuit are cascaded. When the potential level of the input node is taken into the gate of the output transistor and the next second drive signal is applied to the drain of the output transistor, when the potential level of the input node is taken into the gate and the potential level of the input node is "H" level. , the potential level of the output node which is the source of the output transistor becomes "H" level, the input node of the second type of unit circuit is connected to the output node of the first type of unit circuit, and the second type of unit circuit is connected to the output node of the first type of unit circuit. The potential level of the input node is taken into the gate of the output transistor by the drive signal, and when the next first drive signal is applied to the drain of the output transistor, the potential level of the input node taken into the gate becomes " 2. The semiconductor memory device according to claim 1, wherein the potential level of the output node, which is the source of the output transistor, is at the "H" level only when the potential level is at the "H" level.