JPH0379799B2 - - Google Patents

Description

[Detailed Description of the Invention] This invention is a dynamic type MOS (metal-insulator-semiconductor) RAM (random
access memory). Dynamic MOSRAM (hereinafter referred to as D-RAM)
For example, an address buffer is provided in the periphery of an IC (integrated circuit) chip.
A plurality of memory arrays are provided approximately at the center of the IC chip, and address decoders such as a row decoder and a column decoder are provided corresponding to the memory arrays. A column decoder is arranged, for example, between two adjacent memory arrays. The output wiring of the address buffer is extended onto the IC chip around the memory array. However, the number of wires provided between the address buffer and the row decoder and between the address buffer and the column decoder is relatively large. Therefore, the wiring area that must be set up on the IC chip increases. The inventor of the present application has proposed the D-
Focusing on the fact that in RAM, address signals are input in a time-series manner, we considered using a common address signal line that should be provided between the address buffer and the decoder. An object of the present invention is to provide a dynamic MOSRAM that is highly integrated. Other objects of the invention will become apparent from the following description and drawings. Hereinafter, this invention will be explained in detail together with examples. FIG. 1 shows a circuit configuration diagram of a D-RAM according to an embodiment. The illustrated D-RAM includes eight memory arrays M-ARY1 each having memory cells arranged in 128 columns (rows) x 64 rows (columns), that is, a storage capacity of 8182 bits (8K bits), although this is not particularly limited. It has ~M~ARY8, and has a total storage capacity of approximately 64K bits. Note that the main blocks in this figure are drawn according to their geometrical arrangement on the actual IC chip. 128 decoder output signals obtained based on address signals A0 to A7 are applied to the row address selection lines (word lines) of each memory array M-ARY1 to M-ARY8. At this time, in order to shorten the wiring length of the word line in each memory array, that is, to reduce the propagation delay time of signal transmission from one end of the word line to the other end, a total of four row decoders R-DCR1 are installed.
~Row decoder R-DCR4 is connected to two adjacent memory arrays M-ARY1 and MARY3, respectively.
located between two memory arrays. Column decoder C-DCR receives address signal A
9 to A15, 128 decoded output signals are output. This column selection decode output signal is made common to the memory arrays arranged on the left and right sides of the column decoder C-DCR and to the adjacent upper and lower columns in each memory array, that is, to a total of four columns. Address signals A7 and A8 are assigned to select any one of these four columns. For example, A7 is assigned to left/right selection, and A8 is assigned to up/down selection. The φij signal generation circuit φij-SG decodes four combinations based on address signals A7 and A8, and the column switch selector CSW-SG switches columns based on its output signals φy00, φy01, φy10, and φy11. S1, CSW-S. In this way, the decoder for selecting the column of the memory array includes the column decoder C-DCR and the column switch selectors CSW-S1 and CSW-
It is classified into the second stage of S2. The purpose of dividing the decoder into two stages is, first, to prevent unnecessary blank areas from occurring within the IC chip. In other words, the NOR has a relatively large area and carries a pair of left and right output signal lines of the column decoder C-DCR.
The purpose is to match the vertical pitch of the gates with the column pitch of the memory cells.
That is, by dividing the decoder into two stages, the number of transistors forming the NOR gate can be reduced, and the area occupied by the NOR gate can be reduced. The second aim of dividing the decoder into two stages is to reduce the number of NOR gates connected to one address signal line, thereby lightening the load coupled to one address signal line, and The purpose is to improve switching speed. The row address buffer R-ADB converts the multiplexed and input 8-bit external address signals A0 to A7 into address strobe signals.
Internal timing signal φar formed according to RAS
By taking in the data, eight types of complementary address signals a0 to a7 are formed. Column address buffer C-ADB converts the multiplexed and input 8-bit external address signals A8 to A15 into address strobe signals.
Internal timing signal φac formed according to CAS
and form eight types of complementary address signals a8 to a15 , respectively. In this embodiment, in order to achieve high integration of the IC chip, a multiplexer MPX whose operation is controlled by the internal timing signals φar and φac is provided. The output of address buffer R-ADB and the output of address buffer C-ADB are sent out in time series to a common address signal line via multiplexer MPX. Therefore, the complementary address signals a0 to a7 and a8 to a15 are still multiplexed. In Figure 1, eight types of complementary address signal lines (column/row address lines) CR-
ADL is extended in the vertical direction (on the IC chip, the complementary address signal line is actually arranged so as to pass through approximately the center of the column decoder C-DCR). These address signal lines are
Since it is commonly used for the row selection address signals a0 to a7 and the column selection address signals a8 to a15, the wiring is simpler than when each is provided independently corresponding to the row and column. The number and occupied area are reduced by half. The column/row address line CR-ADL is connected between the 1st and 2nd columns and between the 3rd and 4th columns of the memory array.
Changeover switch SW installed near between the rows
The signal is branched in both left and right directions via , and is connected to row decoders R-DCR1 to R-DCR4. In this embodiment, the operation of the changeover switch SW is controlled by the timing signal φar so as to pass only the complementary row address signals a0 to a7 . The operation of the column decoder C-DCR itself is controlled by a column system timing signal φdf (column decoder control signal). Accordingly, multiplexed complementary column address signals a9 - a15 are separated from complementary address signals a0 - a6 . FIG. 2 shows a circuit diagram of a specific embodiment of the multiplexer MPX, column decoder C-DCR, row decoder R-DCR, and changeover switch SW. Multiplexer MPX and changeover switch
SW are transmission gate MOSFETs (insulated gate field effect transistors) Q1, Q2, and Q7, respectively.
It consists of Row address buffer R-
MOSFETQ1 that transmits the ADB output signal and the above
The timing signal φar is applied to the gate of MOSFET Q7, and the column address buffer C-
The timing signal φac is applied to the gate of MOSFET Q2 that transmits the output signal of ADB. Row decoder R-DCR is precharge
Configure a logic block with MOSFETQ8
It consists of a NOR gate circuit made up of MOSFETs Q9 and Q10. On the other hand, the column decoder C-DCR has a precharge similar to the above.
MOSFETQ3 and logic block MOSFETQ4,
Q5 and the above logic block MOSFET Q4,
Installed between the common source of Q5 and the ground point
Consists of MOSFETQ6. this
The timing signal φdf is applied to the gate of MOSFETQ6. Next, the circuit operation during the address setting process of the D-RAM will be explained with reference to the timing diagram of FIG. In accordance with the change of the address strobe signal to the low level, the timing signal φar is changed to the high level. By changing the timing signal φar to high level, the address buffer R-ADB
operates and as a result, the external address signal A0
~8 types of complementary address signals a0 corresponding to A7
~ a7 is formed. These complementary address signals a0 to a7 are sent to row decoders R-DCR1 to R-DCR1 through switch SW and a multiplexer MPX composed of MOSFETs Q1, Q7, etc., which are turned on by the high level of the timing signal φar.
4 can be conveyed. Next, as the word line selection timing signal φx rises to a high level, the word line selection signal formed by the four row decoders R-DCR is transmitted to the word line WL of the memory array. As a result, word line selection is performed. Next, prior to the input of column address signals A8 to A15, the timing signal φar is set to a low level. After waiting for the word line selection operation, the timing signal φpa is set to high level. The sense amplifier is activated by the high level of the timing signal φpa.
SA1 to SA8 become active, and the stored information read from the selected memory cell to the data line DL is amplified. Next, as the address strobe signal changes to low level, the timing signal φdf becomes high level. The column decoder C-DCR is
The power switch MOSFET Q6 therein is turned on by the timing signal φdf and becomes operable. The timing signal φac rises to high level a little later than the timing signal φdf, so that the address buffer R-ADB
is activated and external address signals A8 to A1 are activated.
8 types of complementary address signals a 8 to a corresponding to 5
15 is formed. This complementary address signal a8 ~
a15 is transmitted to the column decoder C-DCR through a multiplexer MPX composed of MOSFET Q2 and the like, which is turned on by the high level of the timing signal φac. At this time, since the timing signal φar is already at the low level and the changeover switch SWQ7 is off, the complementary address signals a9 to a15 are not applied to the row decoder R-DCR. The row address signals a0 to a6 are held at the inputs of the row decoder R-DCR. Next, when the column switch control signal φy rises to a high level, the φyij signal generating circuit φyij-SG is activated. Note that the complementary address signal a7 corresponding to the address signal A7 is generated by the φyij signal generation circuit when the timing signal φar becomes high level, and the address signal a8 is generated by the φyij signal generation circuit when the timing signal φac becomes high level. It is applied in advance to φyij−SG. Therefore, when the column switch control signal φy rises to a high level, almost at the same time, the φyij signal generation circuit φyij-SG sends column selection timing signals φy00 to φy11 to the column switch selectors CSW-S1 and CSW-S2. . In this way, column switch C-SW1,
One pair out of a total of 512 MOSFET pairs in C-SW2 is selected by the output of the decoder C-DCR and the φyij signal generation circuit. As a result, the pair of data lines DL in the memory array are connected via the selected pair of MOSFETs to the common data line pair CDL,
Connected to CDL. In the D-RAM of the above embodiment, since the address signal line to the row decoder R-DCR and the column decoder C-DCR can be shared, the IC chip can be highly integrated. By the way, by sharing the address signal line mentioned above, the area occupied by about 40 memory cells can be reduced in the horizontal direction, and 512 memory cells can be formed in the vertical direction as described above. In terms of memory cells as a whole, the area can be reduced by approximately 4K bits. Furthermore, in this embodiment, since address buffers are provided independently for row addresses and column addresses, the operation can be made faster. That is, it is conceivable that the address buffer may be used in common for the row address signal and the column address signal, but in this case, a precharge operation that takes a relatively long time would be required when taking in the column address signal. This is because the operation becomes slow. FIG. 4 shows a circuit diagram of another embodiment of the invention. In this example, the common data line is
Since there are a total of four lines running on the common data line CDL, and the read/write data signal is transmitted to the common data line CDL after the column address signal is sent to the column decoder C-DCR, The above common data line CDL,
CDL is also used in common with the address signal line CR-ADL. In this embodiment, as the common data line and address signal line are shared, it is necessary to add a latch function for the address signal, so the column decoder C-DCR is constructed using MOSFETs Q3 to Q
In addition to 5, the following circuit elements are added. NOR that constitutes the above column decoder C-DCR
The output of the gate is the newly installed transmission gate.
The signal is transmitted via MOSFETQ12 to the gate of MOSFETQ14 that constitutes the column switch selector CSW-S. And, at the gate of this MOSFETQ12,
A precharge MOSFETQ11 and a discharge MOSFETQ13 are provided, and the gate of the discharge MOSFETQ13 has the above-mentioned
A column switch selection timing signal φyij is applied through MOSFETQ14. Next, the operation of this embodiment circuit will be explained. When all the column address signals from the address signal line CR-ADL are at low level and their decoded outputs are at high level, when the timing signal φyij is supplied, the column switch C-SW
MOSFETQ15, 16 constituting the
Since MOSFETQ12 is turned on, MOSFETQ12 is turned off. Therefore, at the gate of MOSFETQ14,
The decoded output signal will be held.
Then, configure the above column switch C-SW.
When MOSFETQ15 and Q16 are turned on, at the time of reading, the read signal from the data line DL is transmitted to the address signal line CR-ADL, and the data output buffer (DOB in Fig. 1) (not shown) is transmitted to the address signal line CR-ADL.
During writing, the write data formed by the data input buffer (DIB in Figure 1), not shown, is applied to the address signal line CR-ADL.
and is transmitted to the data line DL. At this time, the data signal on the address signal line causes the column decoder C-DCR to
Even if the logic MOSFETs Q5, Q6, etc. constituting the MOSFET Q5 and Q6 are turned on, they are not affected by the turning off of the MOSFET Q12. In this embodiment, the common data line is also
Since it can be reduced by sharing it with the address signal line, it is possible to achieve higher integration of IC chips more quickly. The invention is not limited to the above embodiments. In addition to the above-mentioned 8-mat system, the memory array may have any configuration, such as a 4-mat system, as long as row address signal lines, column address signal lines, or these and common data lines run in parallel. . Furthermore, as the address signal lines are made common, it goes without saying that if precharging or resetting is necessary when transmitting different signals, a circuit for that purpose will be provided. Furthermore, the layout configuration and specific circuit configuration of the peripheral circuit can take various embodiments. That is, the present invention is widely applicable to multi-address D-RAMs.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a specific embodiment thereof, FIG. 3 is a timing diagram for explaining the address setting operation, and FIG. FIG. 4 is a circuit diagram showing one embodiment of the column decoder C-DCR. M-ARY1~8...Memory array, SA1~8
...Sense amplifier, D-ARY1-8...Dummy cell array, R-ADB...Row address buffer, C-ADB...Column address buffer, R
-DCR...Row decoder, C-DCR...Column decoder, CSW-S1~2...Column switch selector, C-SW1~2...Column switch,
MPX...Multiplexer, CR-ADL...Address signal line, φyij-SG...φyij signal generation circuit,
DIB...data input buffer, DOB...data output buffer, SW...changeover switch.

Claims (1)

[Claims] 1. A first address buffer and a second address buffer that receive multiplexed input address signals, and a second address buffer that receives output signals from the first and second address buffers. one address decoder and a second
Dynamic type with address decoder
In the MOSRAM, the first and second address buffers and the first and second address decoders are connected by a common address signal line, and the address signal line is connected to the first and second address decoders. The output signal of the buffer is transmitted in time series, and the timing of transmitting the output signal of the first address buffer is controlled by a first internal timing signal, and the output signal of the second address buffer is controlled by a first internal timing signal. The sending timing is controlled by a second internal timing signal formed from an external signal independent of the first internal timing signal, and between the address signal line and the input of the first address decoder. , the first internal timing signal causes the first internal timing signal to be output from the address signal line to the first internal timing signal.
A dynamic MOSRAM characterized by having a transmission gate circuit that controls transmission of signals to an address decoder. 2. The dynamic device according to claim 1, wherein input/output data signals for memory cells are also multiplexed and transmitted using a predetermined timing signal to the shared address signal line. Type MOSRAM.