JPH0380317B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] 2 ports for graphic display, etc.
This is a frame memory control device using RAM, and the refresh control unit includes a control means for automatically copying data in SAM (serial access memory) in 2-port RAM to all rows of RAM (random access memory). It was configured using the functions of

[Field of Industrial Application] The present invention relates to a frame memory for storing display data of a display device used in a graphic display or the like, and particularly to control of a frame memory using a two-port RAM.

2-port RAM inputs and outputs drawing data
This memory has a RAM side port and a video interface side port that can transfer one row of data in RAM and output it serially.

Therefore, it is equipped with a memory called SAM (serial access memory) that can be accessed both serially and in parallel and can store one row of data.

As a result, drawing can be performed even while the image is being displayed on the display, and the drawing time can be significantly reduced compared to the case where normal RAM is used.

The 2-port RAM has the function of transferring one row of data transferred onto the SAM to other rows. This function will be referred to as SAM copy here.

Clearing memory using the SAM copy function is much faster than clearing memory using a normal write operation. This is a necessary function when the screen is rewritten dozens of times per second, such as when displaying an animation.

The present invention relates to a control method for SAM copy.

[Prior art] Figure 4 shows the conventional technology for 2-port RAM.
FIG. 3 is a diagram showing related circuits for SAM copy control.

In Figure 4, 1 is a 2-port RAM,
RAM accessed in parallel by row address
101, and SAM10 that stores data for one row of RAM101 and can be accessed in parallel and serially.
It consists of 2.

To draw on the 2-port RAM 1, send the drawing address and drawing data to the 2-port RAM 1, input a drawing start signal, and send the drawing address and drawing data to the 2-port RAM 1.
This is done by inputting the access timing for drawing from .

When transferring display data to SAM102,
The refresh control section 3 is activated by the horizontal synchronization signal.

The refresh control unit 3 inputs the display address from the display address register (ADR2) 7 to the 2-port RAM.
1 and transfers the SAM transfer activation signal 1 to the memory access control unit 2 through the OR gate 8.

Memory access control unit 2 sends access timing for SAM transfer to 2-port RAM 1, and
SAM1 the line specified by the display address of 101
Transfer to 02.

The data transferred to the SAM 102 is serially read out, passed through the video interface 4, and input to the display 5 for display.

The refresh operation of RAM101 is normally as described above.
Following the SAM transfer, the refresh control unit 3 sends the refresh row address from the row address register (ADR1) 6 to the 2-port RAM 1, and sends a refresh start signal to the memory access control unit 2, thereby controlling the refresh Access timing is supplied and performed from the specified row.

When one refresh is completed, the address register (ADR1) 6 is sent from the refresh control unit 3.
The next refresh line address is created by counting up the contents of , and the refresh operation is performed again in the same way. This is executed the necessary number of times and the refresh operation is completed.

In the SAM copy operation, data for copying is first drawn in advance on the line to be copied, the address of the drawn line is sent to the 2-port RAM1 as the SAM copy address, and the SAM transfer start signal 2 is ORed.
It is sent to the memory access control section 2 through the circuit 8.

The memory access control unit 2 sends access timing for SAM transfer to the 2-port RAM 1,
Copy source row data of RAM101 to SAM1
Transfer to 02.

Next, the address of the 0th row is sent as a SAM copy address, and a SAM copy start signal is sent to the memory access control unit 2. This allows SAM
Access timing for copying is 2-port RAM
1, and the data of SAM102 is sent to RAM1.
Transferred to the 0th line specified by the SAM copy address of 01.

Next, the first address is sent as the SAM copy address, and a SAM copy activation signal is sent to the memory access control unit 2 to cause the transfer to the first row of the RAM 101. Similarly, RAM101
Transfer SAM102 data to all rows of
SAM copy processing ends.

[Problems to be Solved by the Invention] As explained above, in the conventional frame memory controller, there is a problem in that a lot of work is required to execute SAM copy processing, and during this time it is necessary to occupy the processor. The point was hot.

The present invention aims to provide a novel frame memory controller that solves these conventional problems.

[Means for Solving the Problems] FIG. 1 is a diagram showing the principle of the frame memory controller of the present invention. In FIG. 1, 1 is a two-port RAM, 3 is a refresh control section, and 6 is a row address register (ADR1).

Reference numeral 11 denotes address holding means, which holds the copy source and copy destination row addresses.

12 is the SAM copy control means 1, and the RAM
a first means for controlling to transfer data at a specified row address in the SAM to the SAM; a second means for controlling to set a row address and copy SAM data to the set row address; and third means for counting up addresses.

Reference numeral 13 denotes a SAM copy control means 2, which continues to send out SAM copy signals until the row address reaches its maximum value upon arrival of the SAM copy request signal.

In the controller shown in FIG. 1a, when the row address to be copied is set in address holding means 11 and the SAM copy request signal is input, the SAM
Three means of the copy control means 112 operate, first transferring the row address data held in the address holding means 11 to the SAM, and then setting "0" in the address holding means 11 to transfer the data in the SAM.
Copy to the 0th row of RAM, then count up the row address sequentially and copy to all rows.

In the controller shown in FIG. 1b, the refresh control unit 3 is provided with second, second and third means, and when a SAM copy request signal is input to the SAM copy control unit 213, the SAM copy signal is sent to the refresh control unit. In the refresh control section, the first, second, and third means operate based on this signal, and after transferring the row address data stored in the row address register 6 to the SAM, the data in the SAM is transferred to the RAM. Controls copying to each line of .

[Function] With the above configuration, if a SAM copy request signal is input, transfer from the specified line address to SAM,
Copying of SAM data to all row addresses is done automatically.

The controller shown in FIG. 1b utilizes the functions provided in the refresh control section, and can be implemented with a small amount of required hardware. This is SAM
This is because the copy execution cycle is fast and there is no need for refresh during this period, so most of the control circuits can be shared.

[Example] According to the example shown in FIGS. 2 and 3 below,
The present invention will be explained in more detail.

FIG. 2 is a diagram showing a SAM copy control related circuit according to the first embodiment of the present invention.

In FIG. 2, the objects indicated by numerals 1 to 9 are the same as those shown in FIG. 4, and the drawing operation, display SAM transfer operation, and refresh operation are the same as in the conventional example shown in FIG. be.

11 (ADR3) is a register that holds a row address for SAM copy.

Reference numeral 12 denotes a SAM copy control unit that performs control for SAM copy.

The SAM copy operation according to this embodiment will be explained below.

(1) First, the address of the row to be copied is set in advance in the address register (ADR3) 11 as a row designation address.

(2) Next, a SAM copy request signal is input to the SAM copy control unit 12 to start the SAM copy operation.

(3) The SAM copy control unit 12 sends the copy row address from the address register (ADR3) 11 to the 2-port RAM 1, and sends the SAM transfer activation signal 2.
Memory access control unit 2 through OR gate 8
send to

(4) Memory access control unit 2 sends the timing for SAM transfer to 2-port RAM 1, and
The data in the copy source row of 101 is SAM102
will be forwarded to.

(5) The SAM copy control unit 12 then sets the address register (ADR3) 11 to “0”,
The SAM copy start signal is sent to the memory access control unit 2, and the memory access control unit 2 sets the access timing for SAM copy to the 2-port RAM.
Supply to 1. 2 port RAM1 is RAM10
To the line at address “0” indicated by the copy line address of 1
Copy the data in SAM102.

(6) The SAM copy control unit 12 counts up the contents of the address register (ADR3) 11, specifies the next line, and sends the SAM copy start signal again to the next line of the RAM 101 in the 2-port RAM 1. Copy the data of SAM102.

(7) In this way, address register (ADR3) 11 sends out the last row address.
When the data of SAM102 is copied to all the rows of RAM101, SAM copy control unit 12
determines the completion of processing from the value of address register (ADR3) 11 and ends the SAM copy operation.

FIG. 3 is a diagram showing a SAM copy control related circuit according to a second embodiment of the present invention.

In FIG. 3, the objects indicated by numerals 1 to 9 are the same as those shown in FIG. 4, and the drawing operation, display SAM transfer operation, and refresh operation are the same as the conventional example shown in FIG. be.

Reference numeral 13 denotes a SAM copy control unit that performs control for SAM copy.

The SAM copy operation according to this embodiment will be explained below.

(1) First, copy data is drawn in advance on the line to be the copy source, and the address of the drawn line is set in the address register (ADR1) 6.

(2) Next, a SAM copy request signal is input to the SAM copy control unit 13 to start the SAM copy operation. SAM copy control unit 1
3 sends a SAM copy signal to the refresh control section 3 to activate the SAM copy operation.

(3) The refresh control unit 3 sends the row address of the address register (ADR1) 6 to the 2-port RAM 1, and sends a SAM transfer activation signal to the memory access control unit 2. The memory access control unit 2
2 ports access timing for SAM transfer
Send the data of the copy source row to RAM1.
Transfer to SAM102.

(4) Next, the refresh control unit 3 sets “0” to the access register (ADR1) 6,
The SAM copy start signal is sent to the memory access control unit 2, and the memory access control unit 2 sets the access timing for SAM copy to the 2-port RAM.
Send to 1. As a result, the data of SAM102 is transferred to the address register (ADR1) of RAM101.
It is copied to the line at address "0" pointed to by 6.

(5) The refresh control unit 3 then counts up the contents of the address register (ADR1) 6, designates the next line, and similarly executes SAM copy.

(6) Address register (ADR1) 6 sends the last row address to all rows of RAM 101.
Once the SAM102 data has been copied,
The SAM copy control unit 13 determines the completion of processing from the value of the address register (ADR1) 6, and
Ends the SAM copy operation.

[Effects of the Invention] As explained above, according to the present invention, most of the SAM copy processing that was conventionally performed by a processor can be executed automatically and at high speed.
Furthermore, by using a refresh control circuit, it can be realized with a small amount of hardware, and its practical effects are extremely large.

[Brief explanation of drawings]

FIG. 1 is a principle block diagram of the present invention, FIG. 2 is a diagram showing the SAM copy control related circuit of the first embodiment of the present invention, and FIG. 3 is a diagram of the second embodiment of the present invention.
FIG. 4 is a diagram showing a conventional SAM copy control related circuit. In the drawing, 1 is a 2-port RAM, 2 is a memory access control section, 3 is a refresh control section, and 4 is a 2-port RAM.
is the video interface, 5 is the display,
6, 7, 11 are address registers (holding means);
8 is an OR gate, 9 is a control gate, 12 and 13 are
SAM copy control unit (means), 101 is RAM, 1
02 indicates RAM.

Claims (1)

[Claims] 1. A RAM-side port that inputs and outputs drawing data;
Transfer and store one row of data in RAM
This is a frame memory control device configured with a 2-port RAM1 equipped with a SAM side port that can serially output data from SAM (serial access memory).
The first means of controlling the transfer to SAM is to set a row address, and to set the row address to the set row address.
A second means for controlling the copying of SAM data and a third means for counting up the row address is provided, and the data at the row address specified as the copy source is automatically transferred to the SAM, and the SAM data is RAM
A frame memory controller configured to perform copying control to all rows of a frame memory controller. 2. Equipped with address holding means 11 for holding copy source and copy destination line addresses, and the first, second and third means described above.
The frame memory controller according to claim 1, characterized in that it is configured to include SAM copy control means 112. 3 Continue sending SAM copy signals until the row address reaches its maximum value due to the SAM copy request signal.
A SAM copy control means 213 is provided, and the refresh control section 3 includes the first, second and third means, and during reception of the SAM copy signal, the first, second and third means are provided. The frame memory controller according to claim 1, characterized in that the frame memory controller is configured to operate.