JPH0381173B2 - - Google Patents

Description

[Detailed description of the invention]

[Overview] In floating-point addition and subtraction, a field is provided in the microinstruction to modify the operand address, and 2
To simplify digit alignment processing by controlling the reading order according to the magnitude relationship of exponent parts of two operands. [Industrial Application Field] The present invention relates to an arithmetic mechanism of a computer, and in particular to an indirect readout method of operands for digit alignment processing during floating point arithmetic. [Prior Art] When performing addition and subtraction in floating point format, it is first necessary to align the digits of the two operands to be operated. As shown in Figure 4, a floating-point format operand consists of three elements: a sign, an exponent, and a mantissa, and the mantissa is normalized (with leading zeros removed) and stored. There is. The digits of the two operands are aligned by comparing the exponents of both operands, and if there is a difference in exponents, right-shifting the mantissa of the operand with the smaller exponent. In this case, the actual processing is to prepare two types of addition/subtraction routines depending on the magnitude relationship of the exponent values of the two operands (the first operand and the second operand), and
It is necessary to use it depending on whether it is larger than the operand or vice versa, or to add a routine that swaps the first and second operands. In addition, in subtraction, if the exponent of the operand on the minuend side is small, if the subtraction is performed without exchanging the operands, it will become a negative number in complement representation, so it must be recomplemented to express it as an absolute value. There will be a number of steps. Next, a conventional floating point addition/subtraction method in which two types of addition/subtraction routines are switched will be described using the control flow shown in FIG. In Figure 5, the exponent parts of the first and second operands are e ₁ and e ₂ , and the exponent difference of e ₁ − e ₂ is
Let it be W ₁ . Below, each step indicated by 1 to 2 will be explained in order. Read the first operand. Read the second operand. Each exponent part of the first and second operand
Find the difference W ₁ between e ₁ and e ₂ . Determine whether the difference W ₁ is positive or negative, and if W ₁ is 0 ~
Execute the routine, and if W ₁ < 0, ~
Execute the routine. Since W ₁ is 0, the mantissa part of the second operand with the smaller exponent part is shifted to the right. The mantissa parts of the first and second operands are operated on. Store the calculation result and exit. Since W ₁ < 0, the shift amount is reversed and W ₁
←0−W ₁ . Shift the mantissa of the first operand to match the digits. The mantissa parts of the first and second operands are operated on. Store the calculation result and exit. [Problems to be solved by the invention] In conventional floating-point addition and subtraction, it is necessary to separate the addition and subtraction routines depending on the magnitude of the exponent parts of the two operands, or to switch operands, which makes it impossible to increase execution speed. This was one of the causes. [Means for Solving the Problems] The present invention modifies the indirect read addresses of the first and second operands with a microinstruction that reads the operands, and reads the exponent parts in order according to the magnitude relationship of the exponent parts. By always reading the operand with the smaller value first, the number of steps can be reduced. FIG. 1 is an apparatus configuration diagram for explaining the principle of the present invention. In the figure, numeral 11 is a machine instruction for activating the microprogram of this device, which is given, for example, by a CPU located above the device. OP
is the operation code, R _s is the first operand,
R _d is the second operand. 12 is an external memory space, which includes floating registers FR0 to FRn. Floating registers FR0 to FRn are upper
From the CPU's perspective, it appears to be addressed in memory space. Also, floating register FR0 is connected to this device.
~ When looking at FRn, only the mechanical commands indicated by R _d and _Rs appear as data images of R _d and _Rs on the internal memory space 15 via the access circuit 17 (this is indirect reading). ). 13 is a microinstruction that controls this device;
Contains internal address fields and flag control fields. The internal address field is a microinstruction operand specification field and specifies a register on the internal bus. Further, the flag control field is a field that controls the operand exchange control flag via the flag control circuit 19. 14 is an internal bus for data transfer within this device. 15 is the internal memory space of this device, R _d ,
Contains R _s data image, work registers, etc. 16 is a data processing unit, which processes data of R _d and _Rs . Includes ALU and various registers. 17 is an access circuit, which selects the first operand according to the operand exchange control flag 18;
The second operand select is controlled and specifies the floating register FR that appears at the address of the R _s image and the R _d image on the internal memory space 15. Reference numeral 18 denotes an operand swapping control flag, which represents a magnitude relationship based on the index difference between the first operand R _s and the second operand R _d , and specifies to the access circuit 17 whether or not to swap the operands. 19 is a flag control circuit, and microinstruction 1
When the update of the operand exchange control flag 18 is specified in the flag control field 3, the state of the operand exchange control flag 18 is determined by looking at the calculation result of the ALU of the data processing unit 16, and the index is updated from the R _s image address. The smaller operand of
The operand exchange control flag is set so that the operand with the larger index is read from the _Rd image address. [Operation] According to the present invention, when an operand is read for executing a mantissa operation by a microinstruction, the result of the preceding exponent comparison is reflected in the operand access, and if there is an exponent difference, the first The first operand and the second operand are read out in order of size, for example, the smaller one first. Therefore, there is no need to add a special operand exchange step, and the addition and subtraction routines can also be unified. FIG. 2 shows a flowchart of an example of floating point addition/subtraction control according to the present invention shown in FIG. Next, each step indicated by ˜ in the figure will be explained in order. Read the first operand R _s for exponent comparison. Similarly, the second operand _Rd is read. The exponent difference W ₁ = e _{s − e d is calculated for each exponent part e s , e d of} R s , R _d . If W ₁ is 0, turn off the operand exchange control flag 14,
Turn on if W ₁ <0. Read the smaller operand (effective second operand). Read the larger operand (effective first operand). Perform exponent calculation to find the difference W ₁ . Align the mantissa of the smaller operand based on W ₁ . Operates the mantissas of two operands. Store the results. [Embodiment] FIG. 3 shows the configuration of one embodiment of the system of the present invention. In the figure, 30 is an internal bus, 31 is a floating register FR consisting of a plurality of element registers FR-0 to FR-n in which each operand fetched from the main memory is temporarily stored, and 32 is an access circuit. 33 is an EOR circuit, 34 is an operand swapping control flag FLAG, 35 is an operand swapping control signal representing a magnitude relationship based on the index difference between two operands, and 36 is the first operand R _s
Operand selection signal R _d /R _s , 37 which specifies one of the second operand R _d and the second operand R d is element register FR-0 to FR- in floating register FR31.
FR select signal which jointly selects n with operand select signal 36, 38 is the operand output read from floating register FR. The access circuit 32 selects a pair of element registers in which the first and second operands R _s and R _d are stored in the floating register FR 31 using an FR select signal based on the operand address information of the microinstruction. , operand selection signal
Select R _s or R _d from R _d /R _s . The EOR circuit 33 inverts or non-inverts the value of the operand selection signal R d /R s based on the state of the exponent difference set in the operand exchange control flag FLAG 34, and inverts or non-inverts the value of the operand selection signal R _d /R _s . The reading order of the first operand and the second operand is changed or left unchanged. The operand exchange control flag FLAG34 is
Arithmetic unit (not shown) via internal bus
Set by the result of the preceding exponent comparison from . The control logic of the access circuit 32 is shown in the following table. This table represents the relationship between the values of the operand selection signal R _d /R _s and the operand exchange control flag FLAG, and the read operand output.

〔Effect of the invention〕

According to the present invention, operand swapping according to the direction of the exponent difference between two operands is executed on a hardware circuit using microinstructions.
Since no additional steps are required, and no recomplementation is required when there is an exponent difference during subtraction, execution speed can be improved.

[Brief explanation of drawings]

FIG. 1 is a basic configuration diagram of the present invention, FIG. 2 is a control flow diagram of floating-point addition/subtraction according to the present invention, and FIG.
FIG. 4 is a block diagram of an embodiment of the present invention, FIG. 4 is a block diagram of operands in floating point format, and FIG. 5 is a control flow diagram of conventional floating point addition/subtraction. In FIG. 1, 11...machine instruction, 12...external memory space, 13...microinstruction, 14...internal bus, 15...internal memory space, 16...data processing section, 17...access circuit, 18... Operand exchange control flag, 19... Flag control circuit, FR0 to FRn... Floating register,
R _s ...first operand, R _d ...second operand.

Claims (1)

[Claims] 1. An access circuit 17 that sequentially reads first and second operands to be operated on based on operand address information set in a microinstruction.
In a computer equipped with a floating point arithmetic operation, an operand switching control flag 18 is provided which is set with information representing the magnitude relationship of the result of comparing the exponent parts of the first and second operands, and the access circuit 17 controls the mantissa part. When reading the first and second operands for an operation, the operand address information of the microinstruction is changed according to the information of the operand swapping control flag 18, and the first and second operands are An indirect read method of operands in floating point arithmetic, characterized in that the operands are read in an order according to the magnitude relationship of exponent parts.