JPH038124B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a pulse detection circuit used in a pulse counting circuit.

[Technical background of the invention and its problems] Conventionally, pulse counting circuits have been used as follows.

One that determines whether the pulse count has reached a certain value, one that clears the pulse count when it reaches a certain value and repeats the counting again, one that determines the cumulative value of the number of pulses during a certain period, and multiple pulse signals. Calculate the ratio of two pulse counts under the same gate control, or by determining the counts of other counters while the counter reaches a preset count value or during the repetition period. There are some that are capable of various counting processes, such as those that do.

For these uses, each counter is equipped with a comparator, a preset value setter, and a comparison match detection circuit. This requires hardware such as a counter. Other applications include a configuration for controlling multiple counters, that is, a circuit that inputs the same gate control signal, or a circuit that controls the gate control signals of other counters at the time of comparison detection of one counter. Configuration is required. In this case, the configuration of the pulse counting circuit becomes particularly complex as the number of pulse signals increases.

Therefore, in order to simplify the hardware configuration, the present applicant developed a pulse counting circuit that can count multiple pulse signals by time-division processing using a set of counting processing devices (Patent Application No. 53). −120768
No. Specification).

In developing this pulse counting circuit, there is a demand for the development of a pulse detection circuit that can detect the input state of a pulse signal at regular intervals.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a pulse detection circuit capable of detecting the input state of a pulse signal at regular intervals.

[Summary of the Invention] In order to achieve the above object, there is provided a pulse detection means that outputs a pulse detection signal whose logical value is inverted every time a pulse signal is received, and a pulse detection means that outputs a pulse detection signal whose logical value is inverted every time a pulse signal is received, The memory that is written and retained by the hold signal and the pulse detection signal stored and retained by the previous hold signal are stored, and when there is a change compared to the pulse detection signal newly written by the current hold signal. and signal change detection means for outputting a detection signal of a predetermined logical value.

According to the present invention, it is possible to detect the input state of a pulse signal at regular intervals.

[Embodiments of the invention] A basic embodiment of the invention is shown in FIG.

In the figure, 1 is a pulse detection means such as a JK flip-flop circuit that inverts the logical value of the output pulse detection signal every time a pulse signal is input, and 2 and 3 are pulse detection means that output a pulse detection signal and a gate at the timing of a hold signal. Memories 4 and 5 each store the pulse detection signal and gate signal stored in the previous hold signal, and compare them with the newly stored pulse detection signal and gate signal in the current hold signal, respectively. The signal change detection means outputs a detection signal of a predetermined logical value when a change occurs.

In the above configuration, the pulse detection means 1 normally inverts its output at the rising edge or falling edge of the pulse signal. Further, the gate signal is a signal for controlling the start and stop of capturing the pulse signal. The hold signal is externally applied at a constant period shorter than the period of the pulse signal, so that the logic value of the pulse detection signal is allowed to change only once within one period of the hold signal. Therefore, when a pulse signal is input, the signal change detection means 4 detects a change in the pulse detection signal and outputs a detection signal of a predetermined logical value.
Output FP. Since this detection signal FP can be maintained for the period of the hold signal, it becomes possible to check the detection signal FP with an external device and perform pulse counting processing within this period. Furthermore, in this embodiment, since the gate signal is also stored at the same time and its changes are detected, it is also possible to count the pulse signals for a predetermined period.

FIG. 2 is a detailed circuit diagram specifically showing the pulse detection circuit of FIG. 1 mentioned above. In Figure 2, IC1 to IC5 are external clock synchronized JK flip-flops, IC6 and IC7 are exclusive OR circuits, and IC
8 is an inverter that inverts the logical value.

A power supply voltage VCC is applied to the input terminals J and K of the IC1, and the logic value of the output signal LP1 is inverted every time the pulse signal PULSE is input to the clock input terminal Cp. The outputs Q and Q of IC1 are input to the input terminals J and K of IC2, and the outputs Q and Q of IC2 are input to the input terminals J and K of IC2.
is configured to be input to the input terminals J and K of IC4, and the output signal LP2 of IC2 and the output signal of IC4
LP3 is input to IC6. The gate signal GATE is directly input to the input terminal J of the IC3, and the gate signal GATE via the inverter IC8 is input to the input terminal K of the IC3.
The outputs Q and Q of IC3 are input to the input terminals J and K of IC5, and the output signal LG1 of IC3 and the output signal of IC5
LG2 is input to IC7. A hold signal HLD is applied to each of the clock terminals Cp of IC2 to IC5.

In the above configuration, the operation mode when the pulse signal PULSE is input is shown in the time chart of FIG. As shown in the figure, the hold signal HLD
is input at a constant period shorter than the period of the pulse signal PULSE. The pulse signal PULSE is an independent pulse signal independent of the hold signal HLD.
It is input to IC1 as PULSE, and in this embodiment, the output signal LP1 of IC1 is inverted at the falling edge.

As shown in the figure, the time of occurrence of the hold signal HLD
When the output signal LP1 is inverted between t ₀ and t ₁ , the time t ₁
At time t2, the output signal LP2 is inverted, and at time _t2 , the signal LP3 is similarly inverted. Therefore, the detection signal FP, which is the output of the IC 6, outputs a logical value of "1" during the period between times _t1 and _t2 .

Thereafter, in the same way, every time the output signal LP1 is inverted, the detection signal FP is output, and P ₁ of the pulse signal PULSE is
Detection signals P ₁ ′ to P _{7 ′ corresponding to P 7 can} be obtained.

Further, a change in the gate signal GATE is transmitted to the output signal LG1 of IC3 at time _t0 by the hold signal HLD, and is transmitted to the output signal LG2 of IC5 at time _t1 . As a result, the output signal FGG of IC7 outputs a logical value of "1" during the period _t0 and _t1 .

Here, pulse signal PULSE and gate signal
Depending on the timing of GATE, signals FGG and FP may overlap, but signal LG1 (FG) is the hold signal one before the current gate signal GATE.
The state of the HLD can be determined, which allows the pulse signal to be
This is to determine whether PULSE should be counted or not. Also, the signal FGG is the gate signal GATE
This is to check whether there is a change in the gate signal GATE while . signal
FP is for determining whether the pulse signal PULSE is received.

Therefore, it is possible to completely understand the state of the input signal to be counted using these signals FGG and FP, and by checking these signals FGG and FP with an external device that operates in synchronization with the hold signal HLD. Pulse counting processing becomes possible.

Note that when the present invention is applied to a plurality of pulse input systems, pulse detection circuits corresponding to the pulse input systems are provided, and the signals of these pulse detection circuits are
By time-divisionally processing FGG and FP using, for example, a set of counting processors, multiple pulse signals can be generated.
It is also possible to count PULSE.

[Effects of the Invention] According to the present invention, it is possible to obtain a pulse detection circuit that can detect the input state of a pulse signal at regular intervals.

[Brief explanation of the drawing]

Figure 1 is a diagram for explaining one embodiment of the pulse detection circuit of the present invention, Figure 2 is a detailed circuit diagram of Figure 1, and Figure 3 is a time chart for explaining the operation of Figure 2. be. 1... Pulse detection means, 2, 3... Memory, 4, 5
...Signal change detection means.

Claims (1)

[Scope of Claims] 1. Pulse detection means that outputs a pulse detection signal whose logical value is inverted every time a pulse signal is received, and the pulse detection means is written with a hold signal having a cycle shorter than the cycle of the pulse signal. It holds the memory to store and the pulse detection signal stored in the previous hold signal, and detects a predetermined logical value when there is a change in comparison with the pulse detection signal newly written in the current hold signal. A pulse detection circuit comprising: a signal change detection means for outputting a signal; and a pulse detection circuit.