JPH0396222A - Forming method for single crystalline si film - Google Patents
Forming method for single crystalline si filmInfo
- Publication number
- JPH0396222A JPH0396222A JP23329189A JP23329189A JPH0396222A JP H0396222 A JPH0396222 A JP H0396222A JP 23329189 A JP23329189 A JP 23329189A JP 23329189 A JP23329189 A JP 23329189A JP H0396222 A JPH0396222 A JP H0396222A
- Authority
- JP
- Japan
- Prior art keywords
- film
- substrate
- base
- single crystalline
- amorphous
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910021419 crystalline silicon Inorganic materials 0.000 title abstract description 8
- 238000000034 method Methods 0.000 title description 16
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 39
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims abstract description 13
- 238000000137 annealing Methods 0.000 claims abstract description 6
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 25
- 239000007790 solid phase Substances 0.000 claims description 7
- 239000007864 aqueous solution Substances 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 3
- 239000000758 substrate Substances 0.000 abstract description 43
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 6
- 239000007787 solid Substances 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract 3
- 239000000377 silicon dioxide Substances 0.000 abstract 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 229910052682 stishovite Inorganic materials 0.000 abstract 3
- 229910052905 tridymite Inorganic materials 0.000 abstract 3
- 229960002050 hydrofluoric acid Drugs 0.000 abstract 2
- 238000007598 dipping method Methods 0.000 abstract 1
- 239000013078 crystal Substances 0.000 description 3
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000001125 extrusion Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000012071 phase Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 238000009835 boiling Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は、選択的にＳ ｉ Ｏ ！膜を形成した単結晶
Ｓｉ基板上のＳｉ基板面が露出している部分に、単結晶
Ｓｉ膜を形或する方法に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention selectively uses S i O ! The present invention relates to a method of forming a single crystal Si film on a portion of a single crystal Si substrate on which a film is formed, where the Si substrate surface is exposed.
（ロ）従来の技術
絶縁層（絶縁物の基板も含む）上に単結晶Ｓｉ層を形成
したものは、ＳＯ Ｉ （Ｓｉｌｉｃｏｎ ｏｎ Ｉｎ
ｓｕｌａｔｏｒ）構造と称され、狭い領域で容易に素子
分離が行え、高集積化や高遠化が可能なものとして知ら
れている。そして、従来のＳｉ基板上に素子が作製され
る半導体集積回路（ｒｃ）に比べて、特性向上が図られ
ることから盛んに研究開発が行われている。(b) Conventional technology A method in which a single crystal Si layer is formed on an insulating layer (including an insulating substrate) is SOI (Silicon on In).
It is known as a sulator structure, which allows elements to be easily separated in a narrow area, and allows for higher integration and height. Furthermore, research and development are being actively conducted on this semiconductor integrated circuit (RC), which has improved characteristics compared to conventional semiconductor integrated circuits (RC) in which elements are fabricated on a Si substrate.
絶縁層上に単結晶Ｓｉ膜を形成させるものの一つに、固
相エビタキシャル戒長法があり、これは、単結晶Ｓｉ基
板上に、Ｓｉ基板面の一部をシードとして露出させて絶
縁膜を形成し、シードと絶縁膜上に非晶質Ｓｉ（以下ａ
−Ｓｉと称する）膜を堆積し、６００℃程度の低温でア
ニールすることで、横方向に固相戊長させてａ−Ｓｉ膜
を単結晶化させるものである。One method for forming a single-crystal Si film on an insulating layer is the solid-phase epitaxial method, which involves forming an insulating film on a single-crystal Si substrate by exposing a part of the Si substrate surface as a seed. Amorphous Si (hereinafter a) is formed on the seed and insulating film.
-Si) is deposited and annealed at a low temperature of about 600° C., thereby elongating the solid phase in the lateral direction and converting the a-Si film into a single crystal.
しかし、この固相戊長では、＜ｉｏｏ＞方向の横方向に
優先的にａ−Ｓｉ膜の単結晶化が進むので、横方向の戊
長より先にシードから上への縦方向の戒長を必要とする
同相エビタキシャル成長ではシード上のａ−Ｓｉ膜をあ
まり厚くすることができず、つまりシードと絶縁膜表面
との段差を大きく取ることができない。However, in this solid phase elongation, single crystallization of the a-Si film progresses preferentially in the lateral direction in the In the in-phase epitaxial growth that requires , it is not possible to make the a-Si film on the seed very thick, that is, it is not possible to make a large step difference between the seed and the surface of the insulating film.
ところが、ａ−Ｓｉ膜が薄い場合に、シードと絶縁膜表
面との段差が大きい（絶縁膜が厚い）と、堆積されるａ
−Ｓｉ膜とシードの境の部分で段切れができたり、段切
れができなくても段差部分での内部応力が大きくなるた
め、横方向の固相戊長はほとんど起きないか、起きても
横方向威長距離はわずかとなる。However, when the a-Si film is thin and the step between the seed and the insulating film surface is large (the insulating film is thick), the deposited a
- A step break may occur at the boundary between the Si film and the seed, or even if a step break does not occur, internal stress increases at the step portion, so lateral solid phase elongation rarely occurs or even if it does occur. The lateral force distance is small.
このため、シードと絶縁膜表面との段差はできるかぎり
小さく、即ち絶縁膜を薄くする必要があり、通常１００
０λ以下に形成される。For this reason, it is necessary to make the step difference between the seed and the insulating film surface as small as possible, that is, to make the insulating film thinner, and the height difference is usually 100 mm.
It is formed below 0λ.
しかしながら、Ｓｏｔ構造を積層した三次元回路゛素子
を構戒する場合、絶縁膜層下にデバイスを形成すること
になるので、デバイス構造や配線及び電気的特性の安定
化のための保護を勘案すると、絶縁膜として約２ｐｍ以
上の膜厚が必要となる。However, when considering a three-dimensional circuit element with a stacked Sot structure, the device will be formed under an insulating film layer, so when considering protection for stabilizing the device structure, wiring, and electrical characteristics, , the insulating film needs to have a thickness of about 2 pm or more.
そこで、例えばｒｓＥＬＥｃＴＩＶＥ ＥＰＩＴＡＸＩ
ＡＬ ＧＲＯＷＴＨＯＦ ＳＩＬＩＣＯＮ ＢＹ Ｃ
Ｖ Ｄ ＡＮＤ ＩＴＳ ＴＨＥＲＭＯＤＹＮＡＭＩＣ
ＣＯＮＳＩＤＥＲＡＴＩＯＮＪ （ＰＲＰＣＥＥＤＩ
ＮＧＳ ＯＦ ＴＨＥ ＴＥＮＴＨＯＮＴＥＲＮＡＴＩ
ＯＮＡＬ ＣＯＮＦＥＲＥＮＣＥ ＯＮ ＣＨＥＭＩＣ
ＡＬ ＶＡＰＯＲ ＤＥＰＯＳＩＴＩＯＮ １９８７，
Ｐｒｏｃｅｅｄｉｎｇ Ｖｏ１．８７−８，ｐｐ３７９
−３８８）にある様に、選択的に開孔されたＳ ｉ Ｏ
＊膜を形成した単結晶Ｓｉ基板上へと、Ｓ ｔ Ｈ
ｓ Ｃ １ ｍ Ｈ Ｃ ｌ−Ｈ，の常圧ＣＶＤある
いは減圧ＣＶＤ法により、常圧の場合９５０℃乃至１０
５０℃、減圧の場合８５０℃乃至９５０℃の基板温度で
、露出しているＳｉ基板面上のみに単結晶Ｓｉ膜を戒長
させる選択的エビタキシャル成長方法が考えられている
。So, for example, rsELEcTIVE EPITAXI
AL GROWTHOF SILICON BY C
V D AND ITS THERMODYNAMIC
CONSIDERATIONJ (PRPCEEDI
NGS OF THE TENTHONTERNATI
ONAL CONFERENCE ON CHEMIC
AL VAPOR DEPOSITION 1987,
Proceedings Vo1.87-8, pp379
-388), selectively opened S i O
*S t H onto the single crystal Si substrate on which the film was formed.
s C 1 m H Cl-H, by normal pressure CVD or low pressure CVD method, at normal pressure from 950°C to 10°C.
A selective epitaxial growth method has been considered in which a single crystal Si film is grown only on the exposed Si substrate surface at a substrate temperature of 50° C. and 850° C. to 950° C. under reduced pressure.
また、その他に、選択的エビタキシャル威長方法として
、Ｓ ｉ Ｈ ａを用いたＣＶＤやＳｉＨ．をガスソー
スとするＭＢＥ法が考えられている。In addition, as a selective ebitaxial enhancement method, CVD using S i H a and SiH. An MBE method using the gas as a gas source is being considered.
（ハ）発明が解決しようとする課題
これら選択的エビタキシャル戊長方法では、戊長時に９
００℃前後以上の高温に基板を加熱する必要がある。こ
のような高温に基板を曝すと、絶縁膜下にＩｌ虞される
デバイスに悪影響を及ぼし、特性の劣化や破壊を招く虞
がある。(c) Problems to be solved by the invention In these selective ebitaxial extrusion methods, at the time of extrusion, 9
It is necessary to heat the substrate to a high temperature of around 00° C. or higher. Exposure of the substrate to such high temperatures may have an adverse effect on devices that may be exposed under the insulating film, leading to deterioration of characteristics or destruction.
また、戊長終了後の降温時に、Ｓｉｎｓ（絶縁膜）とＳ
ｉの熱膨張係数の差により、Ｓ ｉ Ｏ ｓ膜とＳｉ膜
とが接触する側壁部分の界面に応力が発生して、格子欠
陥を誘起する原因となる。この格子欠陥は、選択的に形
成したＳｊ膜上に更に形成する単結晶Ｓｉ膜の膜質を低
下させてしまう。Also, when the temperature decreases after the end of the boiling process, Sins (insulating film) and S
Due to the difference in thermal expansion coefficient of i, stress is generated at the interface of the sidewall portion where the SiOs film and the Si film are in contact, which causes lattice defects to be induced. These lattice defects degrade the quality of the single crystal Si film that is further formed on the selectively formed Sj film.
本発明は斯様な点に鑑みて為されたもので、選択的に開
孔されたＳｉＯｍ膜を形成した単結晶Ｓｉ基板上の、露
出しているＳｉ基板面上のみに低温で、Ｓｉｎｓ膜と同
じ厚みに単結晶Ｓｉ膜を形成する方法を提供するもので
ある。The present invention has been made in view of the above points, and it is possible to form a Sin film at a low temperature only on the exposed Si substrate surface on a single crystal Si substrate on which a selectively opened SiOm film is formed. The present invention provides a method for forming a single crystal Si film with the same thickness.
（二）課題を解決するための手段
本発明は、単結晶Ｓｉ基台上に基台表面の一部を露出さ
せて絶縁膜をＷＩ戊し、基台と絶縁膜表面上、にＳｉ分
子線を照射してａ−Ｓｉ膜を形成し、基台を加熱した後
、弗酸性水溶液に浸して絶縁膜上のａ−Ｓｉ膜を除去し
、基台上のａ−Ｓｉ膜をアニールにより固相戒長させる
単結晶Ｓｉ膜の形成方法である。(2) Means for Solving the Problems The present invention exposes a part of the surface of the base on a single crystal Si base, WIs the insulating film, and injects Si molecular beams onto the base and the surface of the insulating film. After heating the base, the a-Si film on the insulating film is removed by immersion in a hydrofluoric acid aqueous solution, and the a-Si film on the base is annealed to form a solid phase. This is a method for forming a single-crystalline Si film with a long-length structure.
（ホ）作用
絶縁膜上に形成したａ−Ｓｉ膜は、加熱すると、絶縁膜
とａ−Ｓｉ膜の熱膨張係数の違いによって、その界面で
弾性的な外力が作用して一部剥離する。そして、弗酸性
水溶液に浸すことにより絶縁膜上のａ−Ｓｉ膜だけが容
易に剥離する。その後、アニールすることによって、基
台上のＳｉ膜が結晶化する。(e) When the a-Si film formed on the functional insulating film is heated, elastic external force acts on the interface due to the difference in thermal expansion coefficient between the insulating film and the a-Si film, causing a portion to peel off. Then, by immersing it in a hydrofluoric acid aqueous solution, only the a-Si film on the insulating film is easily peeled off. Thereafter, by annealing, the Si film on the base is crystallized.
（Ｑ−）実施例 第１図Ａ乃至Ｇは本発明一実施例の概略工程図を示す。(Q-) Example FIGS. 1A to 1G show schematic process diagrams of one embodiment of the present invention.
本実施例では、単結晶基台として単結晶Ｓｉ基板を用い
ているが、絶縁基板等の基板上に形成された単結晶Ｓｉ
膜を用いてもよい。In this example, a single-crystal Si substrate is used as a single-crystal base, but a single-crystal Si substrate formed on a substrate such as an insulating substrate
A membrane may also be used.
（１）は（１０Ｇ）面を主面とする単結晶Ｓｉ膜基台と
しての単結晶Ｓｉ基板で、その表面に絶縁膜として膜厚
２μｍ程のＳｉＯ＝膜（２）をＣＶＤ法により堆積し、
更に公知の技術である７ォトリングラ７イ技術により、
シードとしてのＳｆ基板表面が露出する開孔部（２ａ）
を形成する（第１図Ａ）。(1) is a single-crystal Si substrate as a single-crystal Si film base with the (10G) plane as the main surface, and a SiO=film (2) with a thickness of approximately 2 μm is deposited on the surface as an insulating film by the CVD method. ,
Furthermore, by using the well-known technology 7photoringla7i,
Opening part (2a) where the surface of the Sf substrate as a seed is exposed
(Fig. 1A).
この基板を湿式化学処理である白木法により洗浄した後
、図示しないＭＢＥ装置内に基板をセットしてＩ Ｘ
１０−＠（乃至ＩＸＩＯ−’）程度の超高真空状態にす
る。そして、基板温度を８００℃に昇温保持して、３０
分間表面の清浄化を行う。After cleaning this substrate using the Shiraki method, which is a wet chemical treatment, the substrate was placed in an MBE device (not shown) and subjected to IX.
An ultra-high vacuum state of about 10-@ (to IXIO-') is created. Then, the substrate temperature was raised and maintained at 800°C, and
Clean the surface for minutes.
その後、基板温度を１００℃まで降温し、Ｅ−ガン（ｔ
子銃）を用いてＳｉ分子線を発生させ、基板表面（開孔
部（２ａ）において露出しているＳｉ基板（１）表面と
ＳｉＯ＝膜（２）上）に発生したＳｉ分子線を照射して
、基板表面上にａ−Ｓｉ膜（３）を堆積させる。この時
、ａ−Ｓｉ膜（３）の体積速度は５人／ｓｅｃで、Ｓｉ
Ｏ＝膜（２）と同じ厚さ、ほぼ２ｆｉｍ堆積させる（第
ｌ図Ｂ）。Ｅ−ガンにより発生させたＳｉ分子線の照射
によるａ−Ｓｉ膜の堆積では、基板に対してＳｉ分子は
ほぼ垂直に飛来するので、第１図Ｂのようにステップ力
バレッジは悪い。After that, the substrate temperature was lowered to 100°C, and the E-gun (t
Generate a Si molecular beam using a subgun) and irradiate the generated Si molecular beam onto the substrate surface (Si substrate (1) surface exposed in the opening (2a) and SiO = film (2)). Then, an a-Si film (3) is deposited on the substrate surface. At this time, the volume velocity of the a-Si film (3) is 5 persons/sec, and the
O = Deposit the same thickness as film (2), approximately 2 fim (FIG. 1B). When an a-Si film is deposited by irradiation with a Si molecular beam generated by an E-gun, the Si molecules fly almost perpendicularly to the substrate, so the step force barrier is poor as shown in FIG. 1B.
所望の厚さだけａ−Ｓｉ膜（３）を堆積したら、ＭＢＥ
装置内で、基板温度を４００℃（乃至５００℃）に昇温
し、３０分間保持する。すると、第１図Ｃに示す如く、
Ｓｉｎｓ膜（２）上に堆積したａ−Ｓｉ膜（３ｂ）の一
部が剥離する（第ｌ図Ｃ）。After depositing the a-Si film (3) to the desired thickness, MBE
Inside the apparatus, the substrate temperature is raised to 400° C. (or 500° C.) and held for 30 minutes. Then, as shown in Figure 1C,
A part of the a-Si film (3b) deposited on the Sins film (2) is peeled off (FIG. 1C).
清浄な室内で付着したＳｉ原子とＳｉＯ＝膜との結合力
は弱＜ （ＳｉＯ＝膜表面に活性な結合手がないためと
考えられる）、即ち、Ｓｉｎ．膜上に堆積したａ−Ｓｉ
膜の付着力は弱い。そして、ＳｉとＳｉＯ！の熱膨張係
数が違う（ Ｓ ｉ ： ２． ５Ｘ １０−’ｄｅｇ
−’Ｓ ｉｏ ｌ ： ０．３５Ｘ １０−’ｄｅｇ’
″ｌ）ため、昇温によりａ一Ｓｉ膜（３ｂ）とＳ ｉｏ
ｓ［ （ ２ ）との界面で弾性的な外力が作用して
、ａ−Ｓｉ膜（３ｂ）の一部が剥離する。The bonding force between Si atoms attached to the SiO film in a clean room is weak (possibly because there are no active bonds on the SiO film surface), that is, the SiO film has a weak bonding force with the Si atoms attached in a clean room. a-Si deposited on the film
The adhesion of the film is weak. And Si and SiO! The coefficient of thermal expansion is different (Si: 2.5X 10-'deg
-'SioI: 0.35X 10-'deg'
″l), due to temperature rise, the a-Si film (3b) and Sio
An elastic external force acts at the interface with s[ (2), and a part of the a-Si film (3b) peels off.
基板温度を室温まで降温したら、ＭＢＥ装置から基板を
取り出し、ｉｏ％程度の弗酸（ＨＦ）水溶液に十数秒浸
してＳｉｎ．膜（２）上のａ−Ｓｉ膜（３ｂ）を除去す
る（第１図Ｄ）。このとき、剥離によりできたＳｉｎ．
膜（２）とａ−Ｓｉ膜（３ｂ）の界面の隙間にＨＦが入
り込んで、ａ−Ｓｉ膜（３ｂ）は容易に除去される。ま
た、Ｓｉ基板（１）上に堆積したａ−Ｓｉ膜（３ａ）は
、下地の単結晶Ｓｉ基板との付着力が強く、ＨＦ水溶液
によって剥離することはない。After the substrate temperature has been lowered to room temperature, the substrate is taken out from the MBE apparatus and immersed in an aqueous solution of hydrofluoric acid (HF) of about io% for about ten seconds. The a-Si film (3b) on the film (2) is removed (FIG. 1D). At this time, the Sin.
HF enters the gap between the interface between the film (2) and the a-Si film (3b), and the a-Si film (3b) is easily removed. Furthermore, the a-Si film (3a) deposited on the Si substrate (1) has strong adhesion to the underlying single-crystal Si substrate, and will not be peeled off by the HF aqueous solution.
次に、基板を電気炉にセットし、窒素（Ｎ，）雰囲気中
で、６００℃、約１時間のアニール処理を行う。このア
ニール処理により単結晶Ｓｉ基板（１）上のａ−Ｓｉ膜
（３ａ）は、単結晶Ｓｉ基板（１）をシードとして、固
相戊長し単結晶Ｓｉ膜（３′）となる（第１図Ｅ）。Next, the substrate is set in an electric furnace, and annealing treatment is performed at 600° C. for about 1 hour in a nitrogen (N,) atmosphere. Through this annealing treatment, the a-Si film (3a) on the single-crystal Si substrate (1) undergoes solid phase elongation using the single-crystal Si substrate (1) as a seed to become a single-crystal Si film (3'). Figure 1 E).
斯様にして形成された単結晶Ｓｉ （３゜）膜とＳｉＯ
，膜（２）からなる基板の表面は、非常に平坦なものと
なっている。Single-crystal Si (3°) film and SiO formed in this way
, the surface of the substrate consisting of the film (2) is very flat.
そして、この基板表面上にＣＶＤ法等によりａ−Ｓｉ膜
（４）を堆積し（第１図Ｆ）、再びアニール処理をして
同相戒長を行わせ、ａ−Ｓｉ膜（４）を単結晶化させて
、Ｓ ｉ Ｏ ＊膜（２）上に単結晶Ｓｉ膜（４′）を
形成してＳＯＩ構造を得る（第ｌ図Ｇ）。Then, an a-Si film (4) is deposited on the surface of this substrate by a CVD method or the like (Fig. 1F), and annealing is performed again to perform in-phase lengthening to form a single a-Si film (4). By crystallization, a single crystal Si film (4') is formed on the S i O * film (2) to obtain an SOI structure (FIG. 1G).
（ト）発明の効果
本発明は、以上の説明から明らかなように、Ｓｉ分子線
を照射して堆積させたａ−Ｓｉ膜を加熱することにより
、その熱膨張係数の違いから、ＳｉＯ８膜上のａ−Ｓｉ
膜だけを容易に剥離することができる。この結果、Ｓ
＋ Ｏ ｔ膜の開孔部に、低温で、Ｓ ｉ Ｏ ＊膜と
同じ厚さだけ単結晶Ｓｉ膜を形成することができる。そ
して、低温のプロセスなので、Ｓｉｎ．膜下（単結晶Ｓ
ｉ基板）に構戊されるデバイスに悪影響を及ぼして特性
の劣化や破壊を招くことが避けられ、良好に三次元回路
素子を作製することが可能になる。(G) Effects of the Invention As is clear from the above description, the present invention is capable of heating an a-Si film deposited by irradiating Si molecular beams, thereby forming a film on a SiO8 film due to the difference in thermal expansion coefficient. a-Si
Only the film can be easily peeled off. As a result, S
A single-crystal Si film can be formed in the opening of the + O t film at a low temperature to the same thickness as the S i O * film. And since it is a low temperature process, Sin. Under film (single crystal S
It is possible to avoid adversely affecting the devices formed on the i-substrate (i-substrate) and causing deterioration or destruction of their characteristics, and it becomes possible to fabricate a three-dimensional circuit element in good condition.
第１図Ａ乃至Ｇは本発明一実施例の概略工程図である。 FIGS. 1A to 1G are schematic process diagrams of one embodiment of the present invention.
Claims (2)
絶縁膜を形成し、基台と絶縁膜表面上にＳｉ分子線を照
射して非晶質Ｓｉ膜を形成し、基台を加熱した後、弗酸
性水溶液に浸して絶縁膜上の非晶質Ｓｉ膜を除去し、基
台上の非晶質Ｓｉ膜をアニールにより固相成長させるこ
とを特徴とする単結晶Ｓｉ膜の形成方法。(1) Form an insulating film on a single crystal Si base by exposing a part of the base surface, and irradiate the base and the insulating film surface with a Si molecular beam to form an amorphous Si film, Single-crystal Si characterized by heating the base, removing the amorphous Si film on the insulating film by immersing it in a hydrofluoric acid aqueous solution, and growing the amorphous Si film on the base in a solid phase by annealing. How to form a film.
に形成することを特徴とする請求項１記載の単結晶Ｓｉ
膜の形成方法。(2) The single crystal Si film according to claim 1, wherein the amorphous Si film is formed to have approximately the same thickness as the insulating film.
How to form a film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23329189A JPH0396222A (en) | 1989-09-08 | 1989-09-08 | Forming method for single crystalline si film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23329189A JPH0396222A (en) | 1989-09-08 | 1989-09-08 | Forming method for single crystalline si film |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0396222A true JPH0396222A (en) | 1991-04-22 |
Family
ID=16952805
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23329189A Pending JPH0396222A (en) | 1989-09-08 | 1989-09-08 | Forming method for single crystalline si film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0396222A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007329200A (en) * | 2006-06-06 | 2007-12-20 | Toshiba Corp | Manufacturing method of semiconductor device |
-
1989
- 1989-09-08 JP JP23329189A patent/JPH0396222A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007329200A (en) * | 2006-06-06 | 2007-12-20 | Toshiba Corp | Manufacturing method of semiconductor device |
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