JPH0410248B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a method for transmitting large amplitude logic signals such as those handled by semiconductor logic circuits constructed using field effect transistors to semiconductor logic circuits constructed using bipolar transistors. This invention relates to improvements in logic signal amplitude conversion circuits that convert into small amplitude logic signals handled by logic circuits.

[Conventional technology]

Conventionally, a logic signal amplitude conversion circuit as described below with reference to FIG. 2 has been proposed.

That is, it is indicated by the symbol B, and for example, the potential of OV
A field effect transistor ₁ having a P-channel enhancement type and a resistor 2 are connected in that order between a power supply terminal E1 having a potential of V 1 and a power supply terminal E3 having a potential V ₃ of -2.0V, for example. connected in series, and a field effect transistor 1
An input terminal 3 is led out from the gate of , and an output terminal 4 is led out from the midpoint of the connection between the field effect transistor 1 and the resistor 2 .

According to the conventional logic signal amplitude conversion circuit B having such a configuration, the power supply terminal E1 and, for example, -
It has a semiconductor logic circuit A (the details of which are not shown) that operates on the power supply between the power supply terminal E2 and the power supply terminal E2 from which the potential V2 of _5.2V is obtained. A high potential close to the potential V ₁ between the potential V 1 of the terminal _E1 and the potential V ₂ of the power supply terminal E2
A large-amplitude logic signal that sets V _AH as "1" in binary display and the low potential V _AL between potentials V ₁ and V ₂ , which is lower than high potential V _AH , e.g. -5.2V, as "0" in binary display. shall be configured to output SA, and
If the large amplitude logic signal SA is given to the input terminal 3 of the logic signal amplitude conversion circuit B with a binary value of "0", that is, a low potential V _AL , it is given to the gate of the field effect transistor 1. As a result, the field effect transistor 1 is turned on, so that a high potential V _BH lower than the potential V ₁ of the power supply terminal E1 by the voltage drop across the field effect transistor 1 is obtained from the output terminal 4.

Further, from the output terminal 5 of the semiconductor logic circuit A, the above-mentioned large amplitude logic signal SA is displayed as "1" in binary display.
In other words, if a high potential V _AH is taken and applied to the input terminal 3 of the logic signal amplitude conversion circuit B, even if it is applied to the gate of the field effect transistor 1, in this case, the field effect transistor 1 will not turn on. , Therefore, a low potential V _BL approximately equal to the potential V ₃ of the power supply terminal E3 is obtained from the output terminal 4.

Therefore, for example, the power supply terminal _E1' from which the same OV potential _V1 ' as that obtained at the power supply terminal E1 can be obtained
and, for example, the same as obtained at power terminal E2 -
It has a semiconductor logic circuit C that operates on a power supply between the power supply terminal E2' and a power supply terminal E2' from which a potential V _{2 '} of 5.2V is obtained, and the semiconductor logic circuit C has the potential V2' of the power supply terminal E1' at its input terminal 6. ₁ ' and the potential V ₂ ' of the power supply terminal E2', for example, the high potential V _CH of -0.8V is displayed as "1" on the binary display, which is lower than the potential V _CH between the potentials V ₁ ' and V ₂ '. For example, if the low potential V _CL of -1.6V is set to "0" on a binary display, and the amplitude between "1" and "0" on a binary display |
V _CH −V _CL | is output terminal 5 of semiconductor logic circuit A
"1" and "0" of large amplitude logic signal S _A obtained by
The input terminal 6 of such a semiconductor logic circuit C is configured to operate by being supplied with a small amplitude logic signal SC having an amplitude smaller than |V _AH −V _AL |. Logic signal amplitude conversion circuit B
When supplying the output from _the output terminal _{4 of} Low potential C _CL with value display “0”
If the potential is set in advance to be approximately equal to the output terminal 4,
, a large amplitude logic signal given to input terminal 3
It is possible to output a small amplitude logic signal SB having a smaller amplitude than SA.

Therefore, according to the conventional logic signal amplitude conversion circuit B shown in FIG. It has a function of converting it into an amplitude logic signal SB.

[Problem to be solved by the invention]

However, in the case of the conventional logic signal amplitude conversion circuit B shown in FIG. 2, when the small amplitude logic signal SB obtained from the output terminal 4 is "1" in binary display, that is, obtained at the high potential V _BH , A large voltage is applied between the gate of the field effect transistor 1 and the source connected to the power supply terminal E1, and the field effect transistor 1 becomes conductive. It has temperature dependence in that the value of its equivalent conductance decreases as the temperature rises in inverse proportion to the square of . For this reason,
When the small amplitude logic signal SB obtained from the output terminal 4 is obtained at a high potential V _BH , the value of the high potential V _BH is
It decreases significantly as the temperature rises.

Therefore, in the case of the conventional logic signal amplitude conversion circuit B shown in FIG. 2, when the temperature rises, the output terminal 4
The high potential V _BH representing "1" in binary representation of the small amplitude logic signal SB obtained from 2 of the small amplitude logic signal SC to be supplied to the input terminal 6 of the semiconductor logic circuit C
There was a fear that the high potential V _CH , which represents "1" in the value display, would be obtained at a low value outside the allowable range, and the semiconductor logic circuit C would not operate as expected.

Furthermore, in the case of the conventional logic signal amplitude conversion circuit B shown in FIG. 2, the low potential V _BL representing "0" in the binary display of the small amplitude logic signal SB obtained at its output terminal 4 is
is determined by the potential V ₃ of the power supply terminal E3,
Since the potential V ₃ of the power supply terminal E 3 is obtained at a value almost equal to that potential V 3 , the potential V ₃ of the power supply terminal E 3 is a low value representing “0” in the binary representation of the small amplitude logic signal SC to be supplied to the input terminal 6 of the semiconductor logic circuit C. There was a restriction that the potential V _CL had to be within a possible range of values.

Therefore, the present invention seeks to propose a novel logic signal amplitude conversion circuit that does not have the above-mentioned drawbacks.

[Means to solve the problem]

The logic signal amplitude conversion circuit according to the present invention has the following configuration.

That is, a first field effect transistor having a first channel type and a first field effect transistor having one diode or a plurality of diodes connected in series are connected between the first power supply terminal and the second power supply terminal. a first diode circuit and a second field effect transistor having a second channel type opposite to the first channel type; They are connected in series with a polarity that is forward polarity relative to the power source obtained between the terminals.

Further, a first resistor is connected in parallel with the second field effect transistor.

Further, a third field effect transistor having a second channel type and a second resistor are connected in series in that order between the first power supply terminal and the third power supply terminal.

Further, in parallel with the third field effect transistor, a second diode circuit including one diode or a plurality of diodes connected in series connects the power source obtained between the first and third power terminals. It is connected with a polarity that is forward polarity.

Further, a gate of the third field effect transistor is connected to a midpoint between the first diode circuit and the second field effect transistor.

Furthermore, a common input terminal is led out from the gates of the first and second field effect transistors.

Furthermore, an output terminal is led out from a connection midpoint between the third field effect transistor and the second resistor.

The above is the configuration of the logic signal amplitude conversion circuit according to the present invention.

[Effect]

According to the logic signal amplitude conversion circuit according to the present invention having such a configuration, a large amplitude logic signal similar to that applied to the input terminal 3 of the conventional logic signal amplitude conversion circuit B described above in FIG. 2 is input to the input terminal. SA is
If it is given as "0" in binary display, that is, a low potential, the first and second field effect transistors turn on and off, respectively, and the gate of the third field effect transistor is connected to the first power supply terminal. A high potential lower than the potential by the sum of the voltage drop in the first field effect transistor and the voltage drop in the first diode circuit is applied, and the third field effect transistor is turned on, changing its state. keep it. Therefore, a high potential lower than the potential of the first power supply terminal by the voltage drop across the third field effect transistor can be obtained from the output terminal.

In addition, the above-mentioned large-amplitude logic signal is connected to the input terminal.
If SA is given as "1" in binary display, that is, a high potential, the first and second field effect transistors are turned off and on, respectively, and the second field effect transistor is connected to the gate of the third field effect transistor. A low potential approximately equal to the potential of the power supply terminal is applied, and the third field effect transistor is turned off. Therefore, a low potential that is lower than the potential of the first power supply terminal by the voltage drop in the second diode circuit is obtained from the output terminal.

Therefore, by appropriately selecting the potentials of the first, second, and third power supply terminals, the number of diodes in the first and second diode circuits, etc., it is possible to control the voltage applied from the output terminal to the input terminal. It is possible to output a small amplitude logic signal having a smaller amplitude than a large amplitude logic signal.

Therefore, the logic signal amplitude conversion circuit according to the present invention also functions as a logic signal amplitude conversion circuit, as in the case of the conventional logic signal amplitude conversion circuit described above with reference to FIG.

However, in the case of the logic signal amplitude conversion circuit according to the present invention, a small amplitude logic signal is output from the output terminal.
When a high potential is obtained that is lower than the potential of the first power supply terminal by the voltage drop in the third field effect transistor, the first field effect transistor and the first diode circuit are electrically connected, and the third The field effect transistor also conducts, but at this time, the first
As the temperature rises, the field effect transistor has an equivalent conductance that is inversely proportional to the square of the temperature, similar to the field effect transistor 1 in the conventional logic signal amplitude conversion circuit B described above in FIG. Even if the value of the equivalent conductance has a temperature dependence that decreases, the first
The diodes that make up the diode circuit are
Contrary to the case of the first field effect transistor, the equivalent conductance has a temperature dependence in which the value of the equivalent conductance increases as the temperature rises in a manner that is inversely proportional to the cube of the temperature. Therefore, the voltage applied to the gate of the third field effect transistor is lower than the potential of the first power supply terminal by the sum of the voltage drop in the first field effect transistor and the voltage drop in the first diode circuit. The value of the low high potential increases with increasing temperature.

Therefore, even if the third field effect transistor has a temperature dependence in its equivalent conductance, which decreases in value as the temperature rises, as in the case of the first field effect transistor, the Since the high potential applied to the gate of the field effect transistor No. 3 increases as the temperature rises, the high potential value of the small amplitude logic signal obtained from the output terminal may drop significantly as the temperature rises. It won't rise significantly.

Also, from the output terminal, a small amplitude logic signal is output from the first
When a low potential is obtained that is lower than the potential of the power supply terminal of the second diode circuit by the voltage drop in the second diode circuit, the value of the low potential is the voltage drop in the second diode circuit, and therefore the second diode circuit. Determined by the number of diodes in the configuration.

〔effect〕

From the above, according to the logic signal amplitude conversion circuit according to the present invention, a small amplitude logic signal obtained from its output terminal is constructed using a bipolar transistor that handles a small amplitude logic signal similar to that described above in FIG. Even if the high potential of the small-amplitude logic signal obtained from the output terminal is supplied to a semiconductor logic circuit configured using bipolar transistors, the high potential of the small-amplitude logic signal obtained from the output terminal will be High potentials are obtained with acceptable values. Therefore, there is no fear that a semiconductor logic circuit configured using bipolar transistors will not operate as expected even if the temperature rises.

Furthermore, when a small amplitude logic signal is obtained from the output terminal at a low potential, the value of the low potential is determined by the number of diodes constituting the second diode circuit. There is no restriction that the potential has to be within the possible range of the low potential of the small amplitude logic signal to be supplied to the input terminal of the semiconductor logic circuit configured using the above-mentioned bipolar transistor.

〔Example〕

Next, an embodiment of the logic signal amplitude conversion circuit according to the present invention will be described with reference to FIG.

In FIG. 1, parts corresponding to those in FIG. 2 are designated by the same reference numerals, and detailed description thereof will be omitted.

The logic signal amplitude conversion circuit B according to the present invention shown in FIG. 1 has the following configuration.

That is, the power supply terminal E1 from which the potential _V1 is obtained,
A field effect transistor _Q1 of the P-channel enhancement type and, for example, one diode 2 are connected between the power supply terminal E2 and the potential V2.
A diode circuit D1 consisting of 1 and an N channel
a field effect transistor Q2 having an enhancement type, in that order and a diode circuit D.
1 is connected in series with a polarity that is forward polarity with respect to the power source obtained between the power source terminals E1 and E2.

Further, a resistor R1 is connected in parallel with the field effect transistor Q2.

Furthermore, a field effect transistor Q3 having an N-channel depletion type is connected between the power supply terminal E1 and the power supply terminal E3 from which the potential _V3 is obtained;
and resistor R2 are connected in series in that order.

Further, a diode circuit D2 in which, for example, two diodes 22 are connected in series in parallel with the field effect transistor Q3 is connected to the power supply terminals E1 and E3.
With polarity that is forward polarity with respect to the power obtained between
It is connected.

Further, the gate of the field effect transistor Q3 is connected to the connection midpoint between the diode circuit D1 and the field effect transistor Q2.

Further, an input terminal 3 common to the field effect transistors Q1 and Q2 is led out from the gates of the field effect transistors Q1 and Q2.

Furthermore, field effect transistor Q3 and resistor R2
An output terminal 4 is led out from the midpoint of the connection.

The above is the logic signal amplitude conversion circuit B according to the present invention.
This is the configuration of the embodiment.

According to the logic signal amplitude conversion circuit B according to the present invention having such a configuration, the output of the semiconductor logic circuit A similar to that described above in FIG. The large-amplitude logic signal SA output from terminal 5 is at a low potential V _AL representing "0" in a binary display similar to that described above in FIG.
, then it is a field effect transistor Q
1 and Q2, the field effect transistors Q1 and Q2 are turned on and off, respectively, and the voltage drop across the field effect transistor _Q1 and the diode are applied to the gate of the field effect transistor Q3. A high potential that is lower by the sum of the voltage drop in the circuit D1 is applied, and the field effect transistor Q3 is turned on and maintained in that state. Therefore, a high potential V _BH lower than the potential V ₁ of the power supply terminal E1 by the voltage drop of the field effect transistor Q3 is obtained from the output terminal 4.

In addition, the above-mentioned large amplitude logic signal is input to the input terminal 3.
SA is "1" in the same binary display as described above in Figure 2.
If a high potential V _AH representing
2 are turned off and on, respectively, a low potential approximately equal to the potential V ₂ of the power supply terminal E2 is applied to the gate of the field effect transistor Q3, and the field effect transistor Q3 is turned off.

Therefore, a low potential V _BL is obtained from the output terminal 4, which is lower than the potential V ₁ of the power supply terminal E1 by the voltage drop in the diode circuit D2.

Therefore, we now have a semiconductor logic circuit C configured using bipolar transistors similar to those described above in FIG. 2, and supply the output from the logic signal amplitude conversion circuit B to its input terminal 6. In this case, the potential V ₃ of the power supply terminal E3 is, for example,
If the values are set in advance to be the same as those described above in FIG. , a small amplitude logic signal having a smaller amplitude (its value is |V _BH −V _BL |) than the large amplitude logic signal SA applied to input terminal 3.
SB can be output.

Therefore, in the case of the logic signal amplitude conversion circuit B according to the present invention shown in FIG. 1, as well as in the case of the conventional logic signal amplitude conversion circuit described above in FIG. Signal SA,
Small amplitude logic signals handled by semiconductor logic circuit C
It has the function of converting into a small amplitude logic signal SB similar to SC.

However, in the case of the logic signal amplitude conversion circuit B according to _the present invention shown in FIG. When a low high potential V _BH is obtained, the field effect transistor Q1 and the diode circuit D1 are conductive, and the field effect transistor Q3 is also conductive. At this time, the field effect transistor Q1 has an equivalent conductance as shown in FIG. Similar to the field effect transistor 1 in the conventional logic signal amplitude conversion circuit B described above, it has a temperature dependence in which the value of its equivalent conductance decreases as the temperature rises in inverse proportion to the square of the temperature. Even if the diode 21 constituting the diode circuit D1 has an equivalent conductance of
Contrary to the case of the field effect transistor Q1, the field effect transistor Q3 has a temperature dependence in which the value of its equivalent conductance increases as the temperature rises, in a manner inversely proportional to the cube of the temperature. The value of the high potential applied to the gate of the power supply terminal E1, which is lower than the potential _V1 of the power supply terminal E1 by the sum of the voltage drop in the field effect transistor Q1 and the voltage drop in the diode circuit D1, increases as the temperature rises. .

Therefore, the field effect transistor Q3 has an equivalent conductance of the field effect transistor Q3.
As in case 1, even if the field effect transistor Q3 has a temperature dependence in which the value of its equivalent conductance decreases as the temperature rises, the high potential applied to the gate of the field effect transistor Q3 increases as the temperature rises. Since the value is high, the value of the high potential V _BH of the small amplitude logic signal SB obtained from the output terminal 4 does not significantly drop or increase as the temperature rises.

Therefore, even if the small-amplitude logic signal SB obtained from the output terminal 4 is supplied to the semiconductor logic circuit C constructed using bipolar transistors that handle small-amplitude logic signals similar to those described above in FIG. , small amplitude logic signal SB obtained from output terminal 4
The high potential V _BH is obtained with a value within the permissible range of the high potential V _CH of the small amplitude logic signal SC to be supplied to the input terminal 6 of the semiconductor logic circuit C configured using bipolar transistors. Therefore, there is no fear that the semiconductor logic circuit C configured using bipolar transistors will not operate as expected even if the temperature rises.

Also, when the small amplitude logic signal SB is obtained from the output terminal 4 at the low potential V _BL mentioned above, the low potential
Since the value of V _BL is determined by the number of diodes 22 constituting the diode circuit D2, the potential V ₃ of the power supply terminal E3 is a small amplitude logic signal to be supplied to the input terminal 6 of the semiconductor logic circuit C. There is no restriction that the low potential V _CL of SC must be within the possible range of values.

[Brief explanation of drawings]

FIG. 1 is a connection diagram showing an embodiment of a logic signal amplitude conversion circuit according to the present invention. FIG. 2 is a connection diagram showing a conventional logic signal amplitude conversion circuit. E1, E1', E2, E2', E3...Power terminal, A, C...Semiconductor logic circuit, B...Logic signal amplitude conversion circuit, 1, Q1, Q2, Q3...Field effect transistor, 2, R1 , R2...Resistance, 3,
6...Input terminal, 4, 5...Output terminal, D1, D
2...Diode circuit.

Claims (1)

[Claims] 1 Between the first power terminal and the second power terminal,
a first field effect transistor having a first channel type; a first diode circuit consisting of one diode or a plurality of diodes connected in series; and a second field effect transistor having a first channel type;
a second field effect transistor having a channel type of a first resistor is connected in parallel with the second field effect transistor, and a third transistor having a second channel type is connected between the first power supply terminal and the third power supply terminal. A field effect transistor and a second resistor are connected in series in that order, and in parallel with the third field effect transistor.
A second diode circuit consisting of one diode or a plurality of diodes connected in series,
The gate of the third field effect transistor is connected with a polarity that is forward polarity with respect to the power supply obtained between the first and third power supply terminals, and
connected to a connection midpoint between the first diode circuit and the second field effect transistor; a common input terminal is led out from the gates of the first and second field effect transistors; A logic signal amplitude conversion circuit characterized in that an output terminal is led out from a connection midpoint between the field effect transistor and the second resistor.