JPH0410261B2 - - Google Patents
Info
- Publication number
- JPH0410261B2 JPH0410261B2 JP60165671A JP16567185A JPH0410261B2 JP H0410261 B2 JPH0410261 B2 JP H0410261B2 JP 60165671 A JP60165671 A JP 60165671A JP 16567185 A JP16567185 A JP 16567185A JP H0410261 B2 JPH0410261 B2 JP H0410261B2
- Authority
- JP
- Japan
- Prior art keywords
- data
- retransmission
- receiving side
- receiving
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Detection And Prevention Of Errors In Transmission (AREA)
Description
【発明の詳細な説明】
〔概要〕
データ送受信システムにおいて、受信側で受信
データのエラーを検出すると、受信側バツフアメ
モリの読出しを禁止すると共に受信側バツフアメ
モリの内容をクリアし、且つ、送信側バツフアメ
モリをクリアして再送データを書込み、受信側で
再送データを受信側バツフアメモリに格納後、読
出し禁止を解除することにより再送データの受信
側への到達時間の短縮を図つた再送データ送受信
方法。[Detailed Description of the Invention] [Summary] In a data transmission/reception system, when an error in received data is detected on the receiving side, reading of the receiving side buffer memory is prohibited, the contents of the receiving side buffer memory are cleared, and the sending side buffer memory is cleared. This retransmission data transmission/reception method aims to shorten the time it takes for the retransmission data to reach the receiving side by clearing and writing the retransmission data, storing the retransmission data in a receiving side buffer memory on the receiving side, and then releasing read prohibition.
本発明はデータ送受信システムにおける再送デ
ータ送受信方法及び装置に係り、特に画像データ
の伝送エラーに対応して送出する再送データの受
信側への到達時間の短縮を図つたバツフアメモリ
制御方式に関する。
The present invention relates to a retransmission data transmission/reception method and apparatus in a data transmission/reception system, and more particularly to a buffer memory control method for reducing the time required for retransmission data sent in response to an image data transmission error to reach a receiving side.
一般に、画像データ等の高速データの送受信
は、所定単位、例えばフレーム単位に行われる。
このために、所定単位のデータを格納する書き込
み順にデータが読み出される形式のバツフアメモ
リが送信側と受信側に共に設けられている。デー
タは通常、送信側からはDPCM等の差分データ
を符号化して受信側に送られる。受信側はこの差
分データを上記所定単位で受け取り、既に受信済
みのデータと合成して差分データをもとのデータ
に再生する。
Generally, high-speed data such as image data is transmitted and received in predetermined units, for example, in units of frames.
For this purpose, buffer memories are provided on both the transmitting side and the receiving side, which store a predetermined unit of data and are of a type in which data is read out in the order in which they are written. Data is usually encoded as differential data such as DPCM from the transmitting side and sent to the receiving side. The receiving side receives this difference data in the predetermined units, combines it with the already received data, and reproduces the difference data into the original data.
このように、受信側に受け取られるデータは差
分データなので、受信データに1ビツトでも伝送
路上で生じた誤りがあるとその後の再生データに
はエラーに差分が加算されて再生データ中のエラ
ーが次第に伝播してしまう。 In this way, the data received by the receiving side is differential data, so if even one bit of error occurs on the transmission path in the received data, the difference will be added to the error in the subsequent reproduced data, and the errors in the reproduced data will gradually disappear. It will spread.
これを防ぐために、受信データ中にエラーを検
出すると、受信部から送信部にデータ再送指示を
与え、送信部はこれを受けて前の画面によらない
正しいデータを送信側バツフアメモリを介して再
送するようにしている。 To prevent this, when an error is detected in the received data, the receiving section issues a data retransmission instruction to the transmitting section, and the transmitting section receives this and resends the correct data, which is not based on the previous screen, via the transmitting side buffer memory. That's what I do.
従来のデータ送受信方式においては、データ再
送指示に応じて正しいデータを送信側バツフアメ
モリに書込む場合、通常の送信データと同様にし
て書込んでいた。すなわち、送信側バツフアメモ
リに送信データを書込み中、あるいは送信側バツ
フアメモリから送信データを読出し中は、再送デ
ータの書込みは待機しており、上記送信データの
書込みあるいは読出しが終了後にはじめて再送デ
ータを送信側バツフアメモリに書込んでいた。そ
して受信側ではデータ再送指示の送出から再送デ
ータ中に含まれる再送指示データを検出する迄の
間に受信されたデータの読出しを禁止し、再送指
示データ検出後に再びデータを受信し解読して再
生していた。 In the conventional data transmission/reception system, when writing correct data to the transmitting side buffer memory in response to a data retransmission instruction, it was written in the same manner as normal transmission data. In other words, while writing transmission data to the sending buffer memory or reading transmission data from the sending buffer memory, writing of retransmitted data is on standby, and the retransmitted data is not written to the sending side until after writing or reading of the transmission data is completed. It was written to buffer memory. Then, on the receiving side, reading of the data received from the sending of the data retransmission instruction until the retransmission instruction data included in the retransmission data is detected is prohibited, and after the retransmission instruction data is detected, the data is received again, decoded, and reproduced. Was.
前述の如く、従来は、送信側バツフアメモリへ
の再送データの書込みは、受信側からの再送指示
があつてから、書込み中又は読出し中の通常の送
信データの書込み又は読出しの終了の後にはじめ
て行われるので、再送指示を発してから再送デー
タが受信側に到達する迄に要する時間が長すぎる
という問題点がある。特に、各々が1フレーム分
のデータを格納する送信側バツフアメモリを複数
個並置して送信データの読出しにおける待ち時間
をなくしてマルチバツフアメモリ構成において
は、再送データが受信側に到達する迄に複数フレ
ームの送信データが送出されることになり、上記
問題点は一層深刻になる。
As mentioned above, conventionally, retransmission data is written to the transmitting side buffer memory only after a retransmission instruction is received from the receiving side and after the normal transmission data writing or reading that is being written or read is completed. Therefore, there is a problem that the time required from issuing a retransmission instruction until the retransmission data reaches the receiving side is too long. In particular, in a multi-buffer memory configuration in which multiple transmitting side buffer memories, each storing one frame of data, are arranged in parallel to eliminate waiting time in reading out transmitted data, multiple transmitting side buffer memories are arranged in parallel to eliminate waiting time in reading out transmitted data. Since the transmission data of the frame is sent out, the above problem becomes even more serious.
上記の問題点を解決するために、本発明によ
り、データ送受信システムにおいて、受信側で受
信データにエラーを検出すると、書き込み順にデ
ータが読み出される受信側バツフアメモリの読出
しを禁止すると共に送信側および受信側の書き込
み順にデータが読み出されるバツフアメモリをク
リアして該送信側バツフアメモリに正しいデータ
である再送データを書込み、該受信側で該再送デ
ータを受信側バツフアメモリに格納後、読出し禁
止を解除することにより再送データを該受信側バ
ツフアメモリから読出すようにしたことを特徴と
する再送データ送受信方法が提供される。
In order to solve the above problems, the present invention provides a data transmission/reception system in which, when an error is detected in received data on the receiving side, reading of the buffer memory on the receiving side from which data is read out in the order of writing is prohibited, and both the sending and receiving sides Clear the buffer memory in which the data is read in the order in which they were written, write retransmission data that is correct data to the sending buffer memory, and then store the retransmitted data in the receiving buffer memory on the receiving side, and release the read prohibition to read the retransmitted data. There is provided a retransmission data transmission/reception method characterized in that the retransmission data is read from the receiving side buffer memory.
受信データ中のエラー検出に応じて送信側およ
び受信側のバツフアメモリをクリアすることによ
り、直ちに再送データを書き込むことができ、書
き込まれたデータを直ちに読み出すことができる
ので、データの再送が短時間に行われる。
By clearing the buffer memory on the sending and receiving sides in response to error detection in received data, retransmission data can be written immediately, and the written data can be read immediately, reducing data retransmission in a short time. It will be done.
以下、添付の図面に基づいて本発明の実施例を
説明する。同図に示される本発明の一実施例によ
るデータ送受信システムは、送信側Sと受信側R
からなつている。送信側Sはデータ発生部DG
と、第1のスイツチSW1と、3つの送信側バツ
フアメモリBM1,BM2およびBM3と、第2
のスイツチSW2と、送信側制御回路SCとを備え
ている。受信側Rは、第3のスイツチSW3と、
3つの受信側バツフアメモリBM4,BM5およ
びBM6と、第4のスイツチSW4と、データ受
信部DRと、受信側制御回路RCとを送信側及び受
信側のバツフアメモリは、すべて、書き込み順に
データが読み出される形式のバツフアメモリであ
る。送信側Sの第2のスイツチSW2と受信側の
第3のスイツチSW3とは伝送路Lにて接続され
ている。データ受信部DRはエラー検出回路EDを
備えており、データ発生部DGは初期化回路INI
を備えている。
Embodiments of the present invention will be described below based on the accompanying drawings. The data transmission/reception system according to an embodiment of the present invention shown in the figure includes a sending side S and a receiving side R.
It is made up of Sender S is data generator DG
, a first switch SW1, three transmitting side buffer memories BM1, BM2 and BM3, and a second switch SW1.
switch SW2 and a transmission side control circuit SC. The receiving side R includes a third switch SW3,
The three receiving-side buffer memories BM4, BM5, and BM6, the fourth switch SW4, the data receiving section DR, and the receiving-side control circuit RC are all buffer memories on the transmitting and receiving sides in a format in which data is read out in the order in which they are written. It is a buffer memory. A second switch SW2 on the sending side S and a third switch SW3 on the receiving side are connected by a transmission line L. The data receiving section DR is equipped with an error detection circuit ED, and the data generating section DG is equipped with an initialization circuit INI.
It is equipped with
エラー検出回路EDが受信データ中にエラーを
検出していないときは、データ発生部DGはデー
タ受信部DRにおいて前回再生された1画面のデ
ータとの差分のデータを第1のスイツチSW1を
介して送信側バツフアメモリBM1,BM2、お
よびBM3のいずれか1つに書込む。送信側制御
回路SCは送信側バツフアメモリBM1,BM2、
およびBM3における書込みまたは読出しのタイ
ミングを制御すると共に、第1および第2のスイ
ツチSW1およびSW2を制御して、送信側バツ
フアメモリBM1,BM2、およびBM3のいず
れか1つに送信データを書込み中は、残りの送信
バツフアメモリの1つから、既に書込まれている
送信データを伝送路Lに読出すようにしている。 When the error detection circuit ED detects no error in the received data, the data generation unit DG transmits the difference data from the data of one screen that was reproduced last time in the data reception unit DR via the first switch SW1. Write to any one of the sending side buffer memories BM1, BM2, and BM3. The transmitting side control circuit SC includes transmitting side buffer memories BM1, BM2,
While controlling the write or read timing in BM3 and controlling the first and second switches SW1 and SW2 to write transmission data to any one of the transmitting side buffer memories BM1, BM2, and BM3, Transmission data that has already been written is read out onto the transmission path L from one of the remaining transmission buffer memories.
受信側では受信側制御回路RCの制御の下に、
伝送路Lを伝送されて来たデータを第3のスイツ
チSW3を介して受信側バツフアメモリBM4,
BM5,BM6のいずれかに書込むと共にBM4,
BM5,BM6からスイツチSW4を介して順次
データ受信部DRに読出す。データ受信部DRは
受信データをデコードして画面データを再生す
る。 On the receiving side, under the control of the receiving side control circuit RC,
The data transmitted through the transmission line L is sent to the receiving side buffer memory BM4 via the third switch SW3.
While writing to either BM5 or BM6, BM4,
The data is sequentially read from BM5 and BM6 to the data receiving unit DR via switch SW4. The data receiving unit DR decodes the received data and reproduces screen data.
エラー検出回路EDが受信データ中にエラーを
検出したときの動作を次に説明する。 The operation when the error detection circuit ED detects an error in received data will be described next.
エラー検出回路EDは、受信データにエラーを
検出すると、受信側制御回路RCに読出し禁止信
号(INH)を与え、それにより該受信側制御回
路RCは第4のスイツチSW4をオフにして受信
側バツフアメモリBM4,BM5、およびBM6
からデータ受信部DRへのデータの読出しを禁止
する。エラー検出回路EDはまた、エラー検出に
応じてデータ発生部DG内の初期化回路INIにデ
ータを再送要求信号(DREQ)を送る。受信側制
御回路RCはまた、エラー検出回路EDから読出し
禁止信号(INH)を受け取ると、受信側バツフ
アメモリBM4,BM5、およびBM6の内容を
クリアする。 When the error detection circuit ED detects an error in the received data, it gives a read inhibit signal (INH) to the reception side control circuit RC, which causes the reception side control circuit RC to turn off the fourth switch SW4 and close the reception side buffer memory. BM4, BM5, and BM6
Prohibits data reading from the data receiving unit DR. The error detection circuit ED also sends a data retransmission request signal (DREQ) to the initialization circuit INI in the data generation unit DG in response to error detection. When the receiving side control circuit RC also receives a read inhibit signal (INH) from the error detection circuit ED, it clears the contents of the receiving side buffer memories BM4, BM5, and BM6.
初期化回路INIは、エラー検出回路EDから上
記データ再送要求信号(DREQ)を受け取ると、
再送データを作成すると共に、送信側制御回路
SCに初期化指示信号(INI2)を与える。再送デ
ータは既に送出したデータとの差分データではな
い1フレーム分の正しいデータであり、且つ、再
送データであることを示す再送指示ビツトを含ん
でいる。 When the initialization circuit INI receives the data retransmission request signal (DREQ) from the error detection circuit ED,
In addition to creating retransmission data, the transmitter control circuit
Give the initialization instruction signal (INI2) to the SC. The retransmission data is correct data for one frame, not difference data from data that has already been transmitted, and includes a retransmission instruction bit indicating that it is retransmission data.
送信側制御回路SCは、上記初期化指示信号
(INIC2)を受け取ると、送信側バツフアメモリ
BM1,BM2、およびBM3のすべてを直ちに
クリアした後に、例えば送信側バツフアメモリ
BM1に初期化回路INIからの再送データを書込
むべく第1のスイツチSW1を制御する。送信側
制御回路SCはまた、第2のスイツチSW2を制御
して、上記再送データをBM1に書込み後直ちに
そこから読出して伝送路Lに送出する。 When the transmitting side control circuit SC receives the above initialization instruction signal (INIC2), the transmitting side buffer memory
After immediately clearing all BM1, BM2, and BM3, e.g.
The first switch SW1 is controlled to write retransmission data from the initialization circuit INI to BM1. The transmission side control circuit SC also controls the second switch SW2 to read the retransmission data from there immediately after writing it to the BM1 and send it to the transmission line L.
受信側Rでは、再送指示検出回路Dが再送デー
タ中の再送指示ビツトを検出すると受信側制御回
路RCに再送指示検出信号(D)を与え、それに
より受信側制御回路RCは第3のスイツチSW3
を制御して伝送路Lからの再送データを直ちに、
例えば受信側バツフアメモリBM4に書込む。受
信側制御回路RCは、BM4に再送データを書込
み終了後、信号(INI1)によりデータ受信部
DRへ再送データ準備完了を通信し、第4のスイ
ツチSW4を制御して読出し禁止を解除し、BM
4から再送データをデータ受信部DRに読出す。 On the receiving side R, when the retransmission instruction detection circuit D detects the retransmission instruction bit in the retransmission data, it gives a retransmission instruction detection signal (D) to the receiving side control circuit RC, which causes the receiving side control circuit RC to switch the third switch SW3.
to immediately retransmit data from transmission line L.
For example, it is written to the buffer memory BM4 on the receiving side. After the receiving side control circuit RC finishes writing the retransmission data to BM4, the receiving side control circuit RC controls the data receiving section by a signal (INI1).
Notifies the DR that the retransmission data is ready, controls the fourth switch SW4 to cancel the read prohibition, and then sends the BM
4, the retransmission data is read out to the data receiving unit DR.
以上の実施例によれば受信部で受信データにエ
ラーを検出すると直ちに、送信側バツフアメモ
リ、受信側バツフアメモリ共にクリアするように
したので、読出し中あるいは書込み中のバツフア
メモリの動作の終了を待つ必要なしに、且つバツ
フアメモリに既に格納されているデータの読み出
し終了を待つ必要なしに、直ちに再送データの書
込みおよび読出しができる。 According to the above embodiment, as soon as the receiving section detects an error in the received data, both the transmitting side buffer memory and the receiving side buffer memory are cleared, so there is no need to wait for the completion of the buffer memory operation being read or written. , and retransmission data can be written and read immediately without having to wait for the completion of reading data already stored in the buffer memory.
なお、本発明は上記の実施例に限定されるもの
ではなく、例えばバツフアメモリの数は送信側、
受信側共に任意の数でよい。 Note that the present invention is not limited to the above embodiments; for example, the number of buffer memories may vary depending on the transmitting side,
Any number may be used on both receiving sides.
以上の説明から明らかなように、本発明によれ
ば、データ送受信システムにおいて、受信データ
中にエラーを検出したとき、送信側および受信側
のバツフアメモリをクリアした後に再送データを
送出するようにたので、エラー検出から再送デー
タが受信側に到達する迄の時間が短縮され、特に
画像データ伝送において誤りを含む画面が表示さ
れる時間を短縮できるという効果が得られる。
As is clear from the above description, according to the present invention, when an error is detected in received data in a data transmission/reception system, retransmission data is sent after clearing the buffer memories on the transmitting side and the receiving side. The time from error detection to the time when retransmitted data reaches the receiving side is shortened, and in particular, the time during which a screen containing an error is displayed during image data transmission can be shortened.
添付の図面は本発明の一実施例による再送デー
タ送受信方式を説明するためのブロツク図であ
る。
S…送信側、R…受信側、DG…データ発生
部、INI…初期化回路、BM1〜BM3…送信側
バツフアメモリ、SC…送信側制御回路、DR…デ
ータ受信部、ED…エラー検出回路、BM4〜BM
6…受信側バツフアメモリ、RC…受信側制御回
路、D…再送指示検出回路。
The accompanying drawing is a block diagram for explaining a retransmission data transmission/reception system according to an embodiment of the present invention. S...Sending side, R...Receiving side, DG...Data generation section, INI...Initialization circuit, BM1 to BM3...Sending side buffer memory, SC...Sending side control circuit, DR...Data receiving section, ED...Error detection circuit, BM4 ~BM
6... Receiving side buffer memory, RC... Receiving side control circuit, D... Retransmission instruction detection circuit.
Claims (1)
信データにエラーを検出すると、書き込み順にデ
ータが読み出される受信側バツフアメモリの読み
出しを禁止すると共に送信側および受信側の書き
込み順にデータが読み出されるバツフアメモリを
クリアして該送信側バツフアメモリに正しいデー
タである再送データを書込み、該受信側で該再送
データを受信側バツフアメモリに格納後、読出し
禁止を解除することにより再送データを該受信側
バツフアメモリから読出すようにしたことを特徴
とする再送データ送受信方法。 2 送信側に、データ発生手段と、該データ発生
手段からの送信データを格納する送信側メモリ
と、該送信側メモリに対するデータの書込み/読
出しを制御する送信側制御手段を具備し、受信側
に、該送信側メモリからのデータを格納する受信
側メモリと、該受信側メモリからのデータを受信
するデータ受信手段と、該受信側メモリに対する
データの書込み/読出しを制御する受信側制御手
段とを具備し、該送信側メモリ及び該受信側メモ
リはそれぞれ、書き込み順にデータが読み出され
るものであるデータ送受信システムにおいて、 該データ受信手段はエラー検出手段を具備し、
該エラー検出手段は、受信データのエラーを検出
すると該受信側制御手段の制御の下に該受信側メ
モリから該データ受信手段へのデータ読出しを禁
止させると共に該受信側メモリをクリアし、且
つ、該データ発生手段にデータ再送要求信号を送
るものであり、 該データ発生手段は、初期化手段を具備し、該
初期化手段は、該データ再送要求信号に応答して
再送指示検出データを含む正しいデータである再
送データを作成すると共に、該データ再送要求信
号に応答して該送信側制御手段の制御の下に該送
信側メモリをクリアした後に該再送データを該送
信側メモリに書込むものであり、 該受信側は、該送信側メモリから送られて来た
該再送データから該再送指示検出データを検出す
る再送指示検出手段を具備し、 該再送指示検出手段は、該再送指示検出データ
の検出に応じて、該受信側制御手段の制御の下
に、該受信側メモリに該再送データを書込ませた
後に該受信側メモリからのデータの読出し禁止を
解除させるものであることを特徴とする再送デー
タ送受信装置。[Claims] 1. In a data transmission/reception system, when an error is detected in received data on the receiving side, reading of the buffer memory on the receiving side, where data is read out in the order of writing, is prohibited, and data is read out in the order of writing on the sending and receiving sides. After clearing the buffer memory and writing retransmission data, which is correct data, to the transmitting side buffer memory, and storing the retransmitted data in the receiving side buffer memory on the receiving side, read the retransmitted data from the receiving side buffer memory by canceling the read prohibition. A retransmission data transmission/reception method characterized by transmitting retransmission data. 2. The transmitting side is equipped with a data generating means, a transmitting side memory for storing transmission data from the data generating means, and a transmitting side control means for controlling writing/reading of data to and from the transmitting side memory, and the receiving side , a receiving side memory for storing data from the sending side memory, a data receiving means for receiving data from the receiving side memory, and a receiving side control means for controlling writing/reading of data to/from the receiving side memory. In a data transmission/reception system, wherein data is read from each of the transmitting side memory and the receiving side memory in the order in which they are written, the data receiving means comprises an error detection means,
When the error detecting means detects an error in the received data, the error detecting means inhibits reading of data from the receiving side memory to the data receiving means under the control of the receiving side control means and clears the receiving side memory, and A data retransmission request signal is sent to the data generation means, and the data generation means includes initialization means, and the initialization means responds to the data retransmission request signal to send a correct data retransmission request signal including retransmission instruction detection data. The retransmission data that is data is created, and the retransmission data is written into the transmission side memory after the transmission side memory is cleared under the control of the transmission side control means in response to the data retransmission request signal. Yes, the receiving side includes retransmission instruction detection means for detecting the retransmission instruction detection data from the retransmission data sent from the sending side memory, and the retransmission instruction detection means detects the retransmission instruction detection data. In response to the detection, under the control of the receiving side control means, the retransmission data is written in the receiving side memory and then the prohibition of reading data from the receiving side memory is canceled. retransmission data transmission/reception device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60165671A JPS6226948A (en) | 1985-07-29 | 1985-07-29 | Method and equipment for transmitting and receiving retransmission data |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60165671A JPS6226948A (en) | 1985-07-29 | 1985-07-29 | Method and equipment for transmitting and receiving retransmission data |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6226948A JPS6226948A (en) | 1987-02-04 |
| JPH0410261B2 true JPH0410261B2 (en) | 1992-02-24 |
Family
ID=15816810
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60165671A Granted JPS6226948A (en) | 1985-07-29 | 1985-07-29 | Method and equipment for transmitting and receiving retransmission data |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6226948A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0490648A (en) * | 1990-08-06 | 1992-03-24 | Fujitsu Ltd | Coded transmission system |
| JP5056524B2 (en) | 2008-03-25 | 2012-10-24 | 富士通株式会社 | Data transmission system, data transmission method, data transmission device, and data reception device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52147910A (en) * | 1976-06-03 | 1977-12-08 | Toshiba Corp | Error control system |
-
1985
- 1985-07-29 JP JP60165671A patent/JPS6226948A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6226948A (en) | 1987-02-04 |
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|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |