JPH0411910B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a pattern recognition device, and particularly to a video signal input/output device thereof. The input/output method of a video signal in a conventional pattern recognition device is to input a fixed position and a set number of pixels, and this device is configured as shown in FIG. 1, for example. That is, image information from a subject is read by a TV camera 11, and this image information is binarized by a quantization circuit 12. Then, the binarized image information D _IN is temporarily stored in the shift register 13, and this shift register 1
The computer 14 performs a predetermined calculation on the stored information of No. 3 to recognize the pattern. Kode TV monitor 1
5 is configured to transfer the image of the object photographed by the TV camera 11 or the image of the object binarized by the quantization circuit 12 by switching the changeover switch S. Figure 2a shows the shift register 13 in Figure 1 above.
The image information D _IN binarized by the quantization circuit 12 is transferred to the shift register 13.
are loaded sequentially. When the information stored in this shift register is output, it becomes as shown in FIG. 2b. In such a configuration, even if the required data is only for a part of the screen, a memory element corresponding to the entire screen is required, which not only makes the device expensive, but also makes it difficult to recognize patterns according to the subject. I can't do it. In other words, since this device uses a shift register, the stored data cannot be displayed on a TV monitor, and since the position, shape, size, etc. of the input data group are constant, the image information range is limited in the vertical and horizontal directions. and the sampling period is constant, so
This method has many drawbacks, such as the inability to perform sampling according to the subject. Therefore, it lacks versatility as a pattern recognition device. To eliminate this drawback, if you only want to recognize a part of the image, you can fix the TV camera and set the subject on an XY table and move it, or
Conversely, a method has been implemented in which a TV camera is installed on an XY table, the subject is fixed, and the camera is moved on the XY table. However, since vibration occurs when the XY table moves, pattern recognition cannot be performed until the vibration stops, and it takes about 60 msec to 0.1 sec to start recognition, making it impossible to input image data at high speed. I get used to it. This invention was made in view of the above circumstances, and its purpose is to convert image information from analog to digital, and to store a partial image of an input image set by an external control signal as a recognition range in a storage circuit. By configuring the partial image to be memorized and pattern-recognized, the image recognition range and sampling period can be freely set using an external control signal, and a video signal input/output device capable of high-speed operation is provided. be. An embodiment of the present invention will be described below with reference to the drawings. FIG. 3 is a block diagram showing its configuration. Image information read from the subject by the TV camera 11 is sent via the camera control 16 to an analog/
The signal is supplied to a digital (A/D) converter 17 and A/D converted. The TV camera 11 is controlled from among the output signals of the TV camera 11 by extraction range setting signals Q and R output from a control signal generation circuit 19 to which an external control signal A and a clock pulse signal φ from an oscillator 18 are supplied. 16, image signals in a predetermined range are selectively extracted. Then, the image information A/D converted by the A/D converter 17 is stored as a partial image in the storage circuit 20 by the image capture signal D of the control signal generation circuit 19, and is also supplied to the switching circuit 21. . A switching signal E is supplied to this switching circuit 21, which controls switching between the image taken by the TV camera 11 and the image information stored in the storage circuit 20, and its output is digital/analog (D/A).
TV monitor 24 via converter 22 and amplifier 23
is supplied and monitored. Above D/A converter 2
2. The amplifier 23 is connected to the control signal generation circuit 1, respectively.
It is controlled by a conversion start signal F and a composite synchronization signal G from 9. FIG. 4 shows the control signal generation circuit 19 of FIG. 3 above.
This figure shows a specific example of the configuration of a circuit section related to the gist of the present invention. The clock pulse signal φ output from the oscillator 18 (for example, 28636M
Hz) is the frequency divider 25 and the synchronization signal generation circuit 26
supplied to The synchronization signal generation circuit 26 includes:
An interlaced scanning switching signal H and an odd/even field switching signal are supplied from the outside, and these signals φ,
A horizontal synchronization signal B, a vertical synchronization signal C, and a composite synchronization signal G are generated based on H and I. The horizontal synchronization signal B and the vertical synchronization signal C are supplied to the camera control 16, and the composite synchronization signal G is supplied to the amplifier 23. The extraction range setting signal QR outputted from the control signal generation circuit 19 includes the horizontal synchronization signal B and the vertical synchronization signal C, and the control of the camera control 16 based on these signals B and C allows odd number Scan, even scan, and interlaced scan are selected. On the other hand, the sampling period setting signal J is supplied to the frequency divider 25 to set the sampling period,
The output signal φJ of the frequency divider 25 is supplied to the first counter 27. This counter 27 is supplied with a horizontal input position setting signal L and a horizontal input pixel number setting signal K, and the synchronization signal generation circuit 2
It is reset by the horizontal synchronizing signal B output from the frequency divider 25, and the output signal φJ of the frequency divider 25 is sequentially counted. Then, when the set value of the horizontal direction input position setting signal and the value of the counter 27 match, a counter (part of the counter 27) that counts the number of horizontal direction input pixels starts operating, and when the set value of the number of horizontal direction input pixels is reached, Stop counting operation. Repeat this operation for the entire screen. Furthermore, the horizontal synchronization signal B of the synchronization signal generation circuit 26 is supplied to a second counter 28 . This counter 28 counts the number of horizontal synchronizing signals B (the number of scanning lines), and counts the number of horizontal synchronizing signals B (the number of scanning lines), and the vertical input position setting signal M and the vertical input pixel number setting signal N.
is supplied and reset by vertical synchronization signal C. When the set value of the vertical input position setting signal M and the count value of this counter 28 match, a counter (part of the counter 28) that counts the number of vertical input pixels starts operating, and Counting is performed up to the set value by the number setting signal N. The image data capture signal D is obtained by ANDing the horizontal data input signal O and the vertical data input signal P output from the first and second counters 27 and 28 using an AND circuit. . Next, the operation of the above configuration will be explained using FIGS. 5 to 7. FIG. 5 is a diagram for explaining the position setting of an image to be stored in the storage circuit 20, and in the figure, 24 is
On the screen of the TV monitor, the image taken by the TV camera 11 is transmitted to the camera control 16 and the A/D converter 1.
7. The image is displayed on a TV monitor 24 via a switching circuit 21, a D/A converter 22, and an amplifier 23. First, the pattern recognition start point (P _sx , P _sy ) is set by the horizontal input position setting signal L and the vertical input position setting signal M, and then the horizontal input pixel number setting signal K and the vertical input pixel number setting are set. By the signal N, an input data group 29 in a range of horizontal Px and vertical Py is set. This input data group 29
This data group 29 is a Px × Py grayscale data group.
is stored in the memory circuit 20. This stored data is transferred to the switching circuit 21, the D/A converter 22 and the amplifier 2.
3 to the TV monitor 24 for display. According to such a configuration, it is possible to intensively sample the image data of a necessary portion, so that highly accurate pattern recognition can be performed using an image memory with a relatively small capacity. Figure 6 is a diagram showing the relationship between the TV monitor and the sampling period, where the sampling period T is determined by the frequency divider 2.
It is set by the output signal φJ of No. 5. The output signal φJ of the frequency divider 25 can be freely set using the sampling period setting signal J. Therefore, since the horizontal resolution can be varied arbitrarily, a coarsely sampled image is first input and recognized, and then, based on the processing results, only important parts are intensively sampled and processed. If this is done, pattern recognition time can be shortened even if the image recognition range is wide, and memory usage efficiency can also be improved. Figure 7 shows an example of the procedure for performing pattern recognition over a wide area.First, a pattern with a specific feature is selected, and in order to sequentially perform pattern recognition around the selected pattern,
The screen 24 of the monitor is divided into a plurality of blocks, and patterns are recognized in the order of the blocks indicated by numbers 1, 2, 3, . . . , 12, . in this case,
The movement of the block to be recognized is achieved by changing the horizontal input position setting signal L, vertical input position setting signal M, horizontal input pixel number setting signal K, and vertical input pixel number setting signal N to set values. All you have to do is change it. Therefore, even with a relatively small capacity memory, pattern recognition can be performed over a wide range at high speed. Further, in the image signal input/output device according to the present invention, as shown in Table 1 below, the interlaced scanning switching signal H
By setting the odd/even field switching signal I, it is possible to switch between even scanning, odd scanning, and interlaced scanning. Therefore, when high resolution is required, the vertical resolution is doubled by switching between even and odd scanning. Furthermore, if high-speed processing is required, interlaced scanning may be used.

[Table] In Table 1 above, L is a logic "0" level and H is a logic "1" level. Note that this invention is not limited to the above embodiments, and can be implemented with various modifications.For example, the pattern recognition range (input data group)
If the settings are made using an external control signal, there is a limit to the movement of the recognition range, so the recognition range may be expanded by placing a TV camera or object on the XY table and moving it. As explained above, according to the present invention, image information is A/D converted, a partial image of an input image set by an external control signal is stored in a storage circuit as a recognition range, and this partial image is used for pattern recognition. With this configuration, the pattern recognition range and sampling period can be freely set by external control signals, and sampling can be performed according to the subject, so that a video signal input/output device that is highly versatile and capable of high-speed operation is obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a conventional pattern recognition device, and FIGS.
3 is a block diagram showing the configuration of a video signal input/output device according to an embodiment of the present invention, and FIG. 4 is a block diagram showing the method of inputting image data to the shift register and its output state. Third
FIGS. 5 to 7 are block diagrams showing the configuration of the control signal generation circuit in the block diagram shown in the figure, and are diagrams for explaining the operation of the circuits shown in FIGS. 3 and 4, respectively. 11...TV camera, 16...Camera control, 17...Analog-digital converter, 1
8... Oscillator, 19... Control signal generation circuit, 20
... Memory circuit, 25 ... Frequency divider, 26 ... Synchronization signal generation circuit, 27, 28 ... Counter, A ... External control signal, B ... Horizontal synchronization signal, C ... Vertical synchronization signal, D ... ...Image capture signal, H...Interlaced scanning switching signal, I...Odd/even field switching signal, J...Sampling cycle setting signal, K...Horizontal direction input pixel number setting signal, L...Horizontal direction input position setting signal , M... Vertical input position setting signal, N... Vertical input pixel number setting signal, O...
Horizontal data input signal, P... Vertical data input signal, Q, R... Extraction range setting signal, φ... Clock pulse signal, AND... AND circuit.

Claims (1)

[Claims] 1 In a video signal input/output device for inputting and outputting video signals to a pattern recognition device, there is a TV camera that photographs a subject and reads image information, and a TV camera that photographs a subject and reads image information.
A camera control means for controlling the camera, and the above based on the control of the camera control means.
An analog/digital converter converts the image information read from the TV camera into analog/digital; and a partial image of the image taken by the TV camera in the image information converted into digital data by the analog/digital converter. A storage means for storing a corresponding selected part of image information, and an output signal of the analog/digital conversion means and the image information stored in the storage means are supplied, and a selection is made to select one of them based on a selection signal. means, digital/analog conversion means for digital/analog conversion of the selected output of the selection means, an image taken by the TV camera based on the output signal of the digital/analog conversion means, and a partial image stored in the storage means. oscillation means for generating a clock pulse signal; synchronization signal generation means for generating a horizontal synchronization signal and a vertical synchronization signal based on the clock pulse signal generated from the oscillation means; A frequency dividing means to which the generated clock pulse signal and a sampling period setting signal are supplied, and a dividing period of the clock pulse signal is set based on the sampling period setting signal, an output signal of the frequency dividing means, and a horizontal input position. A setting signal, a horizontal input pixel number setting signal, and a horizontal synchronization signal output from the synchronization signal generating means are supplied, and the output signal of the frequency dividing means is applied to the horizontal input pixel from the supply of the horizontal input position setting signal. a first counting means that counts up to the number of pixels set by the number setting signal and outputs a horizontal data input signal, and is reset by the horizontal synchronization signal; a vertical input position setting signal; and a vertical input pixel number setting signal. , the horizontal synchronization signal and the vertical synchronization signal are supplied, the horizontal synchronization signal is used as a count input, and the vertical direction is counted from the supply of the vertical direction input position setting signal to the number of pixels set by the vertical direction input pixel number setting signal. a second counting means that outputs a data input signal and is set by the vertical synchronization signal; a horizontal data input signal output from the first counting means; and a vertical data input output from the second counting means. and logical product means for controlling the acquisition of the image data supplied from the analog/digital converting means to the storage means by performing a logical product with the signal and supplying the logical product output to the storage means. , stored in the above storage means.
It is configured to pattern recognize image information corresponding to a partial image of an image taken by a TV camera, and to change the sampling period by setting the dividing period of the frequency dividing means based on the sampling period setting signal. A video signal input/output device comprising: