JPH0413666B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a monitoring device in an automobile integrated wiring system, and more particularly to a device for monitoring malfunctions of controlled objects such as lamps and various sensors provided in various parts of the automobile body.

Recently, with the increase in the number of objects to be controlled such as lamps and various sensors installed in automobiles, problems arise in that electrical wiring becomes complicated, wiring errors are likely to occur, and the amount of electrical wires used increases, making it expensive. In order to solve this problem, an integrated wiring system has been proposed that remotely controls a large number of control objects using one data transmission line (control signal line). This control signal line may be an electric wire or an optical fiber. In any case, at one end of the data transmission line there is a central processing unit (CPU)
A central control unit is provided including: The central control unit is
The control object connected to the other end of the data transmission line is remotely controlled in response to the operating state of the operating switch.

However, in an integrated wiring system, if the controlled object is a lamp, it may not operate normally due to a burnout of the lamp, or may not operate normally due to an abnormality in data transmission between the central control unit and the terminal control unit. There was a problem in that it was not possible to accurately detect abnormalities in various controlled objects.

Therefore, it is conceivable to provide the central control unit with a function of determining abnormal operation, and to display abnormal conditions using lamps for indicating abnormalities provided on an instrument panel or the like. However, devices that display such abnormal displays require an increase in the number of display sections on the instrument panel, which increases costs and increases costs.
Drivers can easily mistake them for other instruments or indicator lamps, causing problems that impede safe driving.

Therefore, an object of the present invention is to enable detection of abnormal operation states of multiple controlled objects by cause in an automobile centralized wiring system, to easily know abnormal states during maintenance and inspection, and to be useful for safe driving. Another object of the present invention is to provide a monitoring device for an automobile integrated wiring system.

In summary, the present invention groups a plurality of control objects installed in an automobile according to their installation positions, and configures the control objects included in each group to be controllable by a corresponding terminal control unit. A data transmission line connects one central control unit and each terminal control unit. The central control unit tests the operational status of the terminal control unit or the operational status of a plurality of control objects provided in each terminal control unit, stores the results in a storage means, and then returns the vehicle to a service station or the like for maintenance. When performing an inspection, the contents of the storage means are transferred to an operating state monitoring means provided at the service station. The operating state monitoring means determines the presence or absence of an operational abnormality for each terminal control unit and each of the plurality of controlled objects corresponding to each terminal control unit based on the collected data, and visually displays the determination result. This notification is provided in a visually recognizable manner (display or print).

Hereinafter, specific embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram schematically showing an integrated wiring system for an automobile to which the present invention is applied. In the configuration, a master processor (hereinafter referred to as master MPU) 10, which is an example of a central control unit, is provided at a location near the driver's seat of the automobile (for example, under the dash board). A DC voltage is supplied to the master MPU 10 from the storage battery 1. The master MPU10 has
Operating means 2A and indicator 2B are connected. The operating means 2A includes various operating switches provided, for example, in relation to an instrument panel or a steering wheel.

Furthermore, terminal processors (hereinafter referred to as terminal MPUs) 20A to 20D, which are examples of terminal control units provided at appropriate locations in the automobile, are connected to the master MPU 10 via cables 30A to 30D. Each terminal
A plurality of control objects and/or detection objects (hereinafter collectively referred to as a group of control objects) 40A to 40D are connected to the MPUs 20A to 20D. Here, the controlled object refers to electrical components such as various lamps and wipers that are installed in an automobile, as will be explained with reference to FIGS. 2A to 2D, which will be described later. Detection targets are various sensors that are detected by various indicators included in the instrument panel of an automobile. These control object groups 40A to 40D are a plurality of control objects grouped according to their arrangement positions, and each group has a corresponding terminal MPU 20.
It is controlled by A to 20D. Here, although the illustration shows a case where there are four terminal MPUs, this is to represent a case where various control objects are divided and grouped on the front, rear, left and right sides of the automobile. For this purpose, the controlled object group 40A includes various controlled objects provided at the front left portion of the automobile, and the terminal MPU 20A is provided at a position close to the front left portion of the automobile. Similarly, the controlled object group 40B,
40C and 40D are provided in relation to the front right part, the rear left part, and the rear right part of the automobile, respectively, and the terminals MPU 20B, 20C are connected thereto.
and 20D are provided.

Figures 2A to 2D show each terminal MPU20A to 2.
FIG. 2 is a diagram schematically showing an example of a controlled object or a detected object connected to an output terminal or an input terminal of 0D. Therefore, each output terminal is connected to a signal line for the various control objects shown in the figure or a switch for activating these control objects. As is clear from the illustration, the output terminal and input terminal of each terminal MPU 20A to 20D each consist of a fixed number of bits (for example, 8 bits), and the operating state of the controlled object is determined by the logic state output from one bit. It is something to control. In addition, Figure 2B and Figure 2
As shown in Figure C, the data input to each of the terminal MPUs 20B and 20C is a value detected by a sensor for detecting the water temperature or a sensor for detecting the amount of gasoline, which is an example of the detection target. .

Further, although not shown in FIGS. 2A to 2D, the detected current of each controlled object is input to each terminal MPU 20A to 20D, respectively.

Furthermore, in this embodiment, the master MPU 10 itself has a function as a terminal, and its input terminals are mainly connected to operating means (switch means) and indicators as shown in FIG. 2E. If the number of operating means is more than 1 byte (for example, 8 bits) as shown in the figure, the outputs of all the operating means are received as input using a plurality of bytes.

The types of objects to be controlled and objects to be detected connected to each of these terminal MPUs 20A to 20D and the master MPU 10 are merely examples, and differ depending on the model and type of vehicle.

FIG. 3 is a sectional view showing the specific structure of cables 30A to 30D. Cable 30A~30D
includes a power line 31, which is an example of a power supply line, in its center. A data transmission line 33 including a set of system power lines 32 and a set of optical fibers 331 and 332 is arranged around the power line 31 . The peripheral portion of each line or optical buffer is covered with an insulator 34.

FIG. 4 is a specific circuit diagram of an embodiment of a monitor device in an integrated wiring system, which is a feature of the present invention. Note that in the illustrated embodiment, the master
The relationship between the MPU 10 and one terminal MPU (for example, 20A) is shown.

In the configuration, the master MPU 10 includes a central processing unit (hereinafter referred to as CPU) 11. CPU11 has
A program storage memory (hereinafter referred to as ROM) 13 and a data storage memory (hereinafter referred to as ROM) are connected via a bus line 12.
RAM) 14, transmission control circuit 15, and input/output interface 16 are connected. Also, the master
A system power supply circuit 17 for supplying power to each part is connected to the MPU 10. A socket 18 is connected to the RAM 14 for reading the stored contents from the outside by direct access. The input/output interface 16 has an MPU 20A for each terminal.
An operating means 2A and various indicators 2B for instructing or selecting the operating states of a plurality of controlled objects corresponding to 20D are connected. The operating means 2A includes
A plurality of operation switches 2a to 2n are included.

The transmission control circuit 15 includes each cable 30A to 3.
1 included in 0D (only 30A is shown in the diagram)
Transmitting buffer amplifiers 51a-51d and receiving buffer amplifiers 58a-58d are connected to the paired optical fibers 331, 332.

The terminal MPU (for example, 20A) includes a CPU 21, and a ROM 23, a RAM 24, and a transmission control circuit 2 connected to the CPU 21 via a bus line 22.
5 and an input/output interface 26. Furthermore, the terminal MPU 20A includes a system power supply circuit 27 for supplying power to each part. A reception buffer amplifier 54a and a transmission buffer amplifier 55a are connected to the transmission control circuit 25. The transmitting buffer amplifier 51a and the receiving buffer amplifier 54a are connected via an optical coupler 52a, an optical fiber 331, and an optical coupler 53a. The transmitting buffer 55a and the receiving buffer 58a are connected to an optical coupler 56.
a, an optical fiber 332, and an optical coupler 57a. System power supply circuit 27 is connected to storage battery 1 via system power supply line 32 .

A plurality of controlled objects included in the controlled object group 40A,
For example, a drive circuit is provided in connection with headlight 410 and wiper 415. This drive circuit includes
Power switch 4 connected in series to headlight 410
30 and a diode 441, a power switch 435 and a diode 445 connected in series to the wiper 415, and the like. These power switches 430...435 are connected to the positive terminal of the storage battery 1 via the power line 31. CPU2
A driver 42 is provided to selectively turn each power switch 430...435 on or off with a single output.

In addition, other terminals MPU20B to 20D are
The circuit configuration is the same as that of 20A, and the only difference is the group of controlled objects to be connected, so the detailed configuration will be omitted.

Further, the master MPU 10 is connected to an operating state monitor device 50, which is a feature of the present invention. This operating state monitoring device 50 is usually installed at a location away from the vehicle, such as a service station, and when the vehicle comes to the service station for maintenance or inspection,
RAM connected to the master MPU 10
14, and based on the stored content, determine the presence or absence of an abnormality in each terminal MPU 20A to 20D, and the abnormal operation of the controlled object group 40A to 40D connected to each terminal MPU 20A to 20D, The judgment results are monitored.

More specifically, the operating state monitoring device 50 includes:
Includes CPU51. A program storage memory (ROM) 53 and a display drive circuit 55, which is an example of an output drive means, are connected to the CPU 51 via a bus line 52, and a data storage memory (RAM) 54 is connected as necessary. be done. The display drive circuit 55 includes a numeric display 56, which is an example of an output means, and a plurality of display sections 571 to 57n.
is connected. This number display 56 is
It is used to display malfunctions of multiple control targets for each MPU as a multi-digit code.
The plurality of display sections 571 to 57n use light emitting diodes, display lamps, or the like, and are provided corresponding to each control target (load) of each terminal MPU. Therefore, each display section 571 to 57n may be
Identification information (load number) indicating the corresponding controlled object is associated with the load number. In addition, the display section 571
~57n is the maximum number of control objects included in one terminal MPU (for example, seven), by displaying which terminal MPU corresponds to the number display 56, the number display 56 and the display section 57
A controlled object having an operational abnormality may be displayed by a combination of display states 1 to 57n.

In addition, as another example of notifying the abnormal operation of each controlled object in a visual manner, displaying the specific name of the abnormal controlled object on the CRT display,
A printer, which is an example of a printing means, may be provided and the information may be printed and recorded.

A plug 58 is connected to the data bus 52. This plug 58 is connected to the socket 18 when collecting the memory contents of the RAM 14.
It is used to read the storage contents of the RAM 14 by direct access and collect data.

Figure 5A shows the RAM included in the master MPU 10.
14 is a diagram schematically showing fourteen storage areas. FIG.
The RAM 14 includes storage areas 14a to 14d used to test the operating states of each terminal MPU 20A to 20D and the operating states of each control target group. Each of the storage areas 14a to 14d includes at least 3-byte storage areas (hereinafter referred to as areas) M11 to M43 for each terminal MPU, corresponding to the terminals MPUs 20A to 20D, respectively. Here, area M
12, M13, M22, M23, M32, M3
3. M42 and M43 are each terminal MPU20A
It is used to store test data to be transmitted to 20D, for example, transmission/reception data matching check data. Areas M11, M21, M31, and M41 are used to temporarily store data transmitted from each terminal MPU 20A to 20D.

FIG. 5B is a diagram schematically showing a part of the storage area of the RAM 24 included in each terminal MPU 20A to 20D. In the figure, each terminal MPU
RMA24 included in 20A to 20D is the master
It includes areas (registers) R1 to R4 for temporarily storing data received from the MPU 10 or data to be transmitted to the master MPU 10. Each register R1 to R4 is stored in each terminal MPU20.
Control objects provided corresponding to A to 20D (i.e., loads L10 to L17, loads L20 to L27,
It includes bits corresponding to loads L30 to L37 and loads L40 to L47).

FIG. 6 is a time chart for explaining the operation in the test mode. In particular, in the diagram, the test items include a transmission/reception data match check and a load disconnection check for each terminal.
Terminal MPU20A to 20D (These terminal MPU2
RS#1 to RS#4 with 0A to 20D as terminal number
) indicates another data transmission period. Here, various tests or check operations performed in the test mode include each terminal MPU 20A to
Operating status of 20D and optical fibers 331, 33
2. Sending and receiving data matching check to check for disconnection status, and each terminal MPU 20A
- 20D, ie, a load disconnection check. These checks are performed immediately after power-up and before entering the normal operating routine. In this case, the check operation procedure is from the master MPU 10 to the terminal MPU 20A (RS
#1) Send check data to terminal MPU2
After 0A responds and confirms the received data, it sends it to the master MPU 10, and from then on, the terminal
MPU20B (RS#2), 20C (RS#3), 20
The process is repeated in sequence in the order of d (RS#4).
Note that the transmitted/received data is, for example, 4 bytes long, and the first byte is the master data.
Destination terminal to which data should be transmitted from MPU10
The dot of the MPU also indicates data (SDA) indicating the terminal number, the next 1 byte indicates data (SSA) indicating the terminal number of the transmitted terminal (in that case, master MPU 10), and the remaining 2 bytes indicate control or test. Show data.

7A and 7B are flowcharts showing the operation of checking the coincidence of transmitted and received data as an example of the test mode. In particular, FIG. 7A shows the operation flow on the master side, and FIG. 7B shows the operation flow on the terminal side as an example.
The operation flow of MPU20A is shown.

Next, referring to FIGS. 1 to 7B, the operation of checking the coincidence of transmitted and received data will be described.

Immediately after the power is turned on, the CPU 11 included in the master MPU 10 performs initial settings for checking transmission/reception data consistency in step 11.
More specifically, this operation is performed in the storage area 14a.
~14d each 3-byte area M11,
This is done by setting and storing logic "1" in all bits of M12, M13 to M41, M42, and M43. Thereafter, in steps 12 to 16, a transmission/reception data matching check operation is performed for the terminal MPU 20A. That is, in step 12, the CPU 11 uses the terminal MPU 20A.
In order to specify this, SDA is set to terminal number #1 and test data (data set in M12 and M13) in which all bits of 2 bytes are logic "1" is given to the transmission control circuit 15. The transmission control circuit 15 is a terminal
At the timing when MPU20A should be selected,
Destination data (SDA) to select terminal MPU20A
= #1) and all bits of 2 bytes are logic “1”
Buffer amplifiers 51a to 5 transmit test data of
Give to 1d. This data is for each cable 30A
It is applied to the transmission control circuit 25 included in each terminal MPU 20A-20D via an optical fiber 331 included in MPU 20A-30D. At this time, terminal MPU20
In step 21, the CPU 21 of
Data is being received from MPU10. and,
In step 22, it is determined whether the destination data SDA is data (#1) specifying the own terminal, and if it is determined that the own terminal is specified, the operation of step 23 is performed. That is, step 2
3, the CPU 21 sends the received 2-byte data as it is to the transmission buffer 50a and the optical coupler 5.
6a, the optical fiber 332, the optical coupler 57a, and the receiving buffer 58a.

On the other hand, after transmitting the test data in step 12, the CPU 11 enters a reception standby state in step 13. And if any terminal
When response data is transmitted from the MPU, it is determined whether the transmission source data SSA of the response data is terminal number #1 that specifies the terminal MPU 20A. If the terminal
If it is determined that the data is from the MPU 20A, the process advances to step 15. In step 15,
The CPU 11 determines whether all bits of the 2 bytes of received data are logical "1". If all bits are logic 1, the data sent as test data has been returned as is, so it is determined that there is no data transmission error, that is, the sent and received data match, and the next terminal MPU 20B sends and receives the data. Proceed to data match check operation. On the other hand, if all bits of 2 bytes of the received data are not logical "1", it is determined that a data transmission error has occurred, and the process proceeds to step 16.

The data transmission error determined here is the
The MPU20A cannot operate normally, or the optical fibers 331, 3 included in the cable 30A
For example, a disconnection has occurred in one of 32. Then, in step 16, the received 2
Byte data is stored in areas M12 and M13.

In addition, terminal MPU20B, 20C and 20D
The sending/receiving data matching check operation is a step-by-step process.
Since the operation is similar to that of the terminal MPU 20A except that the terminal numbers 12 and 14 are 2, 3, or 4, detailed explanation thereof will be omitted.

In this way, each terminal MPU20A~20D
After checking the consistency of the transmitted and received data in each case, the program proceeds to a load disconnection check routine shown in FIGS. 8A and 8B, which will be described later.

8A and 8B are flowcharts of the load disconnection check routine, which is a feature of the invention. Particularly, FIG. 8A shows the operation flow on the master MPU 10 side, and FIG. 8B shows the operation flow on the terminal MPU (for example, the
0A) side operation flow is shown. Next, with reference to FIGS. 1 to 6, FIGS. 8A and 8B, the operation when performing a load disconnection check will be described. Here, the disconnection of the load means, if the object to be controlled is a lamp, a burnout of the lamp or a disconnection of the electric wire connecting the lamp and the power switch.

Steps 31 to 34 show the operation of the CPU 11 for checking the load disconnection of the terminal MPU 20A. That is, in step 31, the CPU 11 selects the terminal MPU 20A and transmits data (for example, all bit logic "1" stored in area M11) instructing to turn on all loads. On the other hand, the CPU 21 on the terminal MPU 20A side performs initial settings (for example, register R) in step 41.
Logic ``1'' is set and stored in all bits of 1). Then, in step 42, it enters a reception standby state. Next, when the CPU 21 receives the data transmitted from the master MPU 10, the data SDA included in the received data is #1 in step 43.
Determine whether or not. If it is determined that SDA=#1, in steps 44 to 47, the second
A disconnection detection operation for the load (controlled object) corresponding to the 0th bit shown in Figure A is performed. That is, in step 44, the CPU 21 sends a signal to the input/output interface 26 to turn on the load (L10; for example, the headlight 410) corresponding to the 0th bit.
to the driver 42 to turn on the power switch 430. Subsequently, in step 45, the current of the load corresponding to the 0th bit is detected. This load current is detected, for example, based on the terminal voltage of a resistor connected between headlamp 410 and ground. In step 46, the detected current is 0.
It is determined whether or not. If it is determined that the detected current is 0, it is determined that the load that responds to the 0th bit is disconnected, and the process proceeds to step 47. In step 47, CPU 11 writes a logic "0" to the 0th bit of register R1.

On the other hand, if it is determined that the detected current is not 0, the load corresponding to the 0th bit is not disconnected, so a disconnection detection operation for the load corresponding to the 1st bit is performed. This operation differs from the operations in steps 44 to 47 only in the number of the load to be tested and the bit of register R1 to which logic ``1'' is written when an abnormality is detected; other than that, the operations are almost the same. Since they are similar, they will be omitted. Thereafter, the disconnection detection operation is similarly performed for each of load numbers 2 to 7 (L12 to L17). When the disconnection detection operation of the plurality of loads corresponding to the terminal MPU 20A is completed, the process advances to step 48.
At step 48, data SSA is set to #1 and the contents of register R1 are transmitted to master MPU 10. After that, the CPU 21 of the terminal MPU 20A,
Proceed to normal operating mode.

On the other hand, CPU 11 included in master MPU 10
In step 32, each terminal MPU20A~2
Transmission data from 0D is being received. and,
If it is determined in step 33 that the data SSA is #1, the process advances to step 34. step
At 34, the received data from the terminal MPU 20A is written to the area M11.

After that, in the same way, CPU 11 is set to terminal MPU 20.
The operation for checking wires B, 20C, and 20D for disconnection is performed in sequence. This behavior is based on the terminal that should be specified.
Since the operations are almost the same as those in steps 30 to 34 except that the MPUs are terminal numbers 2 to 4, detailed explanation thereof will be omitted. Thereafter, the CPU 11 proceeds to a failure handling routine shown in FIG. 9, which will be described later.

FIG. 9 is a flowchart for handling a failure on the master MPU 10 side. Next, the operation of the failure handling routine will be explained.

In step 51, the CPU 11
2. Determine whether all bits of M13 are logical "1". If logic "0" is stored in any of the bits, there is some kind of abnormality in the terminal MPU 20A itself or the transmission system such as the corresponding cable 30A, so the process proceeds to step 52.
At step 52, a disconnection process for the terminal MPU 20A is performed. This process is performed to prohibit the operation of a controlled object that should be operated based on the operating state of the switch, even if various switches included in the operating means 2A are operated.
Do not give an operation command signal to MPU20A. After step 52 or after determining in step 51 that logic "1" is stored in all bits in areas M12 and M13, the process advances to step 53. Then, in step 53, it is determined whether logic "1" is stored in all bits of areas M22 and M23. If it is determined that logic "1" is not stored in all the bits in areas M22 and M23,
At step 54, the terminal MPU 20B is disconnected. Follow the same steps from now on.
In steps 55 and 57, it is determined whether or not there is an abnormality in the controlled object included in each of the terminal MPUs 20C and 20D, and in steps 56 and 58, the terminal MPU 20C or 20D corresponding to the abnormal controlled object is disconnected. . Thereafter, the process proceeds to normal operation mode. Note that the normal operation mode is not the gist of the present invention, so a description thereof will be omitted.

FIG. 10A is a diagram schematically showing the storage area of the ROM 53. The ROM 53 stores in advance a program for determining operational abnormalities for each terminal MPU and for each controlled object, as shown in FIG. 11, which will be described later, and also includes the following table. In other words, the ROM 53 is the MPU of each terminal.
Codes (or numbers) for each controlled object (load) corresponding to 20A to 20D are set and stored. For example, each terminal MPU 20 as shown in FIG. 5B
Controlled object (load) L10~ corresponding to A~20D
Codes for each of L17, . . . L40 to L47 are set and stored.

FIG. 10B is a diagram schematically showing the storage area of the RAM 54. The RAM 54 includes a plurality of working areas and is used to sequentially store the terminal number of the terminal MPU in which the abnormality occurred or the code of the control object in which the abnormality occurred for each terminal MPU.

FIG. 11 is a flowchart for explaining the operation of the CPU 51 included in the operating state monitor device 50 provided in the service station. Next, the specific operation of the operating state monitoring device 50 will be described with reference to FIGS. 4 and 10 to 11.

When the vehicle arrives at the service station, an attendant inserts the plug 58 of the operating condition monitoring device 50 into the socket 18 included in the vehicle's master MPU 10 to enable reading of the RAM 14. In this state, the CPU 51 starts checking or monitoring the presence or absence of an abnormality based on the stored contents of the memory 14 in accordance with the flowchart of FIG.

That is, in step 61, the contents of areas M12 and M13 of the RAM 14 are read, and by determining whether logic "1" is written in all bits of areas M12 and M13, the master MPU 10 and It is determined whether there is an abnormality in data transmission with the terminal MPU 20A. If logic ``1'' is not written in all the bits in areas M12 and M13, the reception data indicating that an abnormality has occurred has been written in step 16, and this can be determined. Proceed to step 62. At step 62, in order to notify that a data transmission abnormality has occurred between the terminal MPU 20A and the master MPU 10, the corresponding display section lights up.

After the process in step 62 has been performed, or if it is determined in step 61 that there is no abnormality in data transmission, the process advances to step 63. In step 63, the contents of areas M22 and M23 of RAM 14 are addressed and read into CPU 51.
Then, it is determined whether all bits of the storage contents of areas M22 and M23 are logical "1". If all the bits are not logical "1", it is determined that a data transmission error has occurred between the master MPU 10 and the terminal MPU 20B, and the process proceeds to step 64. At step 64, a display section lights up to notify that a data transmission abnormality has occurred between the master MPU 10 and the terminal MPU 20B.

Thereafter, in steps 65 and 67, it is determined whether there is an abnormality in data transmission between the master MPU 10 and the terminal MPU 20C or 20D.
If it is determined that there is an abnormality, step 66 or 68
The corresponding display section is displayed by lighting up. In this way, area M1 of RAM14
2, M13, M22, M23, M32, M33,
Based on the contents of M42 and M43, the master MPU
10 and each of the terminal MPUs 20A to 20D is judged to be abnormal in data transmission.

Subsequently, in step 69, a register (or counter; not shown) N for specifying the controlled object is cleared. The correspondence between the contents (numerical values) of this register N and each controlled object is L10 to L1 indicating each controlled object or load shown in FIG. 5B.
7, . . . corresponds to the one's digit values of L40 to L47. In step 70, the contents of area M11 of the RAM 14 are read out, and based on the logic state of the bit corresponding to the value of register N among the stored contents of area M11, it is determined whether or not there is an abnormal operation of the load corresponding to that bit. . More specifically,
If a logic "1" is not stored in the bit corresponding to the value of register N, a logic "0" indicating a wire break has been written in step 47 described above. Therefore, in step 71, the code for that load is written to a certain area of the RAM 54. After step 71 or if it is determined in step 70 that there is no abnormality in operation, step 72 is performed.
Proceed to. In step 72, one is added to the value of register N. As a result, the number of the load to be judged next for the presence or absence of abnormal operation has been advanced. In step 73, the value of register N is 8.
It is determined whether or not. At this time, terminal MPU20
If the presence or absence of an abnormality has not been determined for all the loads (8) to be controlled by A, since the value of register N is 8 or less, this is determined and the process returns to step 70.

In this way, the operations of steps 70-73 are performed for each load.

Thereafter, in the same manner as steps 69-73, it is determined whether or not there is an abnormality in the operation of the controlled objects (loads) corresponding to the other terminal MPUs 20B-20D. The operation flow in this case is almost the same as steps 69 to 73, and the area of the RAM 14 determined in step 70 is M21, M31, or M41 instead of M11. Therefore, in the illustration, the step of determining whether or not there is an operational abnormality for each controlled object corresponding to the other terminal MPUs 20B to 20D is omitted.

Then, when it is determined whether or not there is an operational abnormality for each controlled object (load) of the terminal MPU 20A to 20D, the load number where the operational abnormality occurred stored in each area of the RAM 54 is sequentially read out in step 74. The display section corresponding to the load number is displayed by lighting. As a result, the service station staff can easily know which load is operating abnormally and which terminal MPU is causing data transmission abnormality by looking at the lighting display state of the display units 571 to 57n. It has the advantage of being able to

In addition, the display of the determination result of abnormal operation is displayed on the operational status monitoring device 50 installed in the service station, so the configuration is simplified compared to the case where this operational status monitoring device 50 is installed in each vehicle. It also has the advantage of being inexpensive to manufacture and preventing the driver from misjudging the displayed content.

As described above, according to the present invention, in a system in which a plurality of control objects installed in an automobile are centrally wired, an abnormality in the central control unit or terminal control unit or an abnormality in the data transmission line, It is possible to accurately detect abnormalities in the operation of the controlled object, and it has unique effects such as being able to perform repairs quickly without the need for tests to detect abnormalities during inspection and repair. In addition, since the means for displaying abnormal conditions in a visually recognizable manner is provided at a predetermined location, such as a service station, away from the automatic display, many display sections are installed on the vehicle's instrument panel. There is no need to provide such a device, the configuration can be simplified, it can be manufactured at low cost, and it also has the effect of preventing the driver from misjudging the displayed content.

[Brief explanation of drawings]

FIG. 1 is a block diagram schematically showing an integrated wiring system for an automobile to which the present invention is applied. Second
Figures A to 2D are terminal MPUs that are examples of terminal control units.
FIG. 2E is a diagram schematically showing an example of a control object connected thereto, and FIG. 2E is a diagram showing the relationship between the input/output terminal of the master MPU and each control object. Third
The figure is a sectional view showing details of the cable. FIG. 4 is a specific circuit diagram of an embodiment of the present invention.
Figures 5A and 5B show RAM 14 and
3 is a diagram schematically showing a part of the storage area of the RAM 24. FIG. FIG. 6 shows a time chart in test mode. FIGS. 7A and 7B are flowcharts on the master MPU side and the terminal MPU side for explaining the matching check operation of transmitted and received data in an example of the test mode. FIGS. 8A and 8B show flowcharts of the load disconnection/short circuit checking operation for the master MPU and terminal MPU in another example of the test mode. FIG. 9 shows a flowchart of the failure handling routine. 10A and 10B show the ROM 53 included in the operating state monitor device 50,
5 is a diagram schematically showing a part of the storage area of the RAM 54. FIG. FIG. 11 is a flowchart for explaining the operation of the operating state monitoring device, which is a feature of the present invention. In the figure, 10 is the master MPU, 20A to 2
0D is the terminal MPU, 40A to 40D are the control target group,
50 indicates an operating state monitoring device.

Claims (1)

[Scope of Claims] 1. In a system in which a plurality of various control objects installed in an automobile are grouped based on those that are located close to each other, and a certain number of control objects included in each group are consolidated and wired for each group, A device for detecting and monitoring abnormalities, comprising a terminal control unit 2 provided for each group.
0A, 20B, 20C, 20D, operating means 2A for selecting the operating state of a certain controlled object among the plurality of controlled objects included in each of the terminal control sections, commonly connected to each of the terminal control sections; , a central control unit 10 that remotely controls each control target by deriving a control signal for controlling the operating state of the control target corresponding to each terminal control unit based on the operation state of the operating means; a plurality of cables 30A, 30B, each connected between the terminal control unit and the central control unit, each including at least a data transmission line;
30C, 30D, and an operating state monitor means 50 that is provided at a predetermined location away from the vehicle and outputs an abnormal operating state; Test signal generation means 11 and 13 that generate test signals for instructing the operation of a plurality of control objects included in the terminal control unit; and a control signal based on the operation state of the operation means or a test signal output from the test signal generation means. of,
a first transmission control means 15 that transmits terminal designation data specifying the certain terminal control unit to each terminal control unit via the data transmission line and receives transmission data from each terminal control unit; a storage means 14 having a storage area corresponding to each of a plurality of control objects for each terminal control section, and each terminal control section controls the operating state of the corresponding control object in response to the control signal. , driving means 4 for operating corresponding control objects of the same group in response to the test signal.
30, 440; operating state detection means 21 for detecting the operating state of each controlled object in the corresponding group when the test signal is applied; and receiving the control signal or the test signal;
and a second transmission control means 25 for transmitting an output signal of the operating state detection means to the central control unit via the data transmission line, and the storage means is configured to store the operating state detection data received from each terminal control unit. a connection connected between the central control unit and the operating state monitoring means when storing an output signal of the means in a corresponding storage area, and determining an operational abnormality based on the stored contents of the storage means; Means 1
8, 58, and the operating state monitoring means 50 includes: an output means 56 for outputting operational abnormalities of a plurality of controlled objects for each of the terminal control units in a visually discernable manner; a control means 51 that reads out the storage contents of the storage means and determines abnormal operation of a plurality of control objects for each terminal control section based on the output signal of the operation state detection means for each terminal control section;
and an output drive means 55 for giving the determination result of the control means to the output means and outputting it in a visually discernible manner. 2. The operating state monitoring means further includes a collected data storage means 54 that collects and stores the storage contents of the storage means of the central control unit, and the control means reads out the storage contents of the storage means via the connection means. read/write means 51 for writing data into the collected data storage means; and a read/write means 51 for writing data into the collected data storage means, based on the output signal of the operating state detection means for each terminal control part stored in the collected data storage means. 2. A monitoring device in an automobile integrated wiring system according to claim 1, further comprising determining means 51 for determining abnormal operation of a plurality of control objects. 3. A monitor device in an automobile integrated wiring system according to claim 1, wherein the output means is a display means 56. 4. The display means includes a plurality of display sections 571 to 57n provided for each control target of each terminal control section.
A monitor device in an automobile centralized wiring system according to claim 3, comprising: 5. A monitor device in an automobile integrated wiring system according to claim 1, wherein the output means is a printing means.