JPH0414371B2 - - Google Patents

Description

[Detailed description of the invention]

[Overview] When multiple access sources access the main memory using consecutive addresses, access contention occurs when the access source with a large access throughput catches up with the address of the access source with a small access throughput, and the access throughput decreases. did. Therefore, addresses of access sources with a small access throughput are generated at intervals, and the scanning speed of the main storage area is apparently made equal to that of an access source with a large access throughput, thereby reducing the chance of access contention. [Industrial Application Field] The present invention relates to a main memory control method in an information processing device, and particularly to an efficient access control method when a continuous area of the main memory is accessed by a plurality of access sources. [Prior Art] FIG. 2 shows an example of an information processing device to which the present invention is applied. In the figure, 1 is the main storage unit MSU, 2 is the main memory control unit MCU, and 3 is the channel processor.
CHP, 4 is a scalar unit SU, 5 is a vector unit VU, 6 is an extended memory control unit EMU,
7 is an expanded memory, 8-0 is a processor element PE consisting of the above 1 to 5, and 8-1 to 8-n are:
Represents another processor element PE. Channel processor CHP, scalar unit
SU, vector unit VU, and extended memory control unit EMU are main memory control units.
The main storage device MSU can be accessed via the MCU. The main memory unit MSU has a configuration in which addresses are interleaved into multiple banks, and parallel access to multiple banks is possible at the same time. The extended memory control unit EMU also controls data transfer between the main storage device MSU of the processor element 8-0 and the extended memory ESU, and also controls data transfer between the extended memory ESU and the MCU of each processor element PE. It also controls transfer. For this reason, the number of access ports that the extended memory control unit EMU (therefore also the extended memory ESU) has for one main memory control unit MCU is limited to the vector unit VU, etc., since there are 0 to n processor elements. The data bus width is also narrower, and the access throughput is usually smaller. For example, in an example system, there are multiple load/store pipelines between the VU and the MCU, each with a throughput of 4 elements/1T, but between the EMU and the MCU there are 1 element throughput. Only one load/store pipeline with a throughput of /1T is provided (1 element = 8 Bytes). When multiple access sources with different access throughputs to the main memory MSU each access a predetermined area of the main memory in ascending order using consecutive addresses (distance d = 1), depending on the condition, bank conflict or
LS (LOGICAL STORAGE) BUSY occurs. This will be explained using specific examples shown in FIGS. 3 and 4. In the example shown, VU is 1 machine cycle (1T)
4LS (LOGICAL STORAGE) or 4 elements can be accessed every 4 machine cycles (4T), but EMU is for the case where 4LS (LOGICAL STORAGE) or 4 elements can be accessed every 4 machine cycles (4T). That is, the ratio of access throughput between the two is 4:1. In FIGS. 3 and 4, the vertical axis shows time, and the horizontal axis shows LS (LOGICAL STORAGE) NO. The unit of one access is 4LS, and the reason why a line extends vertically when accessed is due to the LS Busy time, during which other accesses are prohibited. In the example shown in Figure 3, 9 is an EMU access with a small access throughput, 10 is a VU access with a large access throughput, 11 is a VU access as well, and another access pipeline other than 10 is operating at the same time. It shows. In the illustrated time domain, LS access contention does not occur between accesses, so the access throughput of VU access does not decrease. However, in the example shown in Fig. 4, the VU access of 10 catches up with the EML access LS=i of 19 and waits for access, and henceforth, as shown by 10', the VU access
Access waits for the preceding EMU access for each LS, and the access throughput drops to the same level as EMU access. [Problem to be solved by the invention] In conventional information processing devices, when multiple access sources with different access throughputs access the main memory using consecutive addresses, there is a possibility that access conflicts will occur one after another in consecutive LSs. However, there was a problem in that the access efficiency of access sources with large access throughput decreased, resulting in slow processing speed. [Means for Solving the Problems] The present invention provides a method to prevent consecutive access conflicts between the access addresses of the access sources when a plurality of access sources with different access throughputs access the main memory using consecutive addresses. In other words, in order to prevent the access address of an access source with a small access throughput from being overtaken by the access address of an access source with a large access throughput, the access throughput between the access sources is calculated from the address sequence of the address source with a small access throughput. Access addresses are generated intermittently at intervals based on the ratio of access points, and control is performed to access the main memory. Therefore, consecutive address sequences of access groups with small access throughputs are divided and grouped by the access throughput ratio n (n is an integer). Next, from each group, for example, the lowest address in the group is taken out in order, and after one cycle, the next address in each group is taken out in order. Thereafter, by repeating this operation n times, addresses for the entire original address sequence can be generated. [Embodiment] An embodiment in which the present invention is applied to the information processing apparatus shown in FIG. 2 will be described below. Therefore, the configuration shown in FIG. 2 can be used as is. Vector unit VU has multiple load/store pipelines. One load store pipeline has 4 elements (1 element = 8
Byte)/1T throughput. The extended memory control unit EMU has one load/store pipeline, and its throughput is 1 element/1T. Therefore, VU has N=4 times the throughput compared to EMU. A case will be explained in which the EMU transfers 2KB (2048 bytes) of data from address 10000 (HEX) to the MSU. EMU's throughput is 1 element/1T, but to improve access efficiency, access is performed at 4 elements/4T. 2KB of data is
Equivalent to 64 32-byte accesses. Table 1 shows an example of this EMU access. 32 bytes (DEC) in ascending order from address 10000 =
Create a 2KB address string in units of 20 bytes (HEX). Since N=4, create a group for every 4 addresses and add a NO within the group. First, accesses are made to the main memory in ascending order for the NO within the group. next,,
and send access in the same way. Figure 5 shows the LS when using the method of the present invention.
The relationship between Busy and time is illustrated. This corresponds to the conventional example shown in FIG. By the method of the present invention, the slope on the LS time graph is
VU access and EMU access are equal.
Furthermore, even if a temporary LS Busy conflict occurs between VU access and EMU access, it is within the LS Busy time and throughput is guaranteed. Embodiment Circuit FIG. 1 shows the configuration of an embodiment of a request address generation circuit according to the present invention. This circuit is provided within the EMU and used for EMU access. In the figure, 11 is the OP CODE register, 12
is SA register, 13 is EL register, 14 is adder, 15 is RA register, 16 is control counter, 17 is EL-UP register, 18 is EL-
LW register, 19 is REQ control circuit, 2
0 represents a shift control circuit. The OP CODE register 11 is a register that holds a load or store operation code. The SA register 12 is a register that holds an address (SA) for starting access. The EL register 13 is a register that holds the number of elements (EL) to be loaded or stored. The adder 14 is a circuit that adds distance to the current address to generate the next request address. As the constant to be added, one of the following is selected: 0 1d=20 (HEX) 2d=40 (HEX) 3d=60 (HEX) Nd=80 (HEX). The RA register 15 is a register that holds the current request address, and its output is fed back to the adder 14 in the same way as it is transferred to the MCU. The control counter 16 is composed of a 4-bit shift register, and is a circuit that controls the group scanning sequence. The number of control stages is four. The EL-UP register 17 contains the access throughput multiple N = 4 set for EMU access.
The number of groups obtained as a result of dividing the number of elements (EL) by is set. It is decremented by 1 each time an address is generated, and when it reaches 0, it is reset, and the process ends in 4 rounds. In the EL-LW register 18, a fraction obtained by dividing the number of elements (EL) by N=4 is set, and 0 is set.
Unless otherwise, 1 is subtracted at the end of one cycle of the EL-UP register 17. The REQ control circuit 19 notifies the MCU that the request address is valid.
Output REQUEST VALID. The shift control circuit 20 shifts the control counter 16 by one stage each time the scanning for each group completes one cycle. When an access is issued from the EMU to the MSU, parameters such as an operation code (OP CODE) indicating a load or store, a start address (SA), and the number of elements (EL) are given from the scalar unit SU. When issuing an access request from EMU to MCU, each of the above parameters is
OPCODE register 11, SA register 12, EL
It is set in the register 13 by a control signal inside the EMU called EMU-REQ, and is held until the end of the operation. The constant added by adder 14 to the addresses of SA register 12 and RA register 15 is selected when the RA register hair address is set from SA register 12. These values are designated by control counter 16. The constant Nd=80 (H) is always selected when the path from RA register to RA register is selected. Only 0 to 27 bits of the number of elements are set from the EL register 13 to the EL-UP register 17. This indicates "group NO" when the number of elements is at a 4-element boundary, and indicates "group NO-1" when the number of elements is not at a 4-element boundary. The group number is the number of groups obtained by dividing the number of elements by four. The value of the EL-UP register 17 is set at the timing when stages 0, 1, 2, and 3 of the control counter 16 are set, and the value is subtracted by 1 by the REQ control circuit 19. The EL-LW register 18 is set and holds only 28 BIT and 29 BIT, which are the number of elements, when the 0BIT stage of the control counter 16 turns ON. EL-UP register 17 becomes 0 and EL-UP register 17 becomes 0.
When the LW register 18 is not 0, a request is generated to the REQ control circuit 19, and then 1 is subtracted. The shift control circuit 20 controls the shift of the control counter 16. That is, (EL-LW register = 0)・(EL-UP register =
The control counter 16 performs subtraction using the logic 0)+(EL-LW register subtraction). An example of operation is shown next. EMU start address (SA) Address 1000 Number of elements (EL) 256 elements Operation code As STORE, the following steps are performed. OP CODE register = STORE CODE SA register = 10000 (HEX) EL register = 100 (HEX) are set. The EMU-REQ signal turns on the control counter 0. The constant of the adder is 0
is selected and RA register 10000 is set. EL-UP=16 (DEC) EL-LW=0 is set. The path from RA register to register is selected and the constant = 80 (HEX) is selected. If REQ-VAL is issued, the value of EL-UP is
Subtract by 1. Add 80 (HEX) to the RA register. Repeat the above steps until EL-UP becomes 0. When EL-UP becomes 0, EL-LOW becomes 0, so the control counter is shifted from 0 to 1, selects 1d=20 (HEX) as the adder constant, and changes the path from SA register to RA register. Select and set RA register = 10020.
Set 16 (DEC) to EL-UP. RA register − Select RA register as path,
Select 80 (HEX) as the adder constant.
After issuing REQ-VAL, EL-UP adds 80 (HEX) to the RA register, which is subtracted by 1, and repeats this until EL-UP becomes 0. If EL-UP becomes 0, EL-LOW becomes 0
Therefore, the control counter is shifted from 1 to 2, and the adder constant is 2d=40.
Select (HEX). Set RA register = 10040. Set EL-UP to 16. Do the same thing. If EL-UP becomes 0, EL-LOW becomes 0
Therefore, shift the control counter from 2 to 3, select 3d=60 (HEX) as the adder constant, set 10060 in the RA register,
Set EL-UP to 16. Do the same thing. [Effects of the Invention] According to the present invention, when an access source with a large access throughput accesses with consecutive addresses, it is hardly affected by the access by an access source with a small access throughput. Access efficiency can be maintained.

【table】

【table】 [Brief explanation of drawings]

FIG. 1 is an example configuration diagram of a request address generation circuit in one embodiment of the method of the present invention, FIG. 2 is a system configuration diagram of an information processing device to which the method of the present invention can be applied, and FIG. 3 is an example of access using the conventional method. FIG. 4 is a graph of another access example using the conventional method, and FIG. 5 is a graph of an access example according to an embodiment of the present invention method shown in FIG. In Figure 1, 11 is the OP CODE register;
12 is SA register, 13 is EL register, 14 is adder, 15 is RA register, 16 is control counter, 17 is EL-UP register, 18 is
EL-LW register, 19 is a REQ control circuit, and 20 is a shift control circuit.

Claims (1)

[Scope of Claims] 1. In a system in which a plurality of access sources, including access sources with different memory access throughputs, mainly perform continuous access to addresses in main memory, a first access source having a certain first access throughput,
compared to the first access source, the access throughput is smaller than the first access throughput, and the access throughput is 1/1/1 of the first access throughput.
a second access source having a second access throughput that is an access throughput in the ratio of n (n is an integer), and the second access source accesses consecutive addresses to the main storage device. an address update control means that updates the address in the same direction as the access direction of the first access source at an address interval n times the access unit; and an address update control means that sequentially adds the address of the access unit to the start address of the access. and address addition means for supplying the address update control means to the address update control means, the second access source updates its own access address by the address update control means and the address addition means, and at this time updates the access address. Arrange the address sequence in a fixed direction for each access unit, divide the address sequence into n groups, assign the same number to each group, select sequentially numbered addresses for each group divided by n, and A main memory control method characterized by updating an access address by changing an address string so that addresses of the same number in each group are accessed for each number.