JPH0414437B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a dynamic memory circuit which is an improved sense amplifier.

(Prior art) MOS memory has been improving its capacity and speed with the advancement of semiconductor manufacturing technology, but in particular, the development of one-transistor type dynamic memory has already entered the 256K era, and its capacity and speed have improved. Application fields are not limited to general-purpose computers, but have come to be used in personal computers, various terminal devices, and home appliances.

As the capacity and speed of IC memory increases, noise generation inside the chip has become a problem. In particular, an increase in the power supply current and ground current causes the power supply potential and ground potential, which should originally be constant potentials, to fluctuate due to their own resistance components, leading to cases where the operating margin becomes narrower. One of the largest internal noises is the ground potential fluctuation that occurs during amplification of the sense amplifier.

This ground potential fluctuation will be explained below using the drawings. Figure 4 is a block diagram showing the configuration of an example of a conventional dynamic memory circuit, Figure 5 is a circuit diagram of its sense amplifier section, Figure 6 is an operating waveform diagram of the sense amplifier section, and Figure 7 is word line drive. FIG. 8 is a circuit diagram of the signal generation circuit, FIG. 8 is a circuit diagram of the row decoder, FIG. 9 is a circuit diagram of the column decoder, and FIG. 10 is a circuit diagram of the sense amplifier activation signal generation circuit.

Memory cell arrays 1 and 1' have word lines 3,
It is composed of a dummy word line 4, bit lines 7 and 8, a cell 5, and a dummy cell 6. Further, bit lines 7 and 8 form a flip-flop with each other by sense amplifier 2. In addition, the column selection signal YS selected by the column address, the bit line and the I/O bus 10,
11 is also included in the sense amplifier 2.

Next, the operation will be explained with reference to the operation waveform diagram in FIG. Internal row address signal X ₀ according to external address input by address buffer activation signal AE,
Generate X ₁ ,...Xn. This signal is used as an input to the X decoder (FIG. 8) to select a word line.
The selected word line 3 and the corresponding dummy word line 4 are driven by the word line drive signal RA, and as a result, a minute signal corresponding to the content held in the cell 5 appears on the bit lines 7 and 8 (time t ₂ ). bit line 7,
The minute signal appearing on 8 is amplified by flip-flop transistors Q ₄ and Q ₅ forming a sense amplifier. The amplification method is performed by connecting the node _N1 , which is a common source node of the flip-flop, to a ground node through an activation transistor _Q6 having a sense amplifier activation signal SE at its gate potential. There is a sense amplifier for each bit line.
Since the minute signals on each bit line are simultaneously amplified, the current flowing to the ground node becomes very large. Generally, the node N ₁ connects the common sources of each sense amplifier to combine them into one, and the transistor Q ₆ has a very large capacity.

In an LSI memory, the node potential of the chip is not always a perfect ideal potential, but has some impedance. These include parasitic resistance existing on the chip, Al wiring resistance, bonding lines, and inductance existing in the package. On the other hand, in order to speed up the access time, which is the most important parameter of a memory, it is necessary to discharge the bit line at high speed. This is because in order to activate the column selection signal YS which transmits a signal to the I/O bus, it is necessary that the bit line is set to high level/low level.

In order to amplify the sense amplifier at high speed,
It is necessary to increase the capacity of transistor _Q6 , but
As a result, the level of the internal ground potential changes in proportion to the current flowing through the transistor _Q6 , causing a change in the operating margin. For example, variations in the level of a write signal input at the same time as variations in the ground potential, variations in activation internal signals over time, variations in floating level, etc. occur, leading to a reduction in the operating margin, especially the power supply margin.

In other words, in conventional dynamic memory circuits, the internal ground potential fluctuates due to the activation of the sense amplifier, reducing the power supply margin and
The drawback was that it hindered high-speed operation.

(Objective of the Invention) An object of the present invention is to provide a dynamic memory circuit that can prevent the reduction in power supply margin due to fluctuations in the internal ground potential that occur when the sense amplifier is activated in a large-capacity memory, and can operate at high speed. become.

(Structure of the Invention) The dynamic memory circuit of the present invention includes
A plurality of memory cells arranged in a matrix in the column direction, a plurality of word lines for selecting the plurality of memory cells in each row, and a plurality of word lines for selecting the plurality of memory cells in correspondence with each other for each column. A plurality of bit lines that transmit data in a corresponding manner, a plurality of sense amplifiers that respectively amplify the signals of the respective bit lines when activated, and a plurality of sense amplifiers that conduct in accordance with a sense amplifier activation signal. A dynamic memory circuit comprising: a first transistor that activates a sense amplifier; and column selection means that selects one of the output signals of the plurality of sense amplifiers in accordance with a column selection signal. A memory cell, a plurality of bit lines, and a plurality of sense amplifiers are divided into a plurality of blocks, each of which has a second transistor connected in parallel with the first transistor and turned on in accordance with a sense amplifier activation control signal. and a second transistor of a block including a sense amplifier from which the output signal is selected is made conductive when the first transistor is conductive, according to the sense amplifier activation signal and the column selection signal. The device includes sense amplifier activation control means for generating an amplifier activation control signal.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a main part of an embodiment of the present invention, FIGS. 2a and 2b are circuit diagrams of a sense amplifier activation control signal generating circuit, and FIG. 3 is an operating waveform diagram thereof.

In this embodiment, a memory cell array is divided into two memory cell groups, a memory cell block 21 and a memory cell block 22, according to example addresses, and each memory cell block 21 and 22 receives internal column address signals Y0 and ₂₂ , respectively. Transistors _Q14 and _Q20 , which are controlled by different sense amplifier activation control signals SEA and SEB generated from ₀ , are used as sense amplifier activation transistors for each memory cell.
It consists of connecting Q ₁₅ and Q ₂₁ in parallel.

In the figure, 23 is a word line, 24 is a dummy word line, and 25 and 26 are I/O buses. In the memory cell block 21, a sense amplifier consisting of transistors _Q10 to _Q13 is connected between the bit lines 27 and 28, and a sense amplifier (not shown) having the same configuration is connected between the bit lines 29 and 30, respectively. Nodes _N10 of each sense amplifier are commonly connected and grounded via an activation transistor _Q15 . Similarly, a sense amplifier consisting of transistors Q ₁₆ to _{Q 19} is connected between bit lines 31 and 32, and the same sense amplifier is connected between bit lines 33 and 34, respectively, and an activation transistor is connected to node N ₁₁ .
Q ₂₁ is connected.

The feature of the present invention is that instead of making all common source nodes of the flip-flops of the sense amplifiers common, an independent signal is generated for each of multiple blocks, and the logic of the column address input is added to the activation signal. The difference is in the amplification speed of the two. The embodiment shown in FIG. 1 is a case where it is divided into two parts.

The row address selects the word line, and the column address selects the bit line, but the bit line that needs to speed up the sense amplifier is selected by the column address and connected to the I/O bus. The refresh operation of the other bit lines only needs to be completed before the operation of the I/O bus is completed. The common source nodes N ₁₀ and N ₁₁ are driven by conventional activation transistors Q ₁₅ , Q ₂₁ and sense amplifier activation control signals SEA, SEB controlled by internal column address signals Y ₀ , ₀ in particular. It is drawn simultaneously by transistors Q ₁₄ and Q ₂₀ .
For example, when the external input of column address A _YO is low level, internal column address signal Y ₀ becomes low level, ₀ becomes high level, and the sense amplifier activation control signal
SEA becomes high level according to the sense amplifier activation signal SE, but the sense amplifier activation control signal
SEB remains at a low level. Therefore, the ability to pull the node N ₁₀ to the ground potential increases, but the ability to pull the node N ₁₁ to the ground potential remains small. As a result, the transition of bit line 27 or 28 drawn by contact N ₁₀ to a low level ends faster than on bit line 31, 32 side. Furthermore, since the current at all ground potential points flows in a time-divided manner, the potential fluctuations that occur are thereby reduced. In other words, it is possible to achieve higher speeds while keeping ground potential fluctuations small. This effect will increase if the number of divisions based on column addresses is increased.

Note that the present invention is applicable not only to single-clock type dynamic memories in which row addresses and column addresses are input as independent terminals, but also to multi-address type dynamic memories in which row addresses and column addresses are input in a time-sharing manner. It can also be applied to memory. Particularly in the multi-address type, this becomes very effective when the row address includes an address other than the refresh address.

Further, in the above description, an N-channel MOS transistor is used as the transistor, but it goes without saying that the present invention can be similarly applied to other insulated gate field effect transistors.

(Effects of the Invention) As explained in detail above, the dynamic memory circuit of the present invention has the above-described configuration, and is grounded by the ground power supply current accompanying amplification in the sense amplifier, which is a problem in large-capacity dynamic memory circuits. This has the effect of simultaneously improving access time by reducing potential fluctuations and speeding up the operation of the selected bit line.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the main part of an embodiment of the present invention, FIGS. 2a and b are circuit diagrams of its sense amplifier activation control signal generation circuit, FIG. 3 is its operating waveform diagram, and FIG. 4 5 is a block diagram showing the configuration of an example of a conventional dynamic memory circuit diagram, FIG. 5 is a circuit diagram of its sense amplifier section, FIG. 6 is an operating waveform diagram of the sense amplifier section, and FIG. 7 is a word line drive generation circuit. 8 is a circuit diagram of a row decoder, FIG. 9 is a circuit diagram of a column decoder, and FIG. 10 is a circuit diagram of a sense amplifier activation signal generation circuit. 21, 22...Memory block, 23...Word line, 24...Dummy word line, 25, 26...
I/O bus, 27-34 bit lines, _N10 , _N11 ...
...node, P...column decoder recharging signal,
Q ₁₀ ~Q ₂₁ ……N channel MOS transistor, RA
...Word line drive signal, SE...Memory cell activation signal, SEA, SEB...Sense amplifier activation control signal, YE...Column selection signal drive signal, YSA,
YSB...column selection signal, _Y0 , ₀ ...internal column address signal, Vcc...power supply.

Claims (1)

[Claims] 1 A plurality of memory cells arranged in a matrix in the row and column directions, a plurality of word lines for selecting the plurality of memory cells in each row, and a plurality of word lines for selecting the plurality of memory cells in correspondence with each other; A plurality of bit lines that correspond to and transmit data for each column,
a plurality of sense amplifiers that respectively amplify signals on the respective bit lines when in an activated state; and a first transistor that conducts in accordance with a sense amplifier activation signal to activate the plurality of sense amplifiers. and column selection means for selecting one of the output signals of the plurality of sense amplifiers according to a column selection signal, at least the plurality of memory cells, the plurality of bit lines, and the plurality of sense amplifiers. The amplifier is divided into a plurality of blocks, and each of these blocks is provided with a second transistor connected in parallel with the first transistor and turned on in accordance with the sense amplifier activation control signal, and the sense amplifier activation signal and the column are connected in parallel. Sense amplifier activation that generates the sense-up activation control signal that makes conductive a second transistor of a block including a sense amplifier from which the output signal is selected when the first transistor is conductive, according to a selection signal; A dynamic memory circuit characterized by being provided with a control means.