JPH0414808B2 - - Google Patents

Description

[Detailed Description of the Invention] (A) Technical Field of the Invention The present invention relates to a master slice type semiconductor circuit device,
In particular, on a quadrilateral semiconductor chip with metal wiring and diffused resistors arranged perpendicular to the wiring area, such as an aluminum gate master slice type semiconductor circuit device, The present invention relates to a master slice type semiconductor circuit device in which a logic circuit which is generally difficult to construct or is not constructed using cells on an example logic cell is integrated on at least one of four corners.

(B) Background and Problems of the Technology The present inventors previously arranged metal wiring and diffused resistors in an aluminum gate master slice type semiconductor circuit device in such a manner that they were perpendicular to each other on the wiring area. We proposed that the desired wiring be achieved by appropriately connecting the two. FIG. 1 shows the overall concept of such a master slice type semiconductor circuit device. In the figure, reference numeral 1 is a master slice type semiconductor circuit device, and 2 is a logic cell column, which constitutes a basic cell column and/or a flip-flop column, and 3, 3, ... 3 are arranged on the left side of the figure. input/output cells (the whole constitutes a cell column...the same applies hereafter), 4, 4,...4 are placed on the bottom side in the figure, input/output cells 5, 5,...5 are placed on the right side in the figure Input/output cells 6, 6, ... 6 are input/output cells arranged on the upper side of the figure, 7, 7 are power terminals, respectively;
8, 8,... are the first wiring area, 9, 9,... are the second wiring area
The wiring areas 10, 10, . . . represent general-purpose use areas according to the present invention.

The second wiring region 9 corresponds to a horizontally long space in the figure between the upper ends of the logic cell rows 2, 2, . . . and the input/output cell rows 6, 6, . In addition, although the above-mentioned general-purpose use areas 10, 10, etc. are marked with circles in the case shown in the figure, they do not actually exist in the master slice type semiconductor circuit proposed by the inventors. In a device, there is a free area, so to speak, and this free area can be considered to be called a general-purpose use area.

Then, the first wiring area 8 and the second wiring area shown in FIG.
The wiring region 9 is filled with patterns such as those shown in FIG. 2A and FIG. 2B, since this is, for example, an aluminum gate master slice type semiconductor circuit device as described above. That is, in the first wiring region 8, a metal wiring 11 extending vertically is provided, and a diffusion resistor 12 extending horizontally is provided on the lower surface of the metal wiring 11, and the electrical connection between the two is achieved by providing a contact window 13. It will be done. Also the second
In the wiring region 9, a metal wiring 11 extending in the horizontal direction is provided, and a diffusion resistor 12 extending in the vertical direction is provided on the lower surface of the metal wiring 11, and electrical coupling between the two is performed by providing a contact window 13.
Needless to say, connections between patterns in the wiring area and cells in the logic cell column and input/output cells are also made as necessary.

In the case of the master slice type semiconductor circuit device proposed by the inventors as described above, the general-purpose use area 10 shown in FIG. It's easy to become. On the other hand, if you try to configure, for example, a Schmitt trigger circuit, a power-on reset circuit, a delay circuit, a mono multivibrator, an analog switch circuit, etc. using the cells in the logic cell column 2 described above, a large number of Cells may become occupied or, in some cases, extremely difficult or impossible to configure.

(C) Object and Structure of the Invention The present invention aims to solve the above-mentioned problems, and as described above, aims to effectively utilize the general-purpose area 10, which tends to become a vacant area. Therefore, in the master slice type semiconductor circuit device of the present invention, logic cell rows each consisting of one or both of a basic cell row and a flip-flop row are arranged at a plurality of row intervals, and the plurality of logic cell rows are arranged at intervals of a plurality of rows. Input/output cell rows are arranged on four sides so as to wrap around the logic cell rows, and wiring areas are provided between the logic cell rows and between the input/output cell rows and the logic cell rows. In a master slice type semiconductor circuit device having a rectangular chip, at least one of the four corners of the rectangular chip is configured as a general-purpose area, and the above-mentioned logic is arranged on the general-purpose area. It is characterized by the integration of logic circuits that cannot be constructed by combining only the logic cells that make up the cell array. This will be explained below with reference to the drawings.

(D) Embodiment of the Invention FIG. 3 shows an embodiment of a logic circuit constructed in the general-purpose area shown in FIG. 1, and FIG. 4 is an explanatory diagram illustrating its operation.

One embodiment of the master slice type semiconductor circuit device of the present invention may also be considered to have a configuration as shown in FIG. That is, it has a plurality of logic cell rows 2, a plurality of input/output cells 3, 4, 5, 6, a power supply terminal 7, a first wiring area 8, a second wiring area 9, and has four corners of the device 1. It may be considered that a general use area 10 exists.
Of course, each wiring area 8 and 9 may be considered to have a pattern as shown in FIG.

In the case of the present invention, the general use area 1 as described above is
For example, a logic circuit as shown in FIG. 3 is integrated within the 0. In the case shown in FIG. 3, the logic circuit is shown as being a Schmitt trigger circuit. That is, the reference numeral 10 in the figure represents the general-purpose area shown in FIG. 1, 14 represents an inverter, and 15 and 16 represent two-input NAND circuits. Further, IN is an intra-area input terminal and is electrically connected to the patterns in wiring areas 8 and/or 9, and OUT is an intra-area output terminal and is electrically connected to the patterns in wiring areas 8 and/or 9. Connected.

For example, when constructing a Schmitt trigger circuit as described above, the circuit is connected to V io and V _io as shown in FIG.
The inverter 14 shown in _FIG . 3 depends on the upper point shown in FIG. 4, and the 2-input NAND circuit 15 depends on the lower point shown in FIG. is shown in figure 2
Together with the input NAND circuit 16, each must be designed with special transistor dimensions, and cannot be constructed from the basic cells in the logic cell array 2 described above. Of course, this does not mean that it cannot be configured by using a large number of basic cells, but it becomes virtually impossible to configure it when considering the usage efficiency of the basic cells.

The logic circuit configured within the general use area 10 is
Although not limited to the above-mentioned Schmitt trigger circuit, power-on reset circuit, delay circuit, mono-multivibrator, and analog switch, in any case, these logic circuits are connected to the power supply terminal 7 shown in FIG. It is desirable that consideration be given so that wiring can be made to all terminals (terminals of basic cells and input/output cells) other than 7 (V _cc and V _ss shown in the figure).

(E) Effects of the Invention As explained above, according to the present invention, it is possible to configure a desired logic circuit within the general-purpose use area 10 shown in FIG. It becomes possible to use it often.

[Brief explanation of drawings]

1 and 2 show a master slice type semiconductor circuit device, which is the premise of the present invention, and show the configuration of an embodiment of the present invention, and FIG. 3 shows a configuration within the general-purpose use area shown in FIG. FIG. 4 shows an explanatory diagram for explaining the operation of one embodiment of the logic circuit. In the figure, 1 is a master slice type semiconductor circuit device;
2 is a logic cell column, 3 to 6 are input/output cells, 7 is a power supply terminal, 8 is a first wiring area, 9 is a second wiring area, 10 is a general use area, 11 is a metal wiring,
12 is a diffused resistor, 13 is a contact window, 14 is an inverter, and 15 and 16 are two-input NAND circuits.

Claims (1)

[Scope of Claims] 1. Logic cell rows consisting of either one or both of basic cell rows and flip-flop rows are arranged at a plurality of row intervals, and a plurality of logic cell rows are arranged on four sides in a manner that wraps around the plurality of logic cell rows. A rectangular chip is formed by arranging input/output cell rows, with wiring areas provided between the logic cell rows and between the input/output cell rows and the logic cell rows. In the master slice semiconductor circuit device, at least one of the four corners of the rectangular chip is configured as a general-purpose area, and on the general-purpose area there are logic cells constituting the logic cell array. 1. A master slice type semiconductor circuit device, characterized in that it integrates logic circuits that cannot be constructed by a combination of only two.