JPH0414835B2 - - Google Patents

Description

Detailed Description of the Invention This invention relates to a two-dimensional solid-state imaging device using a gate accumulation method using an electrostatic induction transistor according to the present invention. The present invention provides a capacitive solid-state imaging device.

A typical configuration of a two-dimensional solid-state imaging device (SIT area sensor) using a conventional gate accumulation method using static induction transistors (hereinafter referred to as SIT) is shown in FIG. GL1, GL2,
GL3, ..., GLm indicate the address gate line (vertical signal address line) to the matrix [Cij] of each pixel, and SL1, SL2, SL3, ...SLn
indicates a signal output line (signal readout line, horizontal signal output line) from the matrix [Cij] of each pixel. The gate of each pixel is connected to the vertical signal address line GLj via the gate capacitor C _G.
The drains are commonly connected to the horizontal signal output line SLi, and each horizontal signal output line SLi is commonly connected to the video output line 3 via the switch MOSQs. Each pixel [Cij]
Signal reading is performed using vertical shift pulses φ _G1 , φ _G2 , φ _G3 , ..., φ _Gn output from vertical shift register 1 to each address gate line, and a horizontal shift register for selecting each horizontal signal output line SLi. X-Y of horizontal shift pulses φ _S1 , φ _S2 , φ _S3 , ..., φ _So outputted from 2 to the gate of switch MOSQs
This is carried out using an addressing method, and the optical information of each pixel is sequentially outputted from the output terminal 4. The video line 6 is biased to the video voltage V _DD via the load resistor R _L , and in the conventional method shown in Figure 1, the DC power flowing between the drain and source of the SIT of each pixel is Detected. optical information is
It is accumulated in the gate capacitor C _G of SIT, and when the height of address gate pulse φ _Gj is low, it approaches non-destructive readout, and when the height of φ _Gj becomes 2.5V or more, it becomes destructive readout. . The pulse width in this case is 100 nsec to several μsec. All the source regions of the SIT of each pixel Cij are set to the ground potential.

The inventors of the present application have already filed a patent application for a solid-state imaging device using the gate accumulation method with the configuration shown in FIG. Special request 1988-
No. 21688 and Japanese Patent Application No. 58-26932.
An example of the signal readout method will be explained based on the operating waveforms shown in FIGS. 2 and 3. Figure 2 is Tokugansho.
56-204656, and in the _circuit configuration of FIG _. 1, _the signal readout lines SL1, _SL2 , Select SL3, ..., SLn one by one, and apply address gate pulses φ _G1 , φ _G2 , φ _G3 , ..., within the selected period (one horizontal period).
φ _Gn to each address gate line GL1, GL2, GL3,
..., GLm is applied to perform X-Y addressing. In the readout method using the operating waveforms shown in Fig. ₂ , the signal readout lines SL1, _SL2 , ..., _SLi- 1
is selected, and within the period of φ _S1 , φ _S2 ..., φ _Si-1, the pulse of φ _Gj is on the line GLj (i
−1) times. Once the pixel signal of Cij is read out, then the same pixel Cij
The period until the signal is read out is the optical integration period T _LI . In the above readout method, address gate pulses φ _Gj are applied to the address gate lines GLj as many times as there are signal readout lines in the X-Y matrix. . Therefore, the gate pulse φ _Gj of the above (i-1) times is applied to the gate of pixel Cij when it is not selected.
The signal readout format shown in FIG. 2 has the disadvantage that the carriers in the gate in the accumulated state tend to escape because of the addition of . The above leakage characteristics depend on the height and width of the gate pulse φ _Gj , and conditions for completely non-destructive readout are required. For example, the height of φ _Gj is 1V or less, and the pulse width is 100nsec or less. In view of the above drawbacks, the present inventors proposed a new signal readout method in patent application No. 58-21688.
and Japanese Patent Application No. 58-26932. FIG. 3 shows an example of the operation waveform. The operating waveform in Fig. 3 is that when reading out a specific pixel Cij, first select the address gate line GLj, apply the gate pulse φ _Gj , and then apply the gate pulse voltage V _G for a period (one time). (horizontal readout period),
This method detects the flowing current by selecting the signal readout line SLi and using the shift pulse φ _Si to flow a DC current from the power supply V _DD through the load resistor R _L between the drain and source of the SIT of the selected pixel Cij. . This method also uses a capacitor at the gate of each pixel.
The problem is the height and width of the pulse φ _G applied via C _G , and as the gate pulse voltage V _G increases, the carrier accumulated in the gate capacitor leaks in an extremely short period of time within one horizontal period. End, φ _S1 ,
As φ _S2 , . . . are sequentially selected, the rear pixel signals read out leaked accumulated information, and the area sensor no longer functions perfectly. Furthermore, over one horizontal period, the gate potentials of the pixels C _1j , C _2j , ..., C _ij , ..., Cnj in one row lined up on G _L selected by φ _Gj are as follows:
It must be held at a constant potential determined by the division of C _G and the input capacitance, but the time constant is required to be longer than one horizontal period, and the potential at the gate where it is accumulated fluctuates, so the gate voltage V _G is Even if it is set low, the carrier will flow out little by little, and in turn φ _S1 ,
_As φ _S2 , . In the system shown in FIG. 3, the gate pulse φ _G serves as a high refresh pulse of V _R during one horizontal retrace period, and has the function of refreshing the carriers accumulated in the gate.

Both formulas shown in Figures 2 and 3 above are
The problem was the height and width of the address gate pulses to be applied to the address gate lines. both
The DC current flowing between the drain and gate of SIT is
- This is a detection method based on the Y address, and in the read state of a specific pixel Cij, the voltage flows from the video power supply V _DD through the load resistor R _L to the video line 3,
Through the switch MOS and signal readout line SLi
There is a DC path flowing between the drain and source of Cij's SIT.

Furthermore, as shown in Japanese Patent Application No. 57-217758, the inventors of the present invention have improved the operation method shown in FIG. We proposed a method in which the parallel signal outputs on each signal readout line that are connected and read out at the vertical signal address are input to the CCD, and the readout part is the CCD. However, this signal readout method also detects the DC current flowing between the drain and source of each pixel.
In addition, it was necessary to connect a load resistor with the same value and a video power supply voltage on each signal readout line, making the structure and operation complicated.

Therefore, the inventors of the present application operate with one load, one video bias power supply, and instead of detecting the conventional DC current, the capacitor of the signal readout line
C _SL 's charging by pre-charge transistor,
A discharge (optical signal information is included in this) due to the impedance between the drain and source of the SIT being lowered by the gate address pulse φ _Gj , and
Load resistance R _L from video power supply by switch MOS
We have discovered a completely dynamic operating method of signal detection by recharging through the sensor, which is easier to configure and operate than conventional operating methods, and is particularly operationally stable even as a large-capacity area sensor, with low switching noise and low switching noise. It was found that the power consumption is low. The reason why the signal readout line SLi is once charged using a precharge transistor is that the potential on the signal readout line SLi changes depending on the light intensity during the optical integration period.
This is because a uniform signal can be read out by applying the gate pulse φ _Gj after returning to a constant potential.

The purpose of the present invention is to
In an area sensor, it operates completely dynamically by charging the signal readout line capacitor with a precharge transistor, discharging with an address gate pulse, and recharging with a switch MOS transistor. Output signals can be obtained, high-speed reading is possible,
Low power consumption due to fully dynamic operation.
The purpose of this invention is to provide a new SIT area sensor configuration that can stably and uniformly read out a large pixel area, and its operating method.

Furthermore, another object of the present invention is to provide a signal readout section of the new area sensor that performs the above-mentioned completely dynamic operation using a CCD instead of reading out from one load.
The purpose is to provide a configuration for output. .

An outline of the present invention will be explained below.

A _pixel Cij (i=1
~n, j=1~m) constitutes an X-Y matrix, and the vertical gate address lines GL ₁ ,
GL ₂ , GL ₃ , ..., GL _n are connected to the gates of SITs forming each pixel C _1j , C _2j , C _3j , ..., _Coj on each GL _j (j=1 to m) via gate capacitors _CG . connected,
The signal readout lines SL ₁ , SL ₂ , SL ₃ , ..., SL _o correspond to each pixel C _i1 , C _i2 , C _i3 , on each SL _i (i=1 to n).
..., a gate accumulation type SIT area sensor commonly connected to the drains of SITs constituting C _in , and each signal readout line SL _i (i = 1 to n) is connected to the ground potential with a predetermined distance. Capacitor C _SL
and are commonly connected to a predetermined power supply voltage V _DD ′ through a precharge transistor Q _p ,
Furthermore, it is connected to the first switching transistor _QT , and each switching transistor
Q _T are each commonly connected to the video output line through a switching transistor Q _S ,
The video output line has one load resistor R _L and one
The gates of each switching transistor Q _T are all connected in common so that a transfer pulse φ _T is applied to each switching transistor Q _T .
A predetermined capacitor C _T is provided between the connection node between Q _T and each switching transistor Q _S and the gate of the switching transistor Q _T , and
A capacitor is connected between the connection node and ground potential.
C _SL ′, and the size relationship of each capacitor is C _G <
C _SL ′C _T C _SL , and each vertical gate address line GL ₁ , GL ₂ , GL ₃ , ..., GL _n receives a vertical shift pulse φ _G1 , from a vertical shift register.
φ _G2 , φ _G3 ,..., φ _Gn are applied, and horizontal shift pulses φ _S1 , φ _S2 , φ _S3 ,..., φ _Sn are applied from the horizontal shift register to the gates of each switching transistor Q _S.
In the configuration of a two-dimensional solid-state imaging device configured such that X- _Y addressing is performed by the application _of With C _SL ′ electrically connected, Qp is turned on in advance by precharge pulse φp, and the capacitors of each signal readout line SL1, SL2, SL3, ..., SLn are connected to each other, C _SL +C _SL ′ After charging all of them to a predetermined voltage level, the pixels C _1j , C _2j , C _3j , ..., lined up in GLj
By simultaneously applying the address gate pulse φ _Gj to the gate of C _oj via the gate capacitor C _G ,
When the SIT of each pixel described above is made conductive, a discharge ΔV _SL corresponding to the amplified signal of the optical information stored in the gate of each SIT occurs from a constant voltage level V _SL of C _SL +C _SL ′, and after this, After turning off φ _T and turning OFF Q _T , the horizontal shift pulses φ _S1 , φ _S2 , φ _S3 ,...
By applying φ _So to the gate of each switch transistor Qs, the discharge amount of the capacitor C _SL ′ is recharged from the video voltage V _DD through the load resistor R _L , and the output terminal has the voltage of each pixel. _C1j , _C2j , _C3j ,
..., information on C _oj will be obtained sequentially. One horizontal readout operation is completed with the above operation, and then the image of each pixel C _1j+1 , C _2j+1 , C _3j+1 , ..., C _{oj+1 on the vertical address gate line GLj+1 is completed in the same manner.} The signals are read out sequentially in the next horizontal period. In this way, all pixels are sequentially read out. A function may be provided to refresh each pixel column simultaneously by applying a refresh gate pulse during the horizontal retrace period. Selection of the height of the gate pulse φ _Gj is easier than in the conventional method, and the height of the gate pulse φ Gj is easy to select.
It can fully operate at around 3V. The feature of signal readout in this method is that all the image information of each pixel is transferred to the capacitor on the readout signal line at the same time as the address gate pulse _{φ Gj} is applied. The self-constant at the output end is a time constant for charging C _SL ′, and since C _SL +C _SL ′ is not charged, it is easy to increase the speed. Furthermore, the time constant until the information of each pixel is output as an amplified signal on the readout signal line by applying the readout gate pulse φ _Gj uses the impedance between the drain and source of the SIT, so the on-resistance
R _po(SIT) can be made extremely small, and the time constant R _po(SIT)・
(C _SL +C _SL ′) is also extremely small. Because the readout speed is fast and the optical output is an amplified signal, it is possible to configure large-capacity area sensors, and it is possible to configure area sensors of 525 x 525 or more, 800 x 800, and 1000 x 1000. is possible.

The present invention provides an area sensor that can perform high-speed reading and has a large capacity by using the new configuration and reading method as described above. The readout method according to the present invention is not a method of passing a DC current through each pixel and detecting the flowing current, but only handles a complete capacitor charging/discharging signal, resulting in low power consumption.

Furthermore, as mentioned above, one load on the video line,
In addition to the method of connecting one video bias voltage and extracting each pixel signal from one load as a serial signal, by applying the above address gate pulse φ _Gj , each pixel C _1j , C _2j , C _3j , ..., The optical information of C _oj is
Each signal readout line as an amplified signal
Capacitor C _SL + compatible with SL1, SL2,..., SLn
Since it is accumulated as the discharge amount of C _SL ′, it is output on each signal readout line as a parallel signal, and these signals are input to the CCD at the same time.
It is also possible to extract the output signal as a CCD output. Since the readout method of the two-dimensional solid-state imaging device according to the present invention basically utilizes charging and discharging of the capacitor of each signal readout line, optical information is primarily transmitted on each signal readout line as a parallel signal. A method of simultaneously inputting these analog signals to the CCD and extracting them as CCD analog outputs will be described later as another embodiment of the present invention.

FIG. 4 is a diagram for explaining the principle of a signal readout method of a two-dimensional solid-state imaging device according to the present invention, FIG. 4a is an operation circuit of one pixel portion, and FIG. 4b is
is the operating waveform. In Figure 4 a, one pixel
C _ij is composed of a normally-off static induction transistor and a gate capacitor _CG , the address gate line GLj is connected to the gate of SIT via the gate capacitor _CG , and the signal readout line SLi is connected to the drain 30 of SIT. has been done.
Furthermore, two switching transistors Qp and Qs are connected to the signal readout line SLi, and a video bias voltage V _DD is applied to the drain terminal (output terminal) 10 of Qs via a load resistor R _L. On the other hand, a constant bias voltage V _DD ' is also applied to the drain terminal 20 of Qp. here,
The parasitic capacitance of the signal readout line SLi is indicated as _CSL . Information on the pixel Cij due to the optical input hν is accumulated in the gate of the SIT. Next, the read operation will be explained. As shown in FIG. 4b, when reading the optical information of the pixel Cij, first the precharge transistor Qp is made conductive by the precharge pulse φp, and the signal readout line SLi is set to a predetermined voltage V _DD ′. −
Charge up to Vthp. Here, Vthp is the threshold voltage of the precharge transistor Qp. Next, an address gate pulse φ _Gj is applied to the address gate line GLi, and a gate pulse is applied to the gate portion 31 of the SIT through the gate capacitor C _G of the pixel Gij, and when the SIT is made conductive, the drain 30 and the source 32 of the SIT are connected. Since the impedance of capacitor C _SL decreases, the precharged voltage
V _DD ′−Vthp is discharged. At this time, the gate potential due to the carrier as optical information stored in the gate 31 of the SIT is added by the external address gate pulse φ _Gj to increase the gate potential. The discharge current flowing between the two becomes larger as the light intensity becomes stronger. If the incident photocurrent is I _L and the reverse saturation current of the pin diode around the SIT gate is Is, then the SIT due to carriers generated by light incidence
The potential increase ΔV _G of the gate 31 is approximately given by the following equation. Here, R represents Boltzmann's constant, T represents absolute temperature, and q represents unit charge amount.

ΔV _G =kT/qln(1+I _L /I _S )...(1) On the other hand, the relationship between the gate voltage V _G and drain current I _D of normally-off SIT is an exponential relationship, and I _D ∝expqn/kTV _G ... ...(2) Here, η indicates the ratio of the gate voltage to the intrinsic gate point.

On the other hand, since the incident photocurrent I _L is proportional to the incident intensity P (μW/cm ² ) when the light intensity is weak, in the above readout operation, the discharge current I _DC flowing between the drain 30 and source 32 of the SIT is Photocurrent I _L and I _DC ∝expqn/kTΔV _G = qn/k {kT/qln (1 + I _L /I _S )} I _DC ∝ (1 + I _L /I _S ) ⁿ ...(3) η1 in the case of normally-off SIT Therefore, the discharge current I _DC of the capacitor C _SL charged to V _DD '−V thp is the incident light current I _L or the incident light intensity P
It can be seen that it is proportional to (μW/cm ² ).

In Fig. 4b, the waveform of V _SLi shows the voltage waveform at both ends of C _SL or the voltage change of the signal readout line SLi, and as the address gate pulse φ _Gj is applied, the dotted line in a, the dashed-dot line in b, and the dashed line in c The solid line changes and causes a voltage drop from the voltage of V _DD ′ - Vthp, a corresponds to the dark current state, b corresponds to the normal light intensity, and c corresponds to the saturated exposure state. are doing. In the circuit shown in FIG. 4, the time constant of this discharge is approximately determined by the product of the on-resistance R _{ph (SIT)} between the drain and source of SIT and C _SL . In the dark current state, it is a desirable condition that SIT does not conduct even if the address gate pulse φ _Gj is applied as shown by the dotted line in FIG. 4b. In the dark current state, by applying only the address gate pulse φ _Gj ,
This is because if discharge of _CSL occurs, a dark current signal will appear on the output waveform, and the S/N between it and the normal optical signal will deteriorate.

After discharging _CSL by applying the address gate pulse _φGj as described above, a recharge signal appears at both ends of the external resistor _RL by recharging the discharged amount of _CSL . .

When Qs is made conductive by applying read address pulse φ _Si to the gate of switching transistor Qs, V _DD −Vths is applied to capacitor C _SL .
The voltage up to is charged. Here, Vths is the threshold voltage of the switching transistor Qs. Usually, it is selected so that V _DD −Vths=V _DD ′−Vthp (4). The waveform of V _SLi in Figure 4b is as follows:
It is shown that C _SL is recharged by applying φ _Si , and at the same time as this recharging, a signal indicated by V _put (enlarged waveform) is detected across the load resistor R _L. . A, b, and c are waveforms corresponding to the amount of discharge, respectively, where a corresponds to a dark current state, b corresponds to a normal light intensity, and c corresponds to a saturated exposure state.

The above is the basic operation of the read operation according to the present invention.

As is clear from the above description, the signal readout method of the present invention utilizes the parasitic capacitor _CSL of the signal readout line SLi, and charges _CSL with the precharge transistor Qp and charges CSL with the address gate pulse _φGj. Discharge proportional to optical information of _SL , C _SL via switching transistor (transistor for selection of signal readout line SLi) Qs
By recharging, the information of the internal pixel C _ij is taken out to the load resistor R _L. During readout, the potential of the signal readout line SLi is always charged to a predetermined potential through the precharge transistor Qp,
Gate pulse φ _Gj from the state where a constant voltage is applied between the drain 30 and source 32 of SIT
Addressing is a feature that allows stable and uniform signals to be obtained. The discharge amount of _CSL can be read out very easily via the switch transistor Qs. In the case of the operation shown in Fig. 4, the time constant of the output waveform V _put at the output terminal 10 is the load resistance
R _L , Qs on-resistance R _pNS and signal readout line
Depending on the parasitic capacitance C _SL of SLi, it is approximately (R _L +R _pNS )·C _SL .

Next, FIG. 5 shows an embodiment of the present invention based on the operating principle shown in FIG. 4. FIG. 5 shows the configuration of the SIT area sensor according to the present invention.
Each pixel Cij arranged in an m×n matrix
consists of a normally-off static induction transistor and a gate capacitor C _G , and the gate of each SIT is connected to address gate lines GL1, GL2, GL3,
..., GLm and the gate capacitor _CG in the m columns, while the drain of each SIT is connected to the signal readout lines SL1, SL2, SL3, ..., SLn in the n columns. The source of each SIT is set to a common ground potential for all pixels. Furthermore, a precharge transistor Qp and a switch transistor _QT are connected on each signal readout line SLi, and Qp
The gate line 54 is connected to each signal readout line.
In SLi, the gates of the upper precharge transistors Qp are all connected in common,
Gate line 53 of transistor _QT for switch
are all connected in common at the gates of the switch transistors _QT on each signal readout line. Furthermore, another switch transistor Qs is connected in series to each switch transistor _Qp , and each switch transistor
At the gate of Qs, signal readout line selection pulse trains φ _S1 , φ _S2 , φ _S3 ,
_{. _ DD} is connected. The signal output is obtained from both ends of the load resistor R _L. From the vertical shift register 52, each address gate line GL1,
Address gate pulses φ _G1 , φ G2 , φ _G3 , . . . , φ _Gn are applied onto GL2, _GL3 , . . . , GLm. More specifically, the drain terminals of each precharge transistor Qp are commonly connected to a power supply line 55 to which a precharge voltage V _DD ' is applied.

In FIG. 5, each signal readout line SL1,
The parasitic capacitors of SL2, SL3, ..., SLn are expressed as C _SL , and _{the gate-drain capacitor of the switch transistor Q T is connected to the ground potential between the drain of Q T and the} source terminal of Qs. The capacitor is expressed as C _SL ′. The size relationship of each capacitor is set as C _G <C _SL 'C _T C _SL (5) in order to effectively extract the optical information of each pixel to the video line 51. In addition, each precharge transistor
Qp threshold voltage is Vthp, switch transistor
The threshold voltages of Q _T and Qs are Vtht and Vths, the height of the precharge pulse φp is V _DD ′, the height of the transfer gate pulse φ _T is V _DD ′, each horizontal shift pulse φ _S1 ,
Assuming that the _{heights of} φ _{S2 , .} Conversely, the voltage level at which the signal readout line SLi is precharged and the capacitor C _SL ′ is charged is equal to the voltage level at which it is recharged by the conduction of the switch transistor Qs, such that V _DD ′,
φp height, Vthp, Vtht, φ _T height, Vths, φ _Si
By selecting the height (i=1 to n), reading is performed under stable and uniform conditions. The drains and gates of the SITs constituting each pixel are separated from each other within the same semiconductor substrate so that pixel signals can be separated from each other. Only the drains of the SITs connected to the same signal readout line SLi are electrically shared.

FIG. 6 shows an example of readout operation waveforms of the two-dimensional solid-state imaging device according to the present invention shown in FIG. In the operation waveform shown in FIG. 6, optical information of pixels arranged in an m×n matrix is sequentially transmitted (C ₁₁ , C ₂₁ , C ₃₁ , ..., Cn ₁ ), (C ₁₂ , C ₂₂ , C ₃₂ ,
…, Cn ₂ ), … (C _1j , C _2j , C _3j , …, C _oj ),
(C _1j+1 , C _2j+1 , C _3j+1 ,…, C _oj+1 ),…(C _1o ,
C _2o , C _3o , . . . , C _on ). Similar signal readout line parasitic capacitor C _SL or C _SL +
There are improved versions that apply the operating principle of C _SL ' charging and discharging to perform interlace scanning for each readout signal line, but the essential part is
In the figure, it is shown. Furthermore, there is a method for improving the operating waveforms shown in FIG. As an example, as explained in FIG. 3, in one horizontal retrace period that exists only a few μsec after one horizontal readout period, a pulse higher than the pulse height of φ _Gj , for example, 2.5 V or more, pulse width within several μsec. There is also a method of adding a function of adding a refresh pulse of 2 to each address gate pulse on the same signal line GLj. In the signal readout method according to the present invention, after the address gate pulse φ _Gj is applied,
Within a short period of time within the pulse width (several μsec or less) of sufficient φ _Gj , the optical information of each pixel is transferred to the capacitor C _SL ,
C _SL ', and there is no need to continue applying the gate pulse φ _Gj over almost one horizontal period as shown in FIG. Therefore, the operating waveform in the present invention is not the waveform shown in FIG. 3, but the horizontal retrace period after approximately one horizontal period by adding φ _Gj (height 2V, pulse width within several μsec) at the address gate. In this case, a refresh pulse higher than φ _Gj (2.5 V or more, within several μsec) is applied on the same line. However, the simplest method is to use an address gate pulse with a pulse height of 2.5 V or more and _a pulse width of several μsec as φ _Gj as shown in Figure 6. Since the carrier is refreshed, there is no need to add a refresh gate pulse to the horizontal retrace period. The spike noise associated with switching increases as the gate pulse height increases, so if switching spike noise becomes a problem, the height of the address gate pulse φ _Gj should be kept within 2V and This means that the function of adding a refresh pulse becomes effective. Therefore, the simplest operating waveform is shown in FIG. 6 here.

The operation shown in FIG. 6 will be explained. The configuration shown in Figure 5 differs from the principle diagram in Figure 4 in that the signal readout line
Switch transistor on SLi (i=1~n)
Q _T is added for the following reason. m SITs are connected to the same signal readout line SLi, but in the light detection state, the impedance between SLi and the ground point is such that each SIT is irradiated with light and carriers are accumulated at the gate. As a result, the height of the potential barrier existing in the channel between the source and drain of each SIT decreases, so it gradually decreases as the light is integrated. When the impedance between SLi and the ground point decreases, the potential precharged in C _SL + C _SL ′ will be discharged, but the amount of discharge is equivalent to the sum of optical information for one row. , it becomes impossible to specify which pixel the optical information belongs to. On the other hand, since optical information is accumulated in the gate of each SIT, almost no information is lost even if the SLi and potential change. The time from when the horizontal shift pulse φ _S1 is applied until when φ _So is applied is approximately equal to one horizontal period, which is about 60 μsec for a TV signal. Therefore, while maintaining the principle diagram shown in FIG. 4, the signal readout line SLi (i=1 to
n) is precharged, GLj is addressed, and φ
After the first pixel C _1j is read out by φ So until C _oj is read out by φ _So , the precharged voltage level is more likely to be discharged in the later signal read lines. In particular, the precharge potential of the SLn line needs to be kept constant for about 60 μsec until Cnj is read out by φ _so , and during that time, the influence of light reception by other pixels connected to the same SLn line is It must be suppressed as much as possible. However, it has been experimentally revealed that one horizontal line SLi
Furthermore, as the number of pixels arranged in a row increases, the impedance between SLi and ground decreases as the light is integrated, and even one horizontal period of about 60 μsec cannot be ignored. Therefore, a new switch transistor Q _T shown in Fig. 5 was inserted,
When precharging the signal readout line in advance, charge the parasitic capacitor C _SL + C _SL ′.
Immediately after charging, address gate pulse φ _Gj is applied, and the optical information of each pixel C _1j , C _2j , C _3j , ..., C _oj is read out from each signal readout line SL1, SL2, SL3, ...,
Accumulate the amount of discharge in the parasitic capacitor C _SL + C _SL ′ of SLn, then immediately turn off Q _T and store the information of each pixel only in the capacitor C _SL ′,
This is a method in which the information of each pixel is taken out to the output line by φ _S1 , φ _S2 , . . . , φ _So regardless of the amount of discharge of _CSL . FIG. 6 shows the operating waveforms of this method over two horizontal periods.

At time _t1 , _φT is applied to simultaneously conduct the switch transistors _QT on each signal readout line, and at time _t2 , φp is applied to simultaneously conduct the precharge transistors on each signal readout line. Then, the capacitors C _SL +C _SL ' of each signal readout line are charged to a predetermined precharge voltage level. Thereafter, at time _{t3 ,} pixels C _1j , C _2j , C _3j ,
..., each SIT of C _oj is made conductive at the same time, and the optical information accumulated in the gate of each SIT is transferred to the parasitic capacitor.
Each signal readout line is calculated as the discharge amount of C _SL + C _SL ′.
SL1, SL2, ..., SLn, then immediately turn off Q _T at time t ₄ , and change C _SL and C _SL ′
separation. Thereafter, at times t ₅ , t ₆ , t ₇ , ..., horizontal shift pulses of φ _S1 , φ _S2 , φ _S3 , ..., φ _So are sequentially applied to the gates of the switch transistors Qs on each signal readout line, thereby changing the video voltage.
By recharging the discharge amount of each capacitor C _SL ′ from V _DD , the output voltage V _put across the load resistor R _L
can be obtained. Similarly, in the next horizontal period, the next pixel columns C _1j+1 , C _2j+1 , C _3j+1 ,...
C _oj+1 is read.

To state the actual time values used, TV
In the case of signals, the number of pixels is approximately 500×500, so one horizontal readout period is approximately 65 μsec. In the SIT area sensor of the present invention, the readout time constant of one pixel is easily realized as several tens of nanoseconds, and the pulse width of φ _T is the pulse width of φ p, and the pulse width of φ _G
5 μsec or less is sufficient as the sum of the pulse widths. Therefore, if this readout method is used, image information of about 500×500 elements can be easily read out using TV signals. In the case of this method, the time constant when read by the pulse of φs is the time constant for charging C _SL ′, as described above.
Since C _SL + C _SL ′ is not charged, it is easy to increase the speed, and a time constant of several tens of nanoseconds can be easily achieved. In order to further increase the speed, the parasitic capacitance and effective resistance of the video output line 51 are reduced.

Next, another embodiment of the present invention is shown in FIG. The major difference between FIG. 7 and the embodiment shown in FIG.
In the figure, signals of point pixels are read out from one load R _L and video voltage V _DD on the video line 51, whereas in the embodiment of FIG. 7, each signal readout line SL1, SL2, ..., SLn Switch transistors Q _T and Qs are connected in series above, and the drain of Qs is connected to each storage region 701, 702, 702 of the CCD 70,
703, . . . 70n.
The CCD70 is operated by two-phase clocks φ _H1 and φ _H2 ,
The pixel information (C _1j , C _2j , C _3j , ..., C _oj information) accumulated in a part of the parasitic capacitance C _SL ' of each signal readout line is transferred to the potential well forming each storage region by each switch transistor. The information in the potential wells of the CCDs is simultaneously transferred in parallel by the transfer pulse φ _GO applied to the common gate line 74 of the Qs, and the information in the CCD potential wells transferred simultaneously within one horizontal period is sequentially transferred to the two-layer clock φ _H1 and φ _H2. In the next horizontal period, the next pixel column (C _1j+1 , C _2j+1 ,...,
The information of C _oj+1 ) is sequentially transferred to the output buffer 71 and read out. In this way, all pixels are read out. After making the switch transistor Q _T conductive in advance by the transfer pulse φ _T ,
By making the precharge transistor conductive by the precharge pulse φp, the capacitance C _SL + of each signal readout line SL1, SL2, SL3, ..., SLn
After charging C _SL ′ to a predetermined potential level, address gate pulse φ _Gj is immediately applied to address gate line GL, and pixels C _1j , C _2j , ..., C _oj store optical information from C _SL + C _SL ′. After accumulating the amount of discharge on each signal readout line SL1, SL2, SL3, ..., SLn, immediately turn off the transfer pulse φ _T and apply the gate pulse φ _GO to the gate line 74 of the switch transistor Qs. The information of pixels C _1j , C _2j , C _3j , ..., C _oj stored in C _{SL ′} is simultaneously stored in each storage section 701, 7 of CCD 70 in parallel.
02, 703, . . . 70n. If the speed of the clocks φ _H1 and φ _H2 of the CCD 70 increases, faster reading will be performed. As a modification of the embodiment shown in FIG. 7, instead of inputting pixel information for one row in parallel to the CCD at the same time, it is possible to divide the information into blocks of several pixels and input them to separate CCDs. be. In this case, higher-speed image detection is performed, but the peripheral portion of the SIT area sensor structure becomes complex.

In the embodiments of the present invention, the optical input has been explained as continuous light, but it goes without saying that image detection for light input over a certain period of time is also possible according to the present invention.
It is clear that this can be done using a dimensional solid-state imaging device.

The electrostatic induction transistor used as a component of the pixel of the present invention is preferably of a vertical structure formed using a semiconductor material. Naturally, infrared light image detection is also possible using not only Si materials but also other materials such as Ge, InSb, and HgCdTe. SIT gate structures include conventional p-n junction single gate, split gate, and partial p-n junction.
An MIS gate structure may also be used. Furthermore, the gate portion may be made of a semiconductor having a wider forbidden band width than the channel region. For example, the channel region is made of GaAs and the gate region is made of lattice-matched GaAlAsP.

FIGS. 8 and 9 show characteristics when a signal of specific pixel information is read out using a two-dimensional solid-state imaging device configured according to the present invention. The pixel structure consists of a static induction transistor formed vertically in Si and a transparent SnO ₂ electrode on the SIT gate p ⁺ diffusion region.
It is formed from a structure with an added MIS gate capacitor made of Si ₃ N ₄ film/P ⁺ Si, and the dimensions are approx.
The size is approximately 50μ×50μ, and the source length is 100μm.
The thickness of the Si ₃ N ₄ film is about 700 Å. Such pixels are separated from each other by insulators and pn junctions. Forming such pixels in a matrix,
Figure 8 shows a plot of the peak value of the output voltage Vont for one pixel among the pixels against the light intensity P (μW/cm ² ) using the ratio of Cp to the capacitor _CSL of the signal readout line as a parameter. . In this experiment, C _SL =C _SL ′=50pF,
V _DD ′−Vthp−Vtht=1V. The optical integration time is 11.2 msec. In Figure 8, the pulse width of φ _T is
The pulse width of φs is 5 μsec and 350 nsec.
As the ratio of C _T /C _SL ' increases, the output voltage tends to approach the saturation level of 1V. In the operating conditions shown in FIG. 8, C _G <C _T C _SL ′=C _SL .
FIG. 9 shows the output voltage Vout and light intensity P when one pixel is read out in a two-dimensional solid-state imaging device according to the present invention similarly formed in a matrix shape.
(μW/cm ² ) is shown using the value of C _SL ′ as a parameter. The light irradiation time is also 11.2m.
sec, and V _DD ′−Vthp−Vths=1V.
The operating conditions shown in FIG. 9 are C _G <C _SL 'C _T C _SL , and the best condition is C _SL '=50 pF.

FIGS. 8 and 9 are examples of results obtained using the readout method using the two-dimensional solid-state imaging device of the present invention. It can be seen that good characteristics can be obtained by satisfying the conditions of equations (5) and (6) above.

The two-dimensional solid-state imaging device according to the present invention has completely dynamic operation that utilizes charging and discharging of capacitors, so it consumes less power than conventional configurations and readout methods, and because it performs pre-charging, it is stable and uniform. In addition, since the voltage level is kept low, spike noise associated with switching is also reduced, and the capacitance related to readout can be reduced, allowing high-speed readout. This solid-state imaging device has unique characteristics and is of high industrial value.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the configuration of a conventional SIT area sensor, Fig. 2 is a diagram illustrating an example of operating waveforms by the conventional readout method in the configuration of Fig. 1, and Fig. 3 is a diagram showing another example of operating waveforms. , FIG. 4 is a diagram explaining the principle of the readout method according to the present invention, FIG. 4a is an operating circuit, FIG. 4b is a diagram showing readout operation waveforms, and FIG. 5 is a configuration example of the SIT area sensor according to the present invention. , FIG. 6 is a diagram showing a part of the readout operation waveform, FIG. 7 is another embodiment of the present invention, and is an example of a configuration in which an output signal is extracted using a CCD, and FIG. 8 is a diagram showing a part of the readout operation waveform. In the two-dimensional solid-state imaging device according to the present invention, the relationship between the output signal read out by the readout method of the present invention and the light intensity P is
The ratio of C _T /C _SL ' is shown as a parameter, and FIG. 9 similarly shows the value of C _SL ' as a parameter. 50...Horizontal shift register, 51...Output video line, 52, 73...Vertical shift register, 53, 75...Gate line for applying transfer pulse _φT , 54, 76...For applying precharge pulse φp Gate line, 55...Precharge power supply line, 70...CCD shift register,
701, 702, 703,..., 70n...CCD
Each signal storage section of the shift register, 72...CCD
Output buffer, 74...Transfer pulse φ _GO
Gate line for application.

Claims (1)

[Claims] 1. A pixel Cij ( _i =
1 to n, j=1 to m) constitute an X-Y matrix, and the vertical gate address lines GL ₁ ,
GL ₂ , GL ₃ , ..., GL _n are connected to the gates of SITs forming each pixel C _1j , C _2j , C _3j , ..., _Coj on each GL _j (j=1 to m) via gate capacitors _CG . connected,
The signal readout lines SL ₁ , SL ₂ , SL ₃ , ..., SL _o correspond to each pixel C _i1 , C _i2 , C _i3 , on each SL _i (i=1 to n).
..., a gate accumulation type SIT area sensor commonly connected to the drains of SITs constituting C _in , each of the signal readout lines SLi (i=1 to
n) each has a predetermined capacitor _CSL between the ground potential and a precharge transistor.
Q _p is commonly connected to a predetermined power supply voltage V _DD
Q _T , each of the first switching transistors Q _T is commonly connected to a video output line via a respective second switching transistor Q _S , and the video output line has one A load resistor R _L and one video power supply V _DD are connected, and the gates of each of the first switching transistors Q _T are all connected in common so that a transfer pulse φ _T is applied, each of the first switching transistors;
Q _T and each second switching transistor Q _S
A predetermined capacitor C _T is provided between the connection node and the gate of each first switching transistor Q _T , and a capacitor C _SL ' is provided between the connection node and the ground potential. The size relationship of each capacitor is set as C _G <C _SL 'C _T C _SL , and each of the vertical gate address lines GL ₁ ,
Vertical shift pulses φ _G1 , φ _G2 , _{φ G3} , …, φ _{Gn are} applied from the vertical shift register to GL 2 , GL ₃ , ..., GL n, and the respective second switching transistors
A two-dimensional solid-state imaging device configured to perform X-Y addressing by applying horizontal shift pulses φ _S1 , φ _S2 , φ _S3 , . . . , φ _Sn from a horizontal shift register to the gate of Q _S. 2 Pixel Cij ( _i =
1 to n, j=1 to m) constitute an X-Y matrix, and the vertical gate address lines GL ₁ ,
GL ₂ , GL ₃ , ..., GL _n are connected to the gates of SITs forming each pixel C _1j , C _2j , C _3j , ..., _Coj on each GL _j (j=1 to m) via gate capacitors _CG . connected,
The signal readout lines SL ₁ , SL ₂ , SL ₃ , ..., SL _o correspond to each pixel C _i1 , C _i2 , C _i3 , on each SL _i (i=1 to n).
..., a gate accumulation type SIT area sensor commonly connected to the drains of SITs constituting C _in , each of the signal readout lines SL _i (i=1 to
n) each has a predetermined capacitor _CSL between the ground potential and a precharge transistor.
Q _p is commonly connected to a predetermined power supply voltage V _DD
Q _T , each of the first switching transistors Q _T is commonly connected to a video output line via a respective second switching transistor Q _S , and the video output line has one A load resistor R _L and one video power supply V _DD are connected, and the gates of each of the first switching transistors Q _T are all connected in common so that a transfer pulse φ _T is applied, each of the first switching transistors;
Q _T and each second switching transistor Q _S
A predetermined capacitor C _T is provided between the connection node and the gate of each first switching transistor Q _T , and a capacitor C _SL ' is provided between the connection node and the ground potential. The size relationship of each capacitor is set as C _G <C _SL 'C _T C _SL , and each of the vertical gate address lines GL ₁ ,
Vertical shift pulses φ _G1 , φ _G2 , _{φ G3} , …, φ _{Gn are} applied from the vertical shift register to GL 2 , GL ₃ , ..., GL n, and the respective second switching transistors
In a two-dimensional solid-state imaging device configured such that X-Y addressing is performed by applying horizontal shift pulses φ _S1 , φ _S2 , φ _S3 , ..., φ _Sn from a horizontal shift register to the gate of Q _S. , when reading the signal, turn on Q _T by transfer pulse φ _T in advance.
Then, with C _{SL ′} electrically connected in parallel to C SL, Q _p is turned on in advance by a precharge pulse φ _p , and each signal readout line SL ₁ ,
After charging all capacitors C _SL +C _SL ′ of SL ₂ , SL ₃ , ..., SL _o to a predetermined voltage level, the gates of pixels C _1j , C _2j , C _3j , ..., C _oj arranged on GL _j are charged. By simultaneously applying an address gate pulse φ _Gj through the gate capacitor C _G to the
When the SITs are made conductive, the discharge ΔV _SL corresponding to the amplified signal of the optical information stored at the gate of each SIT is
A constant voltage level V _SL of C _SL + C _{SL ′} is performed, and after this, φ _T is turned off and Q _T is turned OFF, and horizontal shift pulses φ _S1 , φ _S2 , φ _S3 , ..., φ _So are sequentially turned on each switch. By applying it to the gate of transistor _QS ,
By recharging the discharge amount of the capacitor C _SL ' from the video voltage V _DD via the load resistor R _L , the information of each pixel C _1j , C _2j , C _3j , ..., C _oj is displayed at the output terminal. The above operations complete one horizontal readout operation, and then in the same manner, each pixel C _1j+1 , C _2j+1 , C _3j+1 , . . . on the vertical address gate line GL _j+ 1 is obtained. ,
A signal detection method for a two-dimensional solid-state imaging device in which image signals of C _oj+1 are sequentially read out in the next horizontal period, and all pixels are sequentially read out in this way. 3 During the horizontal retrace period, the refresh gate pulse φ _GR higher than the height of the address gate pulse φ _Gj (j=1 to m) is applied to the address gate line GL ₁ ,
GL ₂ ,..., address gate pulse φ _G1 on GL _n ,
A signal detection method for a two-dimensional solid-state imaging device according to claim 2, characterized in that the signal is added to φ _G2 , φ _G3 , ..., φ _Gn . 4 Pixel C _ij ( _i =
1 to n, j=1 to m) constitute an X-Y matrix, and the vertical gate address lines GL ₁ ,
GL ₂ , GL ₃ , ..., GL _n are connected to the gates of SITs constituting each pixel C _1j , C _2j , C _3j , ..., _Coj on each GL _j (j=1 to m) via gate capacitors _CG . connected,
The signal readout lines SL ₁ , SL ₂ , SL ₃ , ..., SL _o correspond to each pixel C _i1 , C _i2 , C _i3 , on each SL _i (i=1 to n).
..., a gate accumulation type SIT area sensor commonly connected to the drains of SITs constituting C _in , each of the signal readout lines SL _i (i=1 to
n) has a predetermined capacitor _CSL between it and the ground potential, and has a precharge transistor.
Q _p is commonly connected to a predetermined power supply voltage V _DD
QT , and each of the first switching transistors _QT is connected to a CCD for horizontal signal transfer via a second switching transistor _QS .
The gates of each of the first switching transistors Q _T are all connected in common so that a transfer pulse φ _T is applied to each of the first switching transistors Q T . A predetermined capacitor C _T is provided between the connection node between Q _T and each of the second switching transistors Q _S and the gate of each of the first switching transistors Q _T ; A capacitor C _SL ′ is provided between the ground potential and the size relationship of each capacitor is C _G <C _SL ′C _T
C _SL , and the gates of the second switching transistors Q _S are all connected in common so that a transfer pulse φ _GO is simultaneously applied to each vertical gate address line GL. ₁ , GL ₂ , GL ₃ ,..., GL _n receive vertical shift pulses φ _G1 , φ _G2 ,
Every time φ _G3 , ..., φ _Gn is applied, the pixel column C _1j ,
The image information of C _2j , C _3j , ..., C _oj is input in parallel to the CCD by opening and closing switch transistors Q _T and Q _S , and the transfer of one pixel column is completed within one horizontal period, and the image information is sequentially ( C _1j+1 , C _2j+1 , C _3j+1 ,...
C _oj+1 ), (C _1j+2 , C _2j+2 , C _3j+2 ,..., C _oj+2 ),...
(C _1n , C _2n , C _3n , ..., C _on ) and by transferring the above pixel column within the CCD every horizontal period.
A signal detection method for a two-dimensional solid-state imaging device that sequentially obtains pixel information at the CCD output terminal.