JPH0415545B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a time axis error correction circuit for correcting a time axis error in a reproduced signal that occurs when an audio signal is recorded and reproduced by a rotating head type magnetic recording and reproducing device.

FM (frequency modulation) audio analog signal
Methods have been proposed for recording and playing back by converting amplitude information into FM signals and PCM signals using the PCM (Pulse Code Modulation) method, etc., but recording and playback of these converted signals requires high-density and wideband recording. A helical scan type rotating head type magnetic recording/reproducing device is suitable.

However, in such a device, the playback signal includes time axis errors caused by uneven rotation of the rotary head, expansion/contraction of the magnetic tape, etc., so the playback signal from the preceding playback head and the playback signal from the subsequent playback head are particularly different. There is a drawback that signal discontinuity occurs at the joint portion. When recording and reproducing video signals, discontinuities in the signal can be made less noticeable by positioning this joint at the bottom edge of the screen, but such processing is not possible when recording and reproducing audio signals.

Therefore, a circuit has been proposed that uses a stable time reference signal from an oscillator to control the delay of the reproduced signal and corrects the time axis error of the reproduced signal.

In addition, in such delay control, for example, a pilot signal as a time reference signal and an FM signal are recorded together, and during recording, an overlapping portion of the recorded signal is provided between the preceding track and the following track, and this overlap is recorded during playback. Although the signals that follow in time are controlled, especially when dropout occurs during this period, the control is not applied, so the above-mentioned signal discontinuity becomes noticeable.

The present invention provides a time base error correction circuit that also includes such dropout countermeasures, and will be described below with reference to embodiments thereof.

Figure 1 shows the block diagram of the recording circuit.
The converter 1 converts the original audio signal Sa input to the input terminal _t1 into an FM signal Sf. In this case, a relatively low center frequency is selected to improve conversion accuracy, and the beat up circuits 2a, 2b after conversion are
The beat is increased to a center frequency of several MHz. Note that it is better to use different center frequencies for each beat up in terms of crosstalk. Combining circuits 3a and 3b each combine the beat-up FM signal and a pilot signal Sp from a fixed oscillator 4 such as a crystal oscillator. The frequency of the pilot signal Sp is formed by dividing the oscillation frequency of the fixed oscillator 4 so as to be set below the beat-up FM signal band. 5
Reference numerals a and 5b represent recording amplifiers, 6 a head selector switch, and 7a and 7b rotary heads arranged on a rotary cylinder (not shown) with a rotation angle of 180 degrees from each other. As is well known, the combined signal is alternately applied to the rotating heads 7a and 7 in response to switching of the head changeover switch 6.
b is recorded on an inclined track on a magnetic tape (not shown). Note that the rotation speed of the rotary cylinder is controlled using a reference signal from the fixed oscillator 4 in a well-known manner.

The recording signal recorded in this manner is reproduced by the reproduction system circuit shown in FIG. Rotating head 7a,
The reproduction signals alternately reproduced by 7b are amplified by reproduction amplifiers 8a and 8b, respectively, and then separated into a reproduction FM signal and a reproduction pilot signal by FM signal band filters 9a and 9b and pilot signal band filters 10a and 10b. Rotating head 7a,
The reproduced FM signals S'fa and S'fb alternately reproduced in time series from 7b are beaded down by beatdown circuits 11a and 11b, respectively, by beat-up portions during recording, and are then beaded down by beatdown circuits 11a and 11b.
After being made into one continuous reproduction signal by the multiplex circuit 13, it is demodulated by the demodulator 14, whereby the original audio analog signal is taken out from the output terminal _t2 . On the other hand, the reproduced pilot signals S'pa and S'pb from the rotary heads 7a and 7b, which are subject to exactly the same time axis fluctuations as the reproduced FM signal due to uneven rotation, etc., pass through variable delay circuits 15a and 15b, respectively. After that, it passes through gate circuits 16a and 16b to phase comparator 17a,
17b. A stable time reference signal Sr, which is the same as the pilot signal Sp, is supplied from the fixed oscillator 4 to the gate circuits 16a, 16b and the phase comparators 17a, 17b from input terminals _t3a , _t3b , respectively. 16b outputs reproduction pilot signals S'pa and S'pb during the period when the rotary heads 7a and 7b are in contact with the magnetic tape (a time slightly longer than half a rotation of the rotary cylinder), respectively.
Also, during the period when the rotary heads 7a and 7b do not contact the magnetic tape and do not operate (a time slightly shorter than half a rotation of the rotary cylinder), the reproduction pilot signals S'pa,
Instead of S'pb, stable time reference signals Sr are sent to phase comparators 17a and 17b, respectively. Therefore,
The phase comparators 17a and 17b detect the phase error between the reproduction pilot signal and the stable time reference signal only during the active period of the corresponding rotary head, and send the phase error signal obtained by this detection to a necessary smoothing circuit (not shown). The output is always 0 during the inactive period of the corresponding rotary head.

The control circuits 18a and 18b control the variable delay for the reproduced pilot signals when the phases of the reproduced pilot signals S'pa and S'pb and the stable time reference signal Sr do not match and there is an output from the phase comparators 17a and 17b, respectively. The delay times of the circuits 15a and 15b are controlled so that the phases of both signals are completely matched, and the variable delay circuits 12a and 12b for the reproduced FM signal are also controlled to be equal to the delay time control of the reproduced pilot signal.
It is something to be applied to.

First, a specific example of a variable delay circuit will be explained. FIG. 3 shows one embodiment of the variable delay circuit, which constitutes a variable delay circuit for, for example, a reproduced FM signal and a reproduced pilot signal corresponding to one rotary head. . The output from the control circuit described above is input to a divider 19 via an input terminal t ₄ , and the current output of this divider 19 is supplied via a current amplifier 20 to a current mirror circuit 21 . 22 to 25 are monostable multivibrators, each of which is given the same control current I from the current mirror circuit 21. The reproduced FM signal inputted from the input terminal _t5 is delayed by the two-stage monostable multivibrator 22, 23, and the reproduced pilot signal inputted from the output terminal _t7 and input terminal _t6 is delayed by the two-stage monostable multivibrator 22 and 23. The signals are delayed by stable multivibrators 24 and 25 and output from output terminals _t8 , respectively. Metastable time (delay time) of monostable multivibrators 22-25
Tm is the time for the terminal voltage of the capacitors _C1 to _C4 to reach the specified threshold voltage Vt from 0, Tm=CVt/I (C is the capacitance of the capacitor)
However, if left as is, the delay time Tm will be non-linear (reciprocal relationship) with respect to the control current I. Therefore, the divider 19 is arranged to output a current output that is inversely proportional to the control input, thereby making it possible to give a delay time proportional to the control input to the reproduced FM signal and the reproduced pilot signal. However, in this variable delay circuit, the maximum delay amount is determined by the number of stages of monostable multivibrators provided in the signal line, and there is a problem in that each stage added causes deterioration of transmitted information due to time errors, variations, etc.

Figure 4 shows another embodiment of the variable delay circuit, in which the reproduced FM signal or the reproduced pilot signal input from the input terminal _t9 is frequency-divided and delayed in parallel, and then synthesized and output from the output terminal. t ₁₀ , and it is possible to increase the delay time without increasing the number of monostable multivibrator stages. 26 to 28 are JK flip-flop circuits which frequency-divide the delayed signal and divide it into four pulses. The divided signals are subjected to time delays by monostable multivibrators 29 to 32, respectively, and then synthesized by a synthesis circuit 33. The monostable multivibrators 29 to 32 receive an equal control current I from the current mirror circuit 21 in response to the control input from the input terminal _t4 , as in the previous example.
The divider, current amplifier, etc. are also shown with the same reference numerals as in the previous example.

Next, a fifth embodiment of the control circuits 18a and 18b will be described.
To explain using the block diagram of one of the control circuits 18a shown in the figure, the output of the phase comparator 17a is inputted from the input terminal _t11 after smoothing, passes through the buffer amplifier 34a, and then is input to one input terminal of the adder circuit 35a. and multiplier circuits 36a and 37.
The signals are input to each input terminal of a. Prediction signals W _1a and W _2a , which will be described later, are input to the other input terminals of the multiplier circuits 36a and 37a, respectively.
The product information of the phase error signal from W 1a and the predicted signals W _1a and W _2a is sent to the integrating circuits 38a and 39a. Integrating circuits 38a and 39a each integrate and accumulate input product information with a required time constant, and apply the integrated accumulated information, DC voltages D _1a and D _2a , to the subsequent multiplier circuit 40.
It is output to one input terminal of a, 41a. The multiplier circuit 3 is connected to the other input terminal of the multiplier circuits 40a and 41a.
Similarly to 6a and 37a, prediction signals W _1a and W _2a are respectively input, and multiplier circuits 40a and 41a respectively receive DC voltages D _1a and D _2a and prediction signals W _1a and W _2a.
and outputs the product information to the remaining two input terminals of the adder circuit 35a. The adder circuit 35a sends a control signal formed by combining each input signal to the input terminal _t4 of the variable delay circuit described above.

Now, to explain the prediction signals W _1a and W _2a ,
The phase error signal input to the control circuit 18a in response to time axis errors in the reproduced signal caused by various factors includes a predictable component in its waveform in relation to the active period of the rotating head. . for example,
When a magnetic tape recorded by one device is played back by another device, the component based on the positional error of the rotating head is generated as a square wave signal during the active period of the rotating head, and the component due to tape elongation is generated as a square wave signal by the rotating head. can be predicted as a slope signal having a constant slope during the active period of . So the predicted signal
W _1a and W _2a are signals having waveforms corresponding to predictable error components related to the active time of the corresponding rotary head 7a, and predicted signals W 1b and W _2a are similarly related to the active time of the rotary head 7b. W _2b is control circuit 1
8b. FIG. 6 shows a waveform diagram of such a prediction signal.

In the above configuration, the time axis error included in the reproduced signals from the rotary heads 7a and 7b is the reproduced pilot signal separated from the reproduced FM signals S'fa and S'fb.
Monitored by S′pa and S′pb. When a time axis error is detected, the reproduced pilot signal S′pa,
Delay control is also applied to the reproduced FM signals S′fa and S′fb so that S′pb is completely in phase with the stable time reference signal Sr, and the time axis error in the reproduced FM signal is removed, making it variable At the output points of the delay circuits 12a and 12b, the reproduced FM signal from the rotary head 7a is output.
The signal joint point between S'fa and the reproduced FM signal S'fb from the rotary head 7b is completely matched. The reproduced FM signals S′fa, S′fb with time axis errors removed in this way
is converted into one continuous signal by the multiplex circuit 13 in a constant relationship with the rotation of the rotary cylinder, and then demodulated by the demodulator 14 into an audio analog signal.

In addition, since predictive control is applied in advance to the predictable time axis error components related to the rotation of the rotary head, even if a dropout occurs, such components are corrected, so delay control due to dropout can be performed. In addition, it is not necessary to effectively perform high-speed response control on components caused by predictive control, and it is sufficient to simply perform correction control on components caused by tape vibration or the like.

In the above embodiments, recording and reproduction using FM signals have been described, but it is not necessary to record a pilot signal when the information signal itself has a time reference signal, such as a PCM signal.

Further, the components to be subjected to predictive control are not limited to those in the embodiments, but may be components whose error waveforms can be predicted in relation to the rotation of the rotary head. The multiplication circuits 36a and 40a can be configured in various ways, such as by using analog switches.

[Brief explanation of drawings]

1 and 2 are block diagrams of a recording system circuit and a playback system circuit according to the present invention, and FIGS.
5 shows a block diagram of an embodiment of the variable delay circuit, FIG. 5 shows a block diagram of an embodiment of the control circuit, and FIG. 6 shows a waveform diagram of a predicted signal. 4... Fixed oscillator, 7a, 7b... Rotating head, 12a, 12b, 15a, 15b... Variable delay circuit, 17a, 17b... Phase comparator, 18
a, 18b...control circuit, 36a, 37a, 40
a, 41a...Multiplication circuit, 38a, 39a...Integrator circuit, S'fa, S'fb...Regenerated FM signal, S'pa,
S'pb... Reproduction pilot signal, Sr... Stable time reference signal, W _1a , W _1b , W _2a , W _2b ... Prediction signal.

Claims (1)

[Claims] 1. Obtaining a required phase error signal by detecting the phase error between the reproduction time reference signal obtained together with the reproduction information signal in time series by sequentially switching the rotating head and the stable time reference signal from the oscillator. and control means for respectively delay-controlling the reproduction information signal and the reproduction time reference signal, the control means delaying the reproduction time reference signal and the stable time reference signal so that their phases match, and delaying the reproduction information signal and the stable time reference signal, respectively. In a time base error correction circuit that corrects a time base error of the reproduced information signal by giving the reproduced information signal a time delay equal to the time delay of the time reference signal by the control means, A control signal obtained by adding an error signal and a predictive control signal based on a time axis error component that occurs in connection with the rotation of the rotary head and whose phase error waveform is predictable is used to control the reproduction information signal and the reproduction information signal. A time axis error correction circuit characterized in that the reproduction time reference signal and the reproduction time reference signal are respectively delayed and controlled. 2. The prediction control signal is formed by multiplying integral accumulation information formed by integrating and accumulating a product information signal of the phase error signal and a predetermined prediction error waveform signal, by the prediction error waveform signal. The time base error correction circuit according to claim 1, characterized in that: 3. The time-base error correction circuit according to claim 2, wherein the expected error waveform signal comprises at least one of a square wave signal and a slope signal.