JPH0415628B2 - - Google Patents
Info
- Publication number
- JPH0415628B2 JPH0415628B2 JP59260367A JP26036784A JPH0415628B2 JP H0415628 B2 JPH0415628 B2 JP H0415628B2 JP 59260367 A JP59260367 A JP 59260367A JP 26036784 A JP26036784 A JP 26036784A JP H0415628 B2 JPH0415628 B2 JP H0415628B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- power supply
- high level
- circuits
- time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
- H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は保護回路を備えた半導体装置に関し、
特に電源ラインに過電圧保護回路を備え、複数の
内部回路を有する半導体装置に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device equipped with a protection circuit,
In particular, the present invention relates to a semiconductor device that includes an overvoltage protection circuit in a power supply line and has a plurality of internal circuits.
［従来の技術］
第４図は従来例に係る保護回路を備えた半導体
装置の要部回路図であり、保護抵抗R1とMOSト
ランジスタQ1により構成された保護回路が配線
ライン３上に設けられ、たとえば急峻な高電圧が
VDD端子に入力すると保護抵抗R1と配線ライン３
上に存在する容量CLによつて定まる時定数によ
り高電圧を平坦化し、回路１，２に高電圧が印加
されるのを防止している。また、MOSトランジ
スタQ1は電源電圧VDDが通常の動作電源電圧のと
きはオンしないが、通常の動作電源電圧より1.5
〜２倍となつた時にオンして高電圧が回路１，２
に印加されないようにしている。[Prior Art] FIG . 4 is a circuit diagram of a main part of a semiconductor device equipped with a protection circuit according to a conventional example. For example, when a steep high voltage
When input to V DD terminal, protection resistor R1 and wiring line 3
The high voltage is flattened by a time constant determined by the capacitance C L existing above, and high voltage is prevented from being applied to the circuits 1 and 2. Also, MOS transistor Q1 does not turn on when the power supply voltage V DD is the normal operating power supply voltage, but it is 1.5% lower than the normal operating power supply voltage.
~ When it doubles, it turns on and high voltage flows to circuits 1 and 2.
is applied so that it is not applied.
［発明が解決しようとする問題点］
しかしながら、上述した第４図に示す従来の保
護回路は以下に述べる問題点を有している。すな
わち、第４図に示す回路１，２が第５図に示すよ
うなCMOタイプのインバータ回路であり、第７
図に示すクロツクが入力端子IN1，IN2に入力さ
れるとすると、出力端子OUT1，OUT2の出力波
形はそれぞれ第７図に示すような波形になる。す
なわち、時刻t1，t3での出力端子OUT1のハイレ
ベルVH（t1）、VH（t3）は異なり、時刻t1，t2での出
力端子OUT2のハイレベルVH（t1）、VH（t2）も異
なつたものとなる。この理由を次に説明する。[Problems to be Solved by the Invention] However, the conventional protection circuit shown in FIG. 4 described above has the following problems. That is, circuits 1 and 2 shown in FIG. 4 are CMO type inverter circuits as shown in FIG.
If the clocks shown in the figure are input to the input terminals IN 1 and IN 2 , the output waveforms of the output terminals OUT 1 and OUT 2 will be as shown in FIG. 7, respectively. That is, the high level V H (t 1 ) and V H (t 3 ) of the output terminal OUT 1 at times t 1 and t 3 are different, and the high level V H of the output terminal OUT 2 at times t 1 and t 2 is different. (t 1 ) and V H (t 2 ) will also be different. The reason for this will be explained next.
いま、インバータ回路１，２の負荷抵抗をRL
とすると、時刻t3の時点での等価回路は第６図の
ようになる。ここでＰチヤンネル、Ｎチヤンネル
のMOSトランジスタは簡単化のためスイツチ
SW1，SW2，SW3，SW4で表わしている。図より
わかるように時刻t3でのハイレベルVH（t3）は保
護抵抗R1と負荷抵抗RLとにより分圧され、
VH（t3）＝RL／R1＋RL・VDD ……(1)
である。時刻t1ではインバータ回路１，２のＰチ
ヤンネルトランジスタ（スイツチSW2，SW4が両
方ともオンするため、出力のハイレベルVH（t1）
は
VH（t1）＝１／２RL／R1＋１／２RL・VDD ……(2)
となる。また、時刻t2ではインバータ回路２のＰ
チヤンネルトランジスタ（スイツチSW4がオンし
ているため、ハイレベルVH（t2）は時刻t3のとき
と同様に
VH（t2）＝RL／R1＋RL・VDD ……(3)
となつている。ここで、R1＝10Ω、RL＝1KΩ、
VDD＝10Vとして式(1)、(2)、(3)に代入すると、VH
（t2）＝VH（t3）＝9.90V、VH（t1）＝9.80Vとなり、両
者に約0.1Vの差が生じている。この電位差はデ
イジタル回路では問題ないが、この出力がアナロ
グ回路の、例えばサンプルホールド回路のゲート
クロツクとして用いられた場合、大きな問題とな
る。なぜなら、サンプルホールド回路においては
サンプリングゲートとアナログの信号ラインとの
カツプリング容量は必ず存在しており、従つてサ
ンプリングクロツクのノイズは信号ラインに混入
しているので、この状態でサンプリングクロツク
のハイレベルが時刻t1とt3とで異なれば、信号ラ
インに混入するクロツクノイズのレベルも時刻t1
とt3とで異なることになり、アナログ信号ライン
のＳ／Ｎ比を低下させることになる。 Now, the load resistance of inverter circuits 1 and 2 is R L
Then, the equivalent circuit at time t3 is as shown in FIG. Here, the P channel and N channel MOS transistors are switched for simplicity.
They are represented by SW 1 , SW 2 , SW 3 , and SW 4 . As can be seen from the figure, the high level V H (t 3 ) at time t 3 is divided by the protection resistor R 1 and the load resistor R L , and V H (t 3 )=R L /R 1 +R L・V DD ...(1). At time t 1 , the P channel transistors (switches SW 2 and SW 4 ) of inverter circuits 1 and 2 are both turned on, so the output high level V H (t 1 )
is V H (t 1 )=1/2R L /R 1 +1/2R L ·V DD ……(2). Also, at time t2, P of inverter circuit 2
Since the channel transistor (switch SW 4 ) is on, the high level V H (t 2 ) is the same as at time t 3 V H (t 2 ) = R L /R 1 + R L · V DD ...( 3) Here, R 1 = 10Ω, R L = 1KΩ,
By substituting V DD = 10V into equations (1), (2), and (3), V H
(t 2 )=V H (t 3 )=9.90V, V H (t 1 )=9.80V, and there is a difference of about 0.1V between the two. Although this potential difference is not a problem in a digital circuit, it becomes a big problem when this output is used as a gate clock of an analog circuit, for example, a sample-and-hold circuit. This is because in a sample-and-hold circuit, there is always a coupling capacitance between the sampling gate and the analog signal line, and therefore sampling clock noise is mixed into the signal line. If the level is different at time t 1 and t 3 , the level of clock noise mixed into the signal line is also different at time t 1.
and t3 , which lowers the S/N ratio of the analog signal line.
本発明は、クロツク出力のハイレベルがタイミ
ングにより変化を起こすことのない保護回路の提
供を目的とする。 SUMMARY OF THE INVENTION An object of the present invention is to provide a protection circuit in which the high level of a clock output does not change due to timing.
［問題点を解決するための手段］
本発明は電源ラインの入力保護抵抗を、電流を
供給するそれぞれの回路の直前に入れることを特
徴とする。[Means for Solving the Problems] The present invention is characterized in that an input protection resistor for the power supply line is inserted immediately before each circuit that supplies current.
［実施例］
以下、図面を参照して本発明の実施例を説明す
る。[Example] Hereinafter, an example of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例に係る保護回路を備
えた半導体装置の要部の回路図である。本実施例
は第４図の従来例において保護抵抗R1と容量CL
を排し電源ラインの入力保護抵抗R2，R3をそれ
ぞれインバータ回路１，２と電源ライン３間に接
続したものである。 FIG. 1 is a circuit diagram of a main part of a semiconductor device equipped with a protection circuit according to an embodiment of the present invention. This embodiment differs from the conventional example shown in Fig. 4 in that the protective resistance R 1 and capacitance C L
In this case, power line input protection resistors R 2 and R 3 are connected between the inverter circuits 1 and 2 and the power line 3, respectively.
これにより第２図に示すタイミングチヤートか
らわかるように、時刻t4でもt5でも出力端子
OUT2のハイレベルVH（t4）、VH（t5）は同じであ
り、時刻t4でもt6でも出力端子OUT1のハイレベ
ルVH（t4）、VH（t6）は同じとなる。その理由を第
３図を用いて説明する。 As a result, as can be seen from the timing chart shown in Figure 2, the output terminal is activated at both times t4 and t5 .
The high level V H (t 4 ) and V H (t 5 ) of OUT 2 are the same, and the high level V H (t 4 ) and V H (t 6 ) of output terminal OUT 1 are the same at time t 4 and t 6 . are the same. The reason for this will be explained using FIG.
第３図は時刻t6での第１図の回路動作を示す第
６図と同様の等価回路図である。時刻t6での出力
端子OUT1のハイレベルVH（t6）は、
VH（t6）＝RL／RL＋R2・VDD
となる。一方、時刻t4での第３図のスイツチSW3
がオンしスイツチSW4がオフしてもこの出力端子
OUT1のハイレベルは変化せず、電源VDDの電位
を抵抗R2とRLとで分圧した値RL／RL＋R2・VDDとな
る。このことは時刻t4，t5での出力端子OUT2の
ハイレベルでも同様であり、出力端子OUT2のハ
イレベルは
VH（t4）＝VH（t5）＝RL／RL＋R3・VDD
となる。 FIG. 3 is an equivalent circuit diagram similar to FIG. 6 showing the circuit operation of FIG. 1 at time t6 . The high level V H (t 6 ) of the output terminal OUT 1 at time t 6 is V H (t 6 )=R L /R L +R 2 ·V DD . On the other hand, switch SW 3 in Fig. 3 at time t 4
is on and switch SW 4 is off, this output terminal
The high level of OUT 1 does not change, and becomes the value R L / RL + R 2 ·V DD obtained by dividing the potential of the power supply V DD by the resistor R 2 and R L. This also applies to the high level of the output terminal OUT 2 at times t 4 and t 5 , and the high level of the output terminal OUT 2 is V H (t 4 ) = V H (t 5 ) = R L /R L +R 3・V DD .
［発明の効果］
以上説明したように、本発明は電源ラインより
別々の抵抗を通して各回路に電圧を印加すること
により、各回路は他の回路の動作状態による電圧
低下の影響をうけることがないため、他の回路の
動作状態によらず、いつも一定した出力電圧を出
力させることが可能にするとともに、保護回路と
しても充分な機能を発揮することが可能となる。[Effects of the Invention] As explained above, in the present invention, by applying voltage to each circuit from the power supply line through separate resistors, each circuit is not affected by voltage drop due to the operating status of other circuits. Therefore, it is possible to always output a constant output voltage regardless of the operating state of other circuits, and it is also possible to perform a sufficient function as a protection circuit.
第１図は本発明による保護回路の一実施例を備
えた半導体装置の要部回路図、第２図は第１図の
インバータ回路１，２の入出力のタイミングチヤ
ート、第３図は第１図の回路の等価回路図、第４
図は従来例の保護回路を備えた半導体装置の要部
回路図、第５図は第４図のインバータ回路１，２
の回路図、第６図は第４図の等価回路図、第７図
は第４図のインバータ回路１，２の入出力のタイ
ミングチヤートである。
１，２……インバータ回路、３……電源ライ
ン、４……MOSトランジスタ、R2，R3……保護
抵抗。
FIG. 1 is a circuit diagram of a main part of a semiconductor device equipped with an embodiment of a protection circuit according to the present invention, FIG. 2 is a timing chart of input/output of inverter circuits 1 and 2 of FIG. 1, and FIG. Equivalent circuit diagram of the circuit shown in Figure 4
The figure is a main part circuit diagram of a semiconductor device equipped with a conventional protection circuit, and Figure 5 is an inverter circuit 1 and 2 of Figure 4.
6 is an equivalent circuit diagram of FIG. 4, and FIG. 7 is an input/output timing chart of the inverter circuits 1 and 2 of FIG. 4. 1, 2...Inverter circuit, 3...Power line, 4...MOS transistor, R2 , R3 ...Protection resistor.
Claims (1)
素子と、該保護用素子に接続された電源ライン
と、該電源ラインからそれぞれ別個の抵抗を介し
て電力の供給を受け、それぞれ外部に出力を取り
出す複数の回路とを有し、前記保護用素子と前記
各抵抗とは過電圧保護回路を形成することを特徴
とする保護回路を備えた半導体装置。1 A power supply terminal, a protection element connected to the power supply terminal, a power supply line connected to the protection element, each receiving power from the power supply line through separate resistors, and outputting each to the outside. 1. A semiconductor device comprising a protection circuit, comprising a plurality of circuits for taking out the voltage, wherein the protection element and each of the resistors form an overvoltage protection circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59260367A JPS61137359A (en) | 1984-12-10 | 1984-12-10 | Protective circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59260367A JPS61137359A (en) | 1984-12-10 | 1984-12-10 | Protective circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61137359A JPS61137359A (en) | 1986-06-25 |
| JPH0415628B2 true JPH0415628B2 (en) | 1992-03-18 |
Family
ID=17346944
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59260367A Granted JPS61137359A (en) | 1984-12-10 | 1984-12-10 | Protective circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61137359A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR930005184A (en) * | 1991-08-21 | 1993-03-23 | 김광호 | Semiconductor device for preventing electrostatic voltage |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5868043U (en) * | 1981-11-02 | 1983-05-09 | 日産自動車株式会社 | Input protection device for semiconductor devices |
-
1984
- 1984-12-10 JP JP59260367A patent/JPS61137359A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61137359A (en) | 1986-06-25 |
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