JPH0416025B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention mainly relates to dynamic,
In some cases, static random access memory
The present invention relates to a semiconductor memory device having a high-density memory such as RAM (RAM) and a sense amplifier suitable for combination with the memory.

Prior Art and Problems Conventionally, various research and development efforts have been made to improve the degree of integration of dynamic RAM.

For example, as a memory cell, static
Capacitor Cell (M.Koyanagi et.al.Proc.10th
Conf.Solid−State Devices, Tokyo 1978,
Supplement 18-1, JJAP, 18, PP35-42,
1979), etc.) The increase in storage capacity due to multilayer memory capacitors and the adoption of self-aligning contacts have made it possible to fabricate extremely small memory cells, with storage capacities of 50
[fF], the memory cell area is approximately 20 to 30 [μm ² ]
It is believed that a memory cell with a minimum line width of 1.5 to 2 μm can be realized in a design.

However, the highly sensitive sense amplifier that is essential for dynamic RAM requires a column dimension corresponding to the memory cell area, e.g.
In wrapped bit line format, the column pitch is 8.
However, it is impossible to lay out a design based on the minimum line width of 1.5 to 2 [μm] used to realize memory cells within this range.

The reason for this is that memory cells are formed at the intersections of word lines and bit lines, and bit line contacts can be shared between adjacent memory cells, making it difficult to waste area in wiring. In contrast, sense amplifiers require wiring connections between the drain and gate, and if the pattern is designed using the same design criteria, the sense amplifier This becomes an element for selecting the minimum column pitch.

Of course, there are circuit elements such as active restore circuits that require more area than the sense amplifier, but peripheral circuits can be
If the active restore circuit is made into a latch circuit composed of transistors of opposite polarity to the sense latch circuit by using metal oxide semiconductor, its dimensions will be the same as the sense latch circuit. That is, the column dimensions and, as a result, the memory chip dimensions are determined depending on how small these basic latch circuits can be made.

FIG. 1 is a plan view of a main part of a conventional sense amplifier having a folded bit line structure.

In the figure, F is the field region, FB is the field region boundary, IS is the isolation region between adjacent sense amplifiers, S _c is the common source region, D1 and D2 are the drain regions, BL is the aluminum bit line, G1 and G2 indicates a polycrystalline silicon gate electrode, and SCL indicates a common source pull-down circuit. Note that the pattern with an x inside a square indicates a contact portion.

In this sense amplifier layout, the bit lines
Since the gate electrodes G1 and G2 are arranged in the directions BL and BL and the respective sense nodes of the latch circuit are led out in different directions, there are the following drawbacks.

(1) The active region surrounded by the field region boundary FB and the patterns of gate electrodes G1 and G2 are mutually positioned by mask alignment.
If a deviation occurs between the two, for example, the bit line
The widths of the drain region D1 connected to BL and the drain region D2 connected to the bit line BL are different, and the parasitic capacitance, resistance, etc. of the sense node become unbalanced, causing one side of the sense amplifier to become unbalanced. produce effects.

(2) Since one sense amplifier and the sense amplifier next to it are separated by a field region F, as shown by the isolation region IS, such isolation region IS is subjected to selective oxidation (local oxidation of
silicon: LOCOS) method, Birds
Due to the lateral oxidation phenomenon known as bird's beak, the minimum width of the isolation region IS due to the field region F is limited to 2.5 to 3 [μm]. become an obstacle.

There are various possible layouts for the sense amplifier other than those described above. For example, it is not desirable for the sense node to become unbalanced as explained in (1) above, so the layout should be devised to improve the activation. When a mask misalignment occurs between the region and the gate electrode, the sense
Measures have been taken to ensure that the fluctuations are in the same direction between nodes, but such consideration inevitably increases the size of the sense amplifier.

OBJECTS OF THE INVENTION The present invention provides an electrical connection between the sense amplifiers so that even if there is a slight misalignment between the active region and the gate electrode pattern in the sense amplifier, the above-mentioned one-sided effect occurs. To reduce the area required for separation.

Structure of the Invention In the semiconductor memory device of the present invention, a plurality of sense amplifiers are formed by cross-connecting the drains and sources of two transistors, and connecting the sources in common, and adjacent ones of the plurality of sense amplifiers are connected together. a field effect transistor formed in the active region and having a gate electrode connected to a common source region of the sense amplifiers for electrically isolating the adjacent sense amplifiers. Since the structure is adopted, the drain regions of the two transistors in each sense amplifier are connected to the respective gate electrodes and the gate electrode of the field effect transistor for electrically isolating each sense amplifier. Since it is defined,
In each sense amplifier, even if the gate electrode pattern with respect to the active region is slightly shifted, there is no possibility that the drain region of one of the two transistors will be larger or smaller than the drain region of the other. Also, since electrical isolation of each sense amplifier is not done in the field area,
There is no need to consider bird's beak, etc., and it is suitable for miniaturization.

Embodiment of the invention FIG. 2 is a plan view of essential parts of an embodiment of the invention,
The same parts as those described in connection with FIG. 1 are indicated by the same symbols.

In the figure, Q1 to Q5 indicate transistors, respectively. Note that each transistor is represented by indicating its respective gate electrode. In addition, in this embodiment, as the transistor Q5 for electrically isolating the sense amplifier,
Although an MIS field effect transistor is assumed, a short gate field effect transistor may be used instead.

FIG. 3 is a circuit diagram of the main part of the embodiment shown in FIG. 2, and the same parts as those described with reference to FIGS. 1 and 2 are indicated by the same symbols.

In the figure, Q6 represents a transistor in the common source pull-down circuit SCL, and φ _SA represents a signal applied to transistor Q6.

As is clear from the figure, two sense amplifiers are shown here.

Two sense amplifiers composed of transistors Q1 to Q4 are formed in a common active region,
They are electrically isolated by transistor Q5 formed in the same active region. Note that the gate electrode of transistor Q5 is connected to the common source region S _c of the sense amplifier.

The bit line BL and a metal silicide such as polycrystalline silicon or molybdenum silicide are used and are formed in a separate layer from the gate electrode of the sense amplifier.

The common source pull down circuit SCL is formed using aluminum.

The memory cell combined in this embodiment may be of any type; for example, if it is a static capacitor cell, the first layer of polycrystalline silicon is used to form a word line, that is, a transfer line.
In addition to forming the gate, the gate electrode of the sense amplifier, in the figure, the gate electrode of the transistors Q1 to Q4 and the gate electrode of the transistor separating the sense amplifiers, in the figure, the gate electrode of the transistor Q5 is formed. The second layer of polycrystalline silicon forms a field effect storage electrode. The third layer of polycrystalline silicon forms the counter electrode plate (cell plate) of the storage capacitor. Bit lines are formed in the fourth layer of polycrystalline silicon (or molybdenum silicide, etc.). In order to reduce the resistance value of the word line and speed up access time, the aluminum wiring on top of it is laid parallel to the word line and contacted with the transfer gate for every multiple cells (for example, 128 cells). Operates as word line bypass.

Further, for example, in the case of a double polysilicon memory cell, the counter electrode plate (cell plate) of the storage capacitor is formed of the first layer polycrystalline silicon. The second layer of polycrystalline silicon (or molybdenum silicide, etc.) forms the word line, that is, the transfer gate, and also serves as the gate electrode of the sense amplifier, transistors Q1 to Q4 in the figure.
The gate electrode of the transistor isolating between the gate electrode of Q and the sense amplifier, in the figure, the gate electrode of the transistor Q
Gate electrode No. 5 is formed. The third layer of polycrystalline silicon (or molybdenum silicide, etc.) forms bit lines. The aluminum wiring thereon is operated as a bypass to reduce the resistance value of the word line, as described above.

A specific numerical example is shown based on the embodiment shown in FIG. 2. Q1 to Q5
If the distance between the gate electrodes is 2 [μm] and self-alignment contacts are made between the bit line and the sense amplifier and between the common source pull-down circuit and the common source region of the sense amplifier, the column pitch of the folded bit line is It becomes 8 [μm].

Although the above dimensions can be easily achieved using the present invention, other techniques would reduce the gate length to 1 [μ
m] and the width of the isolation region IS to 2 m.
This value cannot be achieved unless it is made as fine as [μm].

Generally, in a sense amplifier, sensitivity deteriorates unless variations in the threshold values of transistors are sufficiently suppressed, and a short gate length of about 1 [μm] is disadvantageous in terms of variations in threshold values. Further, it is impossible to make the width of the isolation region IS 2 [μm] using the current selective oxidation method.

Now, in order for the transistor Q5 to be always off and to electrically isolate the sense amplifiers, it is preferable that its gate electrode be grounded, but separately providing a grounding wiring for the sense amplifier is For this purpose, an occupied area is required.

Therefore, in the present invention, the gate electrode of transistor Q5 is connected to the common source region S _c of the sense amplifier.

Since the wiring related to the common source pull-down circuit of the sense amplifier is essentially required for driving the sense amplifier, its existence does not result in wasted occupying area.

The source and drain of transistor Q5 are bit lines, and since the bit line is always at a higher potential than the common source of the sense amplifier, if transistor Q5 is an n-channel transistor, its gate electrode is higher than the source. It is always at a low potential.

Therefore, transistor Q5, which isolates the sense amplifiers, satisfies the requirement that it always remain cut off.

In this way, when the sense amplifiers are isolated by the gate electrode of the transistor Q5, the isolation region IS has a finer width than when the field region F is used to isolate the sense amplifiers, and the gate electrode of the peripheral circuit (including the sense amplifier) becomes smaller. As electrodes become finer, the width of the isolation region IS also becomes finer, resulting in better overall pattern symmetry.Moreover, special fine isolation technology, such as trench isolation, is required. There is no need for techniques such as digging minute grooves in the material and filling them with insulators.

Also, the sense node, that is, the transistor Q1,
Since the bit line connection part of Q2 or transistors Q3 and Q4 is sandwiched between gate electrode patterns on the same layer, its dimensions are always constant, and there is no misalignment in mask alignment between the active region and the gate electrode pattern. Even if this occurs, the sense node will not be affected in any way.

Furthermore, during manufacturing, the area around the gate electrode is covered with an insulator, and the metal or polycrystalline silicon wiring on the gate electrode makes contact with the source or drain using only the thickness of the insulator, and the contact portion and gate are The so-called self-container is separated from the electrode.
Alignment contact is possible.

In particular, when a self-alignment contact is formed between the bit line and the transfer gate transistor in a memory cell,
If self-alignment contact is not performed for the sense amplifier as well, the pitch of the column and the pitch of the sense amplifier will not match.

The reason for this is that although the pattern becomes finer, the alignment accuracy between layers does not improve, and the alignment tolerance between the gate electrode and the contact hole increases the size of the sense amplifier.

Effects of the Invention The semiconductor memory device of the present invention includes a plurality of sense amplifiers in which the drains and sources of each of two transistors are cross-connected and the sources are commonly connected, and adjacent ones of the plurality of sense amplifiers are a field effect transistor formed in the active region and having a gate electrode connected to a common source region of the sense amplifiers for electrically isolating the adjacent sense amplifiers; Therefore, even if the gate electrode of each transistor in the sense amplifier and the gate electrode of the field effect transistor for electrically isolating each sense amplifier are slightly shifted from the active region, Since there is no difference in area between the drain regions of the transistors, so-called sense amplifier bias does not occur.
In addition, since the electrical isolation between each sense amplifier is achieved by a single field effect transistor, the area occupied is significantly smaller than when isolation is done in the field area, making it possible to achieve high-density memory. It is suitable for

[Brief explanation of drawings]

FIG. 1 is a plan view of essential parts of a conventional example, FIG. 2 is a plan view of essential parts of an embodiment of the present invention, and FIG. 3 is a circuit diagram of essential parts of the embodiment shown in FIG. In the figure, F is a field region, FB is a field region boundary, IS is an isolation region between adjacent sense amplifiers, S _c is a common source region, D1 and D2 are drain regions, BL is a polycrystalline silicon bit line, G1 and G2 are polycrystalline silicon gate electrodes, SCL is a common source pull-down circuit, Q1
Q6 to Q6 respectively indicate transistors.

Claims (1)

[Scope of Claims] 1. A plurality of sense amplifiers each having two transistors whose drains and gates are cross-connected and whose sources are commonly connected, and an activation common to adjacent ones of the plurality of sense amplifiers. a field effect transistor formed in the active region and having a gate electrode connected to a common source region of the sense amplifiers for electrically isolating the adjacent sense amplifiers. semiconductor storage device. 2. The semiconductor memory device according to claim 1, wherein the gate electrode of the field effect transistor formed to electrically isolate the sense amplifier is a shotgun gate electrode.