JPH04167170A - Multiplication/addition arithmetic circuit - Google Patents

Abstract

PURPOSE:To perform a multiplication/addition arithmetic operation continuously and at high speed by clipping a computed result to a positive maximum value when overflow occurs to a positive side and a value nearest to a negative maximum value expressible in an arithmetic and logical unit when the overflow occurs to a negative side. CONSTITUTION:When the overflow occurs, an overflow signal line 100 goes to '1'. An overflow clipping circuit 21, when detecting the fact that the overflow signal line 100 goes to '1', checks a code bit outputted from the arithmetic and logic unit(ALU) 15, and performs such control to input clipped data from a clip data input terminal 101 when the code bit shows '0', and to fix the output of each selector 22 at positive maximum value. Also, when the code bit shows '1', the output of each selector 22 in the overflow clipping circuit 21 is controlled so as to be fixed at the negative maximum value.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a multiplication/addition calculation circuit, particularly a digital signal processing device that processes data input in time series based on a predetermined algorithm and outputs it as time series data. This invention relates to multiplication and addition calculation circuits used in

[Prior Art] Conventionally, a digital signal processing device (DSP system: digital signal processing system) is known as a system that processes an analog signal using a digital method.

Digital signal processing devices are capable of highly accurate processing compared to analog signal processing, and have characteristics such as being able to stably and uniformly obtain arbitrary characteristics by setting parameters, and eliminating the need for adjustment. For this reason, the application range of digital signal processing devices has expanded to a wide range such as audio signal processing and communication signal processing.

Usually, the digital signal processing device described above has the configuration shown in FIG. 2 so as to form a digital filter.

In the figure, the data bus 11 includes an input/output circuit (Ilo
) 12, data RAM 13, multiplier 14, arithmetic circuit (A
LU) 15, accumulator (ACC) 16, etc. are connected. In addition, the output of data RAM 13 and data RO
The output of M17 is connected to the multiplier 14, and the multiplication result output of the multiplier 14 is connected to one input of the arithmetic unit (ALU) 15.

Each of these circuits is controlled by a microcode signal decoded by a decoder 19 in accordance with instructions sequentially read from the program ROM 18.

In realizing the digital filter of this type of digital signal processing device, Y-A-Xi +B-Xi~l+c-Xj-2...
(1) Multiplication and addition operations of the form are repeatedly performed.

Therefore, when realizing this digital filter with a digital signal processing device, the calculation order of the nodes in the filter is determined, a program is created, the program is stored in the program ROM 18, and each coefficient is stored in the data ROM 17. Store it. Then, by executing the program, multiplication and addition operations are performed, and the results of the operations are sequentially stored in the data RAM 1B.

The multiplication/addition calculation circuit used in the digital signal processing device that implements the digital filter described above performs fixed-point calculations where the data handled is two's complement, and the number is expressed as shown in Figure 3. .

That is, in the number system in such a fixed-point arithmetic circuit, the data n handled falls within the range of 1>n≧-1·ψ (2). Therefore, in such a number system in a fixed-point arithmetic circuit, when the maximum negative value is multiplied by the maximum negative value, the maximum positive value that can be expressed by the fixed-point arithmetic circuit is exceeded.

In other words, the multiplication of the maximum negative value (-1) and the maximum negative value (-1) should be -IX-1-1, but as is clear from equation (2) above, in this arithmetic unit, Since positive 1 cannot be handled, an overflow will occur.

Conventional digital signal processing devices have taken the following measures against this overflow.

■ Since the multiplication of the maximum negative value x the maximum negative value will cause an overflow, the software is guarded to prevent multiplication of this combination.

■ Generate an overflow flag when the product is multiplied by the maximum negative value x the maximum negative value, detect the flag using software, and correct the overflow data.

■ When a multiplication of the maximum negative value x the maximum negative value is performed, the multiplier circuit clips to the maximum positive value that can be represented by hardware.

In addition, overflow occurs in the arithmetic circuit as well as in the multiplier. Overflow in an arithmetic circuit includes overflow on the positive side and overflow on the negative side. Generally, the output of the arithmetic circuit is provided with a circuit that outputs a maximum positive value in response to an overflow on the positive side, and outputs a maximum negative value in response to an overflow on the negative side.

Among the countermeasures against overflow in the conventional digital signal processing apparatus described above, overflow countermeasures using software will be explained using the conventional digital signal processing apparatus shown in FIG.

An example will be explained in which a digital filter is constructed by repeating the multiplication and addition shown in equation (1). First, input data x1 and coefficient A are input to the multiplier 14 and multiplied. Whether or not there is an overflow as a result of this multiplication is determined by the overflow flag of the multiplier 14. If there is no overflow, the multiplication result is held in the ACC 16 via the arithmetic circuit 15. When an overflow occurs, that is, when the maximum negative value is multiplied by the maximum negative value, the maximum positive value is applied to the input of the arithmetic circuit 15 instead of the output of the multiplier 14, and the A.C.
It is held at C16. Next, the multiplier 14 multiplies the input data x i-1 of the previous sample stored in the data RAM 1B by the coefficient B.

It is determined whether or not there is an overflow in the result of this multiplication in the same way as described above. If there is no overflow, the arithmetic circuit 15 adds the multiplication result and the previous multiplication result held in the ACC 176. As a result of this addition, if there is no overflow, the addition result is held in ACC16, if there is a positive overflow, the maximum positive value is held in ACC16, and if there is a negative overflow, the maximum negative value is held in ACC16.
It is held at 6. By repeating similar multiplication and addition,
The ACC 16 obtains data that has been subjected to one stage of filter processing. This data is stored in the data RAM 13 for filtering the next sampling data, and is applied to the multiplier 14 as an input for the next stage of filtering. Then, multiplication and addition with the second-stage filter coefficient are performed in the same manner as described above. Of course, overflow is determined when outputting and adding each multiplication result.

In this way, the software detects the occurrence of overflow as a result of multiplication and outputs the output of the multiplier 14 as the maximum positive value (0, 11111...1) to the conversion circuit 16 according to the detection result. was.

[Problems to be Solved by the Invention] However, when performing calculations for realizing a digital filter using a digital signal processing device, the multiplication and addition calculations are required to be performed continuously and at high speed. In addition, the above-mentioned software-based overflow countermeasure requires too much time for software-based overflow detection and avoidance processing.

Therefore, in conventional digital signal processing devices, when multiplication and addition operations are performed in digital filters, etc., the operation result often becomes the next multiplicand, so if the operation result is set to the maximum negative value due to overflow, the multiplier circuit will again that there is a high possibility that the multiplication of the maximum value x the negative maximum value will be performed;
Since multiplication and addition operations are required to be performed continuously and at high speed, the above-mentioned software measures against overflow have the problem of taking too much program processing time and not being able to provide sufficient countermeasures.

In addition, when the multiplication of the maximum negative value x the maximum negative value is performed, the countermeasure (2) above, in which hardware clips the maximum positive value that can be expressed in the multiplier circuit, causes the multiplier circuit to overflow at the output. Since this requires a dedicated circuit to determine the presence or absence of overflow and to clip to the maximum positive value when an overflow occurs, there is a problem in that it is disadvantageous in terms of circuit scale and calculation speed.

The present invention was made to solve the above-mentioned problems, and requires a dedicated circuit to clip to the positive maximum value when an overflow occurs due to the multiplication of the negative maximum value x the negative maximum value. The purpose of this invention is to obtain a multiplication/addition operation circuit for a digital signal processing device that can perform multiplication/addition operations continuously and at high speed without any problems, and that satisfies requirements in terms of circuit size and operation speed. .

Here, the inventors of the present invention focused their attention on a clip circuit when an overflow occurs in an adder in a conventional digital signal processing device. In other words, in conventional digital signal processing devices, overflow may occur even in addition processing, so when an overflow occurs on the positive side, the maximum positive value is set, and when an overflow occurs on the negative side, the maximum negative value is clipped. The present invention was completed by noting that the clipped data becomes the multiplicand again.

[Means for Solving the Problems] When an overflow occurs as a result of an addition operation, the multiplication/addition operation circuit according to the present invention returns to the maximum positive value when the overflow occurs to the positive side, and returns to the maximum positive value when the overflow occurs to the negative side. The present invention is characterized in that it includes a clipping circuit for clipping the calculation result to a negative value closest to the maximum negative value that can be expressed by the calculation circuit.

[Operation] Therefore, according to the multiplication and addition operation circuit of the present invention, when an overflow occurs as a result of an addition operation, when the overflow occurs to the positive side, the maximum positive value is returned, and when the overflow occurs to the negative side, the operation circuit returns to the maximum positive value. Since the calculation result is clipped to the negative value closest to the maximum negative value that can be expressed as This eliminates the possibility of value multiplication.

[Example code] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a multiplication/addition calculation circuit according to the present invention.

In FIG. 1, the multiplication and addition calculation circuit of the present invention includes a multiplier 1
4, an arithmetic unit (ALU) 15, an overflow clip circuit 21, and an accumulator (ACC) 16. It has a selector 22.

Then, the multiplication result output of the multiplier 14 is output from the arithmetic circuit (ALU).
) 15 is applied to one input.

In addition, the overflow clip circuit 21 is an arithmetic circuit (A
When the calculation result from the LU) 15 is input and no overflow occurs as a result of the addition calculation, the overflow signal line 100 is "0", so each selector 22 selects the output of the calculation circuit (ALU) 15. and inputs it to the accumulator (ACC) 16.

On the other hand, when an overflow occurs as a result of an operation in the arithmetic unit (ALU) 15, the overflow signal line 100
becomes “1”. The overflow clip circuit 21 is
When it is detected that the overflow signal line 100 is "1", the sign bit output from the arithmetic unit (ALU) 15 is checked, and if the sign bit is "0", the clip data is output from the clip data input terminal 101. is input, and the output of each selector 22 is set to the maximum positive value (0°1111
...1) is controlled to be fixed.

Further, if the sign bit is #1'', the output of each selector 22 of the overflow clipping circuit 21 is the negative maximum value (
1,000...01).

In other words, if an overflow occurs as a result of an addition operation, the operation result will be clipped to the maximum positive value if it overflows to the positive side, and to the negative value closest to the maximum negative value if it overflows to the negative side. be done.

[Effects of the Invention] As explained above, according to the multiplication/addition operation circuit of the present invention, when an overflow occurs as a result of an addition operation, when the overflow occurs on the positive side, the overflow occurs to the maximum positive value, and when the overflow occurs on the negative side, the overflow occurs to the positive maximum value. When a calculation result is calculated, the calculation result is clipped to the negative value closest to the maximum negative value that can be expressed by the calculation circuit. In the addition calculation circuit, it is possible to eliminate the possibility of multiplication of the negative maximum value x the negative maximum value, and to clip it to the positive maximum value when an overflow occurs due to the multiplication of the negative maximum value x the negative maximum value. does not require a dedicated circuit, and
Multiplying and adding operations can be performed continuously and at high speed, which has the effect of satisfying requirements in terms of circuit scale and operation speed.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a multiplication/add operation circuit showing an embodiment of the present invention, Fig. 2 is a block diagram of a digital signal processing device forming a conventional digital filter, and Fig. 3 is a digital signal realizing the digital filter. FIG. 2 is a diagram showing a numerical expression taken in an arithmetic circuit used in a processing device (that is, a fixed-point arithmetic circuit that performs multiplication-add operations and handles data as a two's complement number); 11... Data bus 12... Input/output circuit (I10) 13...
Data RAM 14... Multiplier 15... Arithmetic circuit (ALU) 16...
Accumulator (ACC) 17... Data ROM 18... Program ROM 19... Decoder 21... Overflow clip circuit 22...
・Selector

Claims (1)

[Claims] A multiplication and addition calculation circuit used in a digital signal processing device etc. that realizes a digital filter and performing multiplication and addition operations, in which an overflow occurs as a result of the addition operation, and when an overflow occurs on the positive side. A multiplication/addition system characterized by having a clipping circuit for clipping the calculation result to the maximum positive value, and when overflowing to the negative side to the negative value closest to the maximum negative value that can be expressed by the calculation circuit. Arithmetic circuit.