JPH0416946B2 - - Google Patents
Info
- Publication number
- JPH0416946B2 JPH0416946B2 JP57195774A JP19577482A JPH0416946B2 JP H0416946 B2 JPH0416946 B2 JP H0416946B2 JP 57195774 A JP57195774 A JP 57195774A JP 19577482 A JP19577482 A JP 19577482A JP H0416946 B2 JPH0416946 B2 JP H0416946B2
- Authority
- JP
- Japan
- Prior art keywords
- input
- pad
- power supply
- circuit
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は、一部マスク変更で作られるセミカス
タムな半導体装置（IC）のパツド形成に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the formation of semi-custom semiconductor device (IC) pads that are made by partially changing masks.
最近、ゲートアレーに代表されるマスタースラ
イスセミカスタムICが広く使われ始めている。
通常、ゲートアレー（以下GAと略記）では、１
層もしくは２層程度の配線層マスクの切換えによ
り、ユーザー仕様の回路を作り込んでいく。また
入力パツドは、各回路に於いて必要最小数を使う
のが普通であり、多くの場合、数ないし数十のパ
ツドは不用になつていた。 Recently, master slice semi-custom ICs such as gate arrays have begun to be widely used.
Normally, in a gate array (hereinafter abbreviated as GA), 1
A user-specified circuit is created by switching the wiring layer mask for one or two layers. In addition, it is common practice to use the minimum number of input pads necessary for each circuit, and in many cases, several to several dozen pads are unnecessary.
従来のCMOSGAに於いて、このような不用パ
ツドの処理は、不用パツドを全く形成しないか、
形成しても入出力回路あるいは電源とも無接続の
状態であつた。従つて、不用パツドのスペースが
無駄になるという欠点があつた。また、従来で
は、パツドが不用になると、そのパツドに対応す
る入出力回路も不用となるが、入力回路の入力端
子はどこにも接続されないままであつた。従つ
て、入力端子が中間電位になりCMOS回路であ
る入力回路に多大な電流が流れ、消費電力が大き
くなると共に電源が不安定になるという欠点を有
していた。 In conventional CMOSGA, processing of such unnecessary pads either does not form unnecessary pads at all, or
Even if it was formed, it was not connected to the input/output circuit or power supply. Therefore, there is a disadvantage that the space of unnecessary pads is wasted. Conventionally, when a pad is no longer needed, the input/output circuit corresponding to the pad is also no longer needed, but the input terminal of the input circuit remains unconnected to anything. Therefore, the input terminal has an intermediate potential, and a large amount of current flows through the input circuit, which is a CMOS circuit, resulting in an increase in power consumption and an unstable power supply.
まず、従来の欠点を解決した出願人に於て周知
でない先行技術として認識されるCMOS・GAの
構成を第１図に示す。図中、１０１は入力もしく
は出力パツド、１０３は入出力回路であり、パツ
ド１０１は必要に応じて入出力回路１０３に接続
され入力もしくは出力パツドとして使用される。
１０４は入出力回路１０３に接続される内部回路
である。入力もしくは出力に使用しない不用パツ
ド１０１に入出力回路１０３の入力回路の入力端
子１０２を接続することなく、接地電位もしくは
電源電圧と同電位の電源線に接続する。これは、
特に入力端子を接地電位もしくは電源電位に接続
しておかないと、入力端子が中間電位となつて
CMOS回路である入力回路に多大な電流が流れ
るのを防ぐためである。従つて、パツドと接続さ
れない入力回路に於いて無意味な電流が流れるこ
となく、低消費電力化が達成される。更に、多大
な電流が流れると半導体装置の電源が不安定とな
るが、そのような心配も不用となる。 First, FIG. 1 shows the configuration of a CMOS/GA, which is recognized as a prior art that is not well known to the applicant and has solved the conventional drawbacks. In the figure, 101 is an input or output pad, 103 is an input/output circuit, and the pad 101 is connected to the input/output circuit 103 as necessary and used as an input or output pad.
104 is an internal circuit connected to the input/output circuit 103. The input terminal 102 of the input circuit of the input/output circuit 103 is not connected to the unnecessary pad 101 that is not used for input or output, but is connected to the ground potential or a power line having the same potential as the power supply voltage. this is,
In particular, if the input terminal is not connected to ground potential or power supply potential, the input terminal will be at an intermediate potential.
This is to prevent a large amount of current from flowing into the input circuit, which is a CMOS circuit. Therefore, no meaningless current flows in the input circuit that is not connected to the pad, and low power consumption is achieved. Furthermore, there is no need to worry about the instability of the power supply of the semiconductor device when a large amount of current flows.
しかし、第１図の先行技術では、不用パツド１
０１は電源に接続されておらず、何らかの要因で
電源変動があつた場合には入力回路の入力端子１
０２の電位も変動して、多大な電流が入力回路に
流れてしまう恐れが依然として存在していた。 However, in the prior art shown in FIG.
01 is not connected to the power supply, and if the power supply fluctuates due to some reason, the input terminal 1 of the input circuit
There was still a risk that the potential of 02 would also fluctuate and a large amount of current would flow into the input circuit.
本発明は、従来及び先行技術の欠点を解決し、
従来何ら役に立つていなかつた不用パツドと不用
パツドから入力を受けない入力回路の入力端子を
電源に接続することにより、不用パツドのスペー
スの有効活用を図ると共に半導体装置の電源の安
定化を図ることを目的とする。 The present invention solves the drawbacks of the conventional and prior art,
By connecting the input terminals of the input circuits that do not receive input from the unused pads and the unused pads that have not been used in the past to the power supply, it is possible to effectively utilize the space of the unused pads and to stabilize the power supply of the semiconductor device. purpose.
以下、図面に基づき本発明を説明する。第２
図、第３図に本発明の実施例を示す。これらの実
施例は、第１図に更に不用パツドを接地電位もし
くは電源電位の電源線に接続して電源用パツドと
する構成を加えたものである。第２図に於いて、
２０１はパツド、２０３は入力回路、２０４は内
部回路である。不用パツド２０１と入力回路２０
３の入力端子２０２は接続され、接地電位もしく
は電源電位の電源線に接続される。また、第３図
に於いで、３０１はパツド、３０３は入力回路、
３０４は内部回路である。不用パツド３０１は接
地電位もしくは電源電位の電源線に接続し、入力
回路３０３の入力端子３０２を入力パツド３０１
と逆電位の電源線に接続する。上記の２つの実施
例で共通しているのが、回路的に不用なパツドが
電源用パツドとして使われていることである。更
に、２つの実施例では、第１図と同様に入力回路
の入力端子も電源線に接続されている。 The present invention will be explained below based on the drawings. Second
Embodiments of the present invention are shown in FIGS. In these embodiments, a configuration is added to FIG. 1 in which an unnecessary pad is connected to a power line of ground potential or power supply potential to serve as a power pad. In Figure 2,
201 is a pad, 203 is an input circuit, and 204 is an internal circuit. Unused pad 201 and input circuit 20
The input terminal 202 of No. 3 is connected to a power line at ground potential or power supply potential. In addition, in Fig. 3, 301 is a pad, 303 is an input circuit,
304 is an internal circuit. The unnecessary pad 301 is connected to a power line with ground potential or power supply potential, and the input terminal 302 of the input circuit 303 is connected to the input pad 301.
Connect to a power line with the opposite potential. What the above two embodiments have in common is that pads that are unnecessary in terms of circuitry are used as power supply pads. Furthermore, in the two embodiments, the input terminals of the input circuits are also connected to the power supply line as in FIG.
以上の本発明によれば、パツドに接続されない
入力回路の入力端子を電源に接続し、入力回路に
電流が流れないようにしているので、半導体装置
を低消費電力化でき、また入力回路にて多大な電
流が流れないので半導体装置の電源の低下や変動
を引き起こすこともなくなる。加えて、不用パツ
ドのスペースを有効に利用し、不用パツドを電源
に接続するため、電源線に広い面積のパツドが接
続されて電源線の配線容量が増し、電源の低下や
変動を押さえることができる。従つて、電源に接
続した入力回路の入力端子の電位が変動して、入
力回路に多大な電流が流れる恐れもなくなる。 According to the present invention described above, the input terminal of the input circuit that is not connected to the pad is connected to the power supply to prevent current from flowing into the input circuit, so that the power consumption of the semiconductor device can be reduced. Since a large amount of current does not flow, there is no possibility of a drop or fluctuation in the power supply of the semiconductor device. In addition, in order to effectively use the space of unused pads and connect unused pads to the power supply, a pad with a wide area is connected to the power line, increasing the wiring capacity of the power line and suppressing power drops and fluctuations. can. Therefore, there is no fear that the potential of the input terminal of the input circuit connected to the power supply will fluctuate and a large amount of current will flow through the input circuit.
また、半導体チツプ内に電源用パツドが多く設
置できるので、チツプ実装時にワイヤーボンデイ
ングの自由度が非常に大きくなる。 Furthermore, since many power supply pads can be installed within a semiconductor chip, the degree of freedom in wire bonding during chip mounting is greatly increased.
第１図は先行技術を示す図、第２図及び第３図
は本発明の実施例を示す図である。
FIG. 1 is a diagram showing the prior art, and FIGS. 2 and 3 are diagrams showing an embodiment of the present invention.
Claims (1)
接続され入力もしくは出力パツドとして使用され
るべきパツドとを備えるマスタースライスな半導
体装置に於いて、前記パツドであつて入力もしく
は出力パツドとして使用されないパツドを該半導
体装置の電源線に接続して電源用パツドとして用
い、当該パツドから入力を受けない前記入出力回
路の入力回路の入力端子を該入力回路にて電流が
流れないように該半導体装置の電源線に接続して
なることを特徴とする半導体装置。1. In a master slice semiconductor device comprising an input/output circuit and a pad that is connected to the input/output circuit as necessary and used as an input or output pad, the pad used as the input or output pad A pad that is not connected to the semiconductor device is connected to the power supply line of the semiconductor device and used as a power supply pad, and the input terminal of the input circuit of the input/output circuit that does not receive input from the pad is connected to the semiconductor device so that no current flows in the input circuit. A semiconductor device characterized by being connected to a power supply line of the device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57195774A JPS5984547A (en) | 1982-11-08 | 1982-11-08 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57195774A JPS5984547A (en) | 1982-11-08 | 1982-11-08 | semiconductor equipment |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21080190A Division JPH03241763A (en) | 1990-08-09 | 1990-08-09 | semiconductor equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5984547A JPS5984547A (en) | 1984-05-16 |
| JPH0416946B2 true JPH0416946B2 (en) | 1992-03-25 |
Family
ID=16346738
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57195774A Granted JPS5984547A (en) | 1982-11-08 | 1982-11-08 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5984547A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61229103A (en) * | 1985-04-04 | 1986-10-13 | Canon Inc | Controller of copying machine or the like |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5561054A (en) * | 1978-10-30 | 1980-05-08 | Mitsubishi Electric Corp | Large scale integrated circuit |
| JPS58197746A (en) * | 1982-05-14 | 1983-11-17 | Hitachi Ltd | Semiconductor integrated circuit device |
-
1982
- 1982-11-08 JP JP57195774A patent/JPS5984547A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5984547A (en) | 1984-05-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6674177B2 (en) | Apparatus for implementing selected functionality on an integrated circuit device | |
| US5422441A (en) | Master slice integrated circuit having a reduced chip size and a reduced power supply noise | |
| JPH0936311A (en) | Semiconductor device | |
| JP2003100891A (en) | Semiconductor integrated circuit device | |
| JPS6011462B2 (en) | semiconductor equipment | |
| JP2682397B2 (en) | Cell-based design semiconductor integrated circuit device | |
| JP2681427B2 (en) | Semiconductor device | |
| JPH0416946B2 (en) | ||
| JPH09107070A (en) | Semiconductor integrated circuit device | |
| JP2791067B2 (en) | Monolithic overvoltage protection assembly | |
| JPH0669276A (en) | Semiconductor device | |
| JPH06163700A (en) | Integrated circuit device | |
| JP2004022777A (en) | Semiconductor device | |
| JPH01257348A (en) | Standard cell integrated circuit device | |
| JP2878765B2 (en) | Semiconductor device | |
| JPH0243343B2 (en) | ||
| JPS6127654A (en) | Master slice integrated circuit device | |
| JPH04326575A (en) | Integrated circuit device | |
| JPS61180470A (en) | Semiconductor integrated circuit device | |
| JP2003124331A (en) | Semiconductor integrated circuit device | |
| JPS6211256A (en) | Semiconductor integrated circuit device | |
| JPH03241763A (en) | semiconductor equipment | |
| JPS60211864A (en) | Input circuit for semiconductor device | |
| JPS62224043A (en) | Semiconductor integrated circuit device | |
| JPH04273147A (en) | Gate array type semiconductor integrated circuit |