JPH0417485B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field The present invention relates to a graphic equalizer that corrects a sound field, and particularly to a graphic equalizer equipped with a display device that displays the signal strength of each band.

(B) Prior Art Generally, when recording music, etc., there are frequency characteristics that are emphasized, and this emphasis during recording is corrected during playback. However, when looking at the band components of the sound range, some parts are emphasized and others are attenuated due to reasons such as sound field resonance, and a graphic equalizer is used to correct such sound fields. ing.

As shown in Fig. 1, the conventional graphical equalizer has only one amplifier, amplifier 1, that amplifies the input signal _Vi , and has a band filter on the input side to divide the input signal into multiple bands. 2a...2n
were provided, and the center frequency f ₀ ... _fo of each band was set by the band filters 2a...2n. Further, on the input side of the amplifier 1, variable resistors 3a...3n are connected to each band filter 2a...2n, and by adjusting the variable resistors 3a...3n, the amplification amount and the amount of signal in each band can be adjusted. It was configured so that the amount of attenuation could be set. Therefore, the output V _p of the amplifier 1 is a signal obtained by mixing signal components of each band. In addition, when displaying the signal strength of each band, band filters 4a...4n are provided for each band in order to divide the output of the amplifier 1 into each band again, and the detection circuits 5a...5n divide the output by the band filters 4a...4n. The detected signal component is detected and the detected output is
The AD converters 6a...6n convert the digital signals to display drive circuits 7a...7.
n, the intensity of the signal component in each band can be displayed on the display 8 composed of LED, LCD, FL, etc.
a...It was displayed as 8n.

In this way, in conventional graphic equalizers, there is only one amplifier that amplifies the input signal, and its output signal is a mixed signal of signal components of each band, so when displaying the signal strength of each band has the disadvantage that a bandpass filter must be installed on the output side of the amplifier;
This was a hindrance to the introduction of ICs. Another disadvantage is that it is necessary to adjust the band filter on the input side of the amplifier and the display band filter provided on the output side of the amplifier.

(c) Purpose The present invention provides a graphical equalizer with a novel configuration that is ideal for IC implementation and can reliably display the signal strength of each band without providing a display band filter on the output side of the amplifier. The purpose is to provide

(D) Embodiment FIG. 2 is a block diagram showing an embodiment of the graphic equalizer according to the present invention. Each amplifier is provided with an amplifier that amplifies or attenuates only the band component of the selected band, and FIG. 2 shows an amplification stage for an arbitrary and unique band and a display block for displaying the signal strength of that band.

In FIG. 2, 9 is a band filter that determines the center frequency to set the band to be selected from among the frequency bands of the input signal; 10 is an amplifier that amplifies or attenuates only the band component set by the band filter 9; Reference numeral 11 indicates a resistance circuit consisting of a plurality of resistors connected between the input terminals of the amplifier, and reference numeral 12 indicates 12 resistor circuits each having one end connected to the connection point of each resistor of the resistance circuit 11 and the other end commonly connected to the bandpass filter 9. A switching circuit 13 consisting of switches S ₁ to S ₆ and S ₈ to _{S 13} decodes switching information C ₀ from the latch circuit 14,
13-bit switching signal for turning on only one switch among multiple switches in switching circuit 12
This is a decode that generates D ₁ to D ₁₃ , and switching circuit 1
The amplification degree of the amplifier 10 is determined by switching the switch No. 2.

Reference numeral 15 denotes a control unit that sends switching information corresponding to the operation key 16 to the shift register 17. The switching information input to the shift register 17 is latched by the latch circuit 14 and input to the decoder 13 described above. In this embodiment, the switching information is 4 bits.

Further, 18 is composed of a differential amplifier 19 and a resistor, and inputs the input signal and output signal of the amplifier 10,
A subtraction circuit 20 generates a difference signal E ₀ between both signals, and 20 is a conversion circuit for converting the difference new signal E ₀ into a signal suitable for display. This conversion circuit 20 has the same configuration as the decoder 13, 4 from latch circuit 14
A decoder 21 that decodes the bit switching information _C0 and generates 13-bit switching signals _D1 to _D13 , an amplifier 22 that amplifies the difference signal _E0 , and the decoder 21
A correction circuit 23 corrects the amplification degree of the amplifier 22 according to a switching signal from the amplifier 22. This correction circuit 23 includes 13 switches S ₁ to S ₁₃ that are turned on and off according to switching signals D ₁ to D ₁₃ from the decoder 21 and a resistor 24 connected to each switch.
It is equipped with a...24g...24m. Also, 5, 6,
7a and 8a are a detection circuit, an AD converter, a display drive circuit, and a display device, respectively, as in the conventional example shown in FIG.

Therefore, for example, if the operation key 16 is operated to maximize the amplification amount of the amplifier 10, "1100" is latched in the latch circuit 14 as switching information C ₀ , and this information is input to the decoder 13 to switch. Among the signals D ₁ to D ₁₃ , only signal D ₁₃ becomes “1”,
Therefore, switch _S13 is turned on. Moreover, if the operation key 16 is operated to maximize the attenuation amount, the switching information "0000" is latched in the latch circuit 14, and only the signal D ₁ among the switching signals D ₁ to D ₁₃ becomes "1".
Then, the switch _S1 of the switching circuit 12 is turned on.

In this way, the switch of the switching circuit 12 is changed according to the operation of the operation key 16, and the amplification degree of the amplifier 10 is set. However, since the bandpass filter 9 is connected to one end of the switch, the input signal is Only the band component set by the band filter 9 in the frequency band is amplified or attenuated by the amplifier 10 according to the amplification degree determined by the switch of the switching circuit 12. That is, if the center frequency of the bandpass filter 9 is f ₀ and this band is called the f ₀ band, the amplification degree of the amplifier 10 other than the f ₀ band is 1, and the input signal and output signal of the amplifier 10 are By comparison, both signals are at the same level except in the f ₀ band. Therefore, only the level difference between the input signal and the output signal in the f ₀ band appears in the output of the subtraction circuit 18. Therefore, based on the difference signal E ₀ that is the output signal of the subtraction circuit 18, it is possible to display the signal strength in the f ₀ band.

Next, the conversion circuit 20 will be explained with reference to FIG. 3.

Here, for the sake of explanation, the switching circuit 12 in FIG.
The amount of change in amplification and attenuation by the switch is 2dB.
Assuming that the attenuation amounts for switches S ₁ , S ₂ , ..., S ₆ are respectively -12 dB, -10 dB, ... -2 dB, the switches
S ₈ , S ₉ ...Amplifiers for S ₁₃ are +2dB and +2dB, respectively.
4dB, ..., +12dB.

FIG. 3 is a characteristic diagram showing the relationship between the amplification and attenuation amount T and the difference signal E ₀ of the subtraction circuit 18 when the level of the input signal to the amplifier 10 is kept constant under the above assumption.

By the way, since the subtraction circuit 18 extracts the difference signal between the input signal and the output signal of the amplifier 10,
Although signal components outside the f ₀ band are removed, the amplifier 1
In the case of amplification at 0 and the case of attenuation, the same positive output appears as shown in curve A in FIG. 3, and it is difficult to distinguish between amplification and attenuation. Furthermore, since the subtraction circuit 18 extracts the difference signal, the signal strength of the difference signal E ₀ is not proportional to the signal strength of the output signal of the amplifier 10, as shown by curve A in FIG. That is, it is not proportional to the amount of amplification and attenuation T.

Therefore, in FIG. 2, the amplification degree of the amplifier 22 to which the difference signal E ₀ of the subtraction circuit 18 is input is corrected in accordance with the switching information C ₀ from the latch circuit 14. That is, each resistor 24a...24g... of the correction circuit 23 is set to a resistance value that corrects the difference signal _E0 shown by the white circle Γ on the curve A in FIG. 3 to the signal level shown by the black circle ● on the straight line B. It constitutes 24m. For example, for the resistors 24a, 24e, 24j, and 24l, when the switches S ₁ , S ₅ , S ₁₀ , and S ₁₂ are turned on, the amplification degree of the amplifier 22 is 0.26 times,
The resistance values are determined to be 1.3 times, 1.5 times, and 1.1 times, respectively. A decoder 21 having exactly the same configuration as the decoder 13 is provided, and switching signals D ₁ to D ₁₃ of the switches S ₁ to S ₆ and S ₈ to _{S 13} of the switching circuit 12 are provided.
_The correction circuit ₂
3 switches _S1 to _S13 . In this way, when the signal strength of the input signal of the amplifier 10 is constant, the output of the amplifier 22 that amplifies the difference signal _E0 of the arithmetic circuit 18 will be amplified and attenuated as shown in FIG. It becomes proportional to T.

Therefore, if the output signal of the amplifier 22 is detected and then AD-converted as in the conventional case, and the AD-converted output is supplied to the display drive circuit 7a, the signal strength in the f ₀ band can be displayed.

By the way, if the amplifier 10 does not perform any amplification or attenuation, the operation key 16 is operated to cause the latch circuit 14 to latch the switching information "0111" and set the switching signal _D7 to "1". In this case, as shown by the broken line in FIG.
If a switch _S7 is connected between the two, and this switch _S7 is turned on by a switching signal _D7 , the amplification degree of the amplifier 10 becomes 1, and the amplifier 10 performs neither amplification nor attenuation. However, in this case,
Since the difference signal E ₀ of the subtraction circuit 18 becomes 0, it becomes impossible to display the signal strength of the band.

Therefore, in Fig. 2, the amplifier 1 is connected to the B side when the switching signal _D7 is "0", and switched to the A side only when it becomes "1".
A bypass switch circuit 25 is provided which connects the input side of 0 directly to the output side to bypass the amplifier 10, and an OR gate 3 which inputs the switching signals _D13 and _D7 and controls the switch _S13 of the switching circuit 12 with its output.
5 is set. Therefore, when the amplifier 10 does not perform any amplification or attenuation, the switching signal D ₇ becomes "1", so that the input signal of the amplifier 10 is bypassed to the output side, and the switching circuit 12
When the switch _S13 is turned on, a difference signal _E0 appears from the subtraction circuit 18, which is exactly the same as when the switching signal _D13 becomes "1". Along with this, decoder 2
1 switching signal D ₇ also becomes "1", so the switch
_S7 turns on. Therefore, by appropriately selecting the value of the resistor 24g connected to the switch _S7 , the output of the amplifier 22 can be set to a predetermined value on the straight line RO in FIG. That is, even when the amplifier 10 does not perform amplification or attenuation, it is possible to display the signal strength of the band. In the above description, switch S ₁₃ is turned on by switching signal D ₇ , but switch S ₇
You may also turn on other switches than the
What is necessary is to change the value of the resistor 24g connected to the switch _S7 of the corresponding correction circuit 23.

Next, the amplification block 2 shown by the dashed line in FIG.
The circuit configuration in which 6 is connected is shown in FIG.

In FIG. 4, 27 is a signal input terminal for inputting an audio signal from a signal source, 28 is a signal input terminal, and amplification blocks 26a, 26b...26
Each of e is an amplification block 26 in FIG. The amplification blocks 26a, 26b...26e are
Each has an amplifier 10a, 10b...10e and a bandpass filter 9a, 9b...9e, and the center frequency of the bandpass filter 9a, 9b...9e is, respectively.
f ₀ , f ₁ , ... are set to f _o . Therefore, in each amplification block 26a, 26b...26e,
Only the band components of the f ₀ band, f ₁ band, ... f _o band are amplified or attenuated. However, since each of these amplification blocks is cascade-connected, at the output point A of the first-stage amplification block 26a, an output signal in which only the _f0 band is amplified or attenuated is obtained, as shown in FIG. 5A. However, at the output point B of the next stage amplification block 26b, as shown in _{FIG .}
An output signal that is amplified or attenuated in the band is obtained, and as we proceed to the next stage,
The results of amplification and attenuation in the previous amplification blocks are mixed, and the output point C of the amplification block 26e at the final stage is output from the f0 band to the _f0 band, as shown in _FIG.
A mixed signal of all band components up to the band will be obtained.

By the way, in FIG. 4, the operation keys 16 include an operation key 16a for specifying a band and an operation key 16b for inputting switching information. Information C ₀ , C _{1 ,} . input to the decoder. Further, _the switching information C ₀ , _{C 1 , .} These multiplexers 31 and 32 automatically select signals in sequential bands and input them to the conversion circuit 20. The output of the conversion circuit 20 is detected, AD converted, and then input to the multiplexer 33. Display drive circuit 7a...
7e and indicators 8a...8e are provided corresponding to each band, and the multiplexer 33 is
It works to supply AD conversion output to the corresponding display drive circuit. Therefore, the signal strength of each band is displayed on the displays 8a...8e.

Next, FIG. 6 shows a main part of a circuit configuration in which the amplification blocks 26 of FIG. 2 are connected in parallel.

Also in FIG. 6, 26a, 26b, . . . , 26e are amplification blocks, and an audio signal from a signal source inputted via the signal input terminal 27 is commonly input to each amplification block. In the case of parallel connection, since only each band component is amplified or attenuated in each amplification block, a mixing circuit 34 is required to obtain an output signal. Note that the other configurations are exactly the same as in the case of the cascade connection shown in FIG.

By the way, in this embodiment, when the amplifier 10 does not perform any amplification or attenuation, the input signal is bypassed and the switch _S13 of the switching circuit 12 is forcibly turned on. A switch S ₇ is provided as shown by a broken line in , and the connection point of this switch S ₇ with the resistance circuit 11 is connected to the ground point P.
If it is shifted slightly, the output of the amplifier 10 will be hardly affected, and the subtracter circuit 1
Since a difference signal is obtained at 8, the signal strength can also be displayed in this case.

Also, comparing the case of connecting the amplification blocks in cascade and the case of connecting them in parallel, when they are connected in cascade, there is no need for a mixing circuit, and the amplification and attenuation of each band can be set completely independently, so there is no need to consider other bands. The advantage is that it is almost unnecessary.

(E) Effect The graphical equalizer according to the present invention is provided with an amplifier that amplifies or attenuates only each band component for each of the plurality of band filters for setting the band to be selected, and the input signal and output of this amplifier are Since we have installed an arithmetic circuit that extracts the signal difference signal,
It eliminates the need for a display band filter to display signal strength, making it ideal for IC implementation. Further, it is not necessary to adjust the band filter as in the conventional case, and the number of man-hours required for assembling the set can be reduced. Furthermore, by using a subtraction circuit, signal components outside the set band can be removed, making it possible to display the signal strength reliably.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a conventional graphic equalizer, Fig. 2 is a block diagram showing an embodiment of the graphic equalizer according to the present invention, and Fig. 3 shows the relationship between the amplification and attenuation amount T and the difference signal E ₀ . The characteristic diagram, Fig. 4 is a block diagram showing an example in which the amplification blocks of Fig. 2 are connected in cascade, and Fig. 5 A,
B and C are waveform diagrams showing waveforms of various parts in the embodiment of FIG. 4, and FIG. 6 is a main part block diagram showing an embodiment in which the amplification blocks of FIG. 2 are connected in parallel. Explanation of main drawing numbers, 2a...2n, 9, 9a, 9b
...9e...bandwidth filter, 4a...4n...bandwidth filter for display, 5a...5n, 5...detection circuit, 6
a...6n, 6...AD converter, 7a...7n...display drive circuit, 8a...8n...display device, 1,10,
10a...10e...Amplifier, 11...Resistance circuit,
12...Switching circuit, 13, 21...Decoder, 1
8... Arithmetic circuit, 20... Conversion circuit, 22... Amplifier, 23... Correction circuit, 25... Bypass switch circuit, 26 , 26a... 26e... Amplification block, 31, 32, 33... Multiplexer, 34
...Mixed circuit.

Claims (1)

[Claims] 1. In a graphic equalizer that is equipped with a plurality of band filters for setting the band to be selected and that can vary the signal strength within the band set by the band filter, only each band component is amplified or attenuated. An amplifier is provided for each of the plurality of band filters, and the difference between the input signal and the output signal of the amplifier cancels out the components outside the band, thereby reducing the difference between the band components. A graphic equalizer comprising a subtraction circuit for extracting a signal, and displaying the signal strength level of each band based on the output signal of the subtraction circuit.