JPH0417507B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a phase matching circuit for synchronizing signals,
In particular, the present invention relates to a synchronization signal phase matching circuit that can match the phase of an internal synchronization signal output from a CRT display control device to the phase of a synchronization signal output from a color television receiver.

Recently, personal computers have come to be used in ordinary households. Then, the home color television receiver was converted into a CRT.
Attempts are being made to connect a personal computer as a display device and display data from the personal computer on a color television receiver.

FIG. 1 is a schematic diagram showing a state in which a conventional personal computer is connected to a color television receiver. First, referring to FIG. 1, when data inputted from the keyboard 1 is inputted to the personal computer 2, R, G, and B signals for displaying the data on the color television receiver 3 are sent to the television circuit 31. is applied to the matrix circuit 32 included in the . And matrix circuit 3
2, R, G, and B signals are applied to a cathode ray tube 33, and characters or graphs are displayed.

By configuring the CRT display control device in this manner, images such as various characters and graphs can be displayed using the color television receiver 3 as a monitor. Furthermore, recently,
Such as displaying data from a personal computer superimposed on a color television broadcast screen.
A CRT display control device has been devised.

FIG. 2 is a schematic block diagram of such a CRT display control device. In the figure, in a color television receiver 3, a television broadcast signal is applied to a tuner 312 via an antenna 311, as is well known. Then, the video intermediate frequency signal is input from the tuner 312 to the video intermediate frequency amplifier 313. After the video signal is detected by the video intermediate frequency amplifier 313, it is applied to the cathode ray tube 33 via the video amplification circuit 314, the chroma circuit 315, and the matrix circuit 32. Further, an audio signal is extracted from the output of the video intermediate frequency amplifier 313 and is provided to a speaker 317 via an audio amplifier 316. Furthermore, a synchronization signal is extracted from the output of the video intermediate frequency amplifier 313 by a synchronization circuit 318, and a horizontal synchronization signal and a vertical synchronization signal are provided to a horizontal/vertical output circuit 320 via a horizontal/vertical drive circuit 319. The horizontal/vertical output circuit 320 provides horizontal/vertical output signals to the cathode ray tube 33 . In addition, horizontal and vertical drive circuit 3
The horizontal synchronization signal and vertical synchronization signal output from 19 are given to a counter 22 included in personal computer 2. Counter 22 counts the clock signal output from oscillation circuit 21 in synchronization with the horizontal and vertical synchronizing signals, and supplies the count value to character generator 23 as an address signal. The character generator 23 provides R, G, and B signals to the matrix circuit 32 of the color television receiver 3. Therefore, the personal computer 2 can provide the color television receiver 3 with R, G, and B signals synchronized with the horizontal and vertical synchronizing signals of the color television receiver 3.

By the way, recently, microprocessors and
A single-chip CRT controller (for example, Hitachi HD46505S) is used to connect to a CRT display and relatively easily display data on the CRT display. This CRT controller is designed to generate synchronization signals including an internal horizontal synchronization signal and an internal vertical synchronization signal based on the output of the oscillation circuit. this
When displaying data from a personal computer on a color television receiver using a CRT controller, it is necessary to match the phase of the internal synchronization signal output from the CRT controller with the phase of the synchronization signal of the color television receiver. For this purpose, it is necessary to construct a synchronization circuit using a hardware circuit, but such a synchronization phase adjustment circuit is generally complicated, has a large number of parts, and is expensive in terms of cost.

Therefore, the main object of the present invention is to provide a synchronization signal phase matching circuit that has a relatively simple configuration, can reduce the number of parts, and can match the phases of an internal synchronization signal and an external synchronization signal. It is.

In summary, this invention outputs a first gate signal according to the phase difference between an internal horizontal synchronizing signal and an external horizontal synchronizing signal based on the timing of an internal horizontal synchronizing signal by a first flip-flop, and The flip-flop outputs a second gate signal corresponding to the phase difference between the internal vertical synchronizing signal and the external vertical synchronizing signal based on the timing of the internal vertical synchronizing signal, and the first and second gate signals are output. The internal synchronization signal is synchronized with the external synchronization signal by stopping counting of a counter that generates the internal synchronization signal for a period of time.

The above objects and other objects and features of the present invention will become more apparent from the detailed description given below with reference to the drawings.

FIG. 3 is a schematic block diagram of one embodiment of the present invention. First, the configuration will be explained with reference to FIG. The oscillation circuit 11 generates clock pulses, which are applied to the dot counter 12. The dot counter 12 is composed of, for example, a 4-bit binary counter. The dot counter 12 divides the clock pulse and sends the divided output to the CRT controller 1.
Give to 3. As the CRT controller 13, for example, Hitachi HD46505S is used. This CRT
The controller 13 has the function of generating an address signal for addressing a refresh memory (not shown), a character generator (not shown), etc., and also counts the clock pulses frequency-divided by the dot counter 12 and calculates a predetermined clock pulse. It has an internal horizontal counter that generates an internal horizontal synchronizing signal when the count value reaches , and an internal vertical counter that counts this internal horizontal synchronizing signal and generates an internal vertical synchronizing signal. The internal horizontal synchronizing signal output from the CRT controller 13 is applied as a clock signal to the clock input terminals of D-type flip-flops 4 and 5. Further, the internal vertical synchronizing signal output from the CRT controller 13 is applied to the clock input terminal of the D-type flip-flop 8. As the external horizontal synchronization signal, a horizontal synchronization signal output from a color television receiver is used. This external horizontal synchronizing signal is applied to the D type flip-flop 4.
is applied to the D input terminal of the inverter 6.
The signal is inverted by and applied to the clear input terminal of the D-type flip-flop 5. The preset input terminal and clear input terminal of the D-type flip-flop 4 are limited to a high level, and the D input terminal and preset input terminal of the D-type flip-flop 5 are similarly set to a high level. Therefore, the D type flip-flop 4 is set at the timing when the external horizontal synchronizing signal is at high level and the internal horizontal synchronizing signal rises. This D type flip-flop 4 is provided for synchronizing the internal horizontal synchronizing signal with the external horizontal synchronizing signal and then synchronizing the internal vertical synchronizing signal with the external vertical synchronizing signal. Further, the D type flip-flop 5 is set at the timing of the rise of the internal horizontal synchronizing signal, is cleared when the external horizontal synchronizing signal becomes high level, and is set according to the phase difference between the internal horizontal synchronizing signal and the external horizontal synchronizing signal. The first
Outputs the gate signal. Therefore, the D type flip-flop 5 functions to synchronize the internal horizontal synchronizing signal with the external horizontal synchronizing signal.

The external vertical synchronizing signal is inverted by an inverter 7 and applied to a clear input terminal of a D-type flip-flop 8 via an AND gate 9. In addition,
The output of the D-type flip-flop 4 is similarly applied to the clear input terminal of the D-type flip-flop 8 via an AND gate 9. This D
The D input and preset input of type flip-flop 8 are set to high level. Therefore, the D-type flip-flop 8 continues to be cleared by the output of the D-type flip-flop 4 until the horizontal synchronizing signal is synchronized, and is set at the timing of the rise of the internal vertical synchronizing signal. That is, the D type flip-flop 8 outputs a second gate signal corresponding to the phase difference between the internal vertical synchronizing signal and the external vertical synchronizing signal. The first and second gate signals as the respective outputs of D-type flip-flops 5 and 8 are
It is applied to the load input terminal of the dot counter 10 via the AND gate 10. Therefore, the dot counter 12 stops counting the clock pulses output from the oscillation circuit 11 while the first and second gate signals are applied.

FIG. 4 is a time chart for explaining the operation of FIG. 3, and FIG. 4 a to h are enlarged views of the time axis of period T in a' to h'. The operation shown in FIG. 3 will be explained with reference to FIG.
As shown in Figure 4a, the external horizontal synchronizing signal has a low level synchronizing signal part, and the internal horizontal synchronizing signal has a high level synchronizing signal part as shown in Figure 4b, and the internal horizontal synchronizing signal has a low level as shown in Figure 4b. Since the period is shorter than that of the horizontal synchronization signal, the synchronization of each horizontal synchronization signal does not match.

The D-type flip-flop 4 sets the state of the external horizontal synchronizing signal based on the rising timing of the internal horizontal synchronizing signal. In other words, if the external horizontal synchronization signal is at high level at the timing when the internal horizontal synchronization signal rises to high level, D
The output of the type flip-flop 4 becomes low level as shown in FIG. 4c. Since this low level signal is applied to the clear input terminal of the D type flip-flop 8 via the AND gate 9, the D type flip flop 8 is reset and its output is at a high level.

On the other hand, the D type flip-flop 5 is set at the rising edge of the internal horizontal synchronizing signal and cleared when the external horizontal synchronizing signal becomes high level. Therefore, as shown in FIG. 4d, the first gate signal which becomes low level only during the phase shift between the internal horizontal synchronizing signal and the external horizontal synchronizing signal is generated from the output of the D type flip-flop. This first gate signal is applied to a dot counter 12 via an AND gate 10. Therefore, the dot counter 12 stops counting the clock pulses output from the oscillation circuit 11 only while the first gate signal is at a low level, and when the first gate signal goes from a low level to a high level, it continues counting for a certain period of time. count the clock pulses.

The internal horizontal counter of the CRT controller 13 is
The counting output of the dot counter 12 is counted, and an internal horizontal synchronizing signal synchronized with the external horizontal synchronizing signal is output as shown in FIG. 4b. When the dot counter 12 stops counting clock pulses, the CRT controller 13 also stops the internal horizontal counter and maintains the level of the internal horizontal synchronizing signal. Additionally, the internal vertical counter of the CRT controller 13 counts the internal horizontal synchronization signal and maintains its level once the internal horizontal counter stops counting. Then, when the first gate signal becomes high level, the dot counter 12 restarts counting clock pulses, and the internal horizontal counter of the CRT controller 13 restarts the counting operation.
When the internal horizontal synchronization signal begins to be generated, the operation of the internal vertical counter is also restarted.

When the internal horizontal synchronizing signal is synchronized with the external horizontal synchronizing signal, the output of the D-type flip-flop 4 becomes high level, as shown in FIG. 4c. Then, the D type flip-flop 8 becomes the fourth
It is set based on the rising timing of the internal vertical synchronizing signal shown in FIG. 4 f', and is cleared when the external vertical synchronizing signal shown in FIG. 4 e' becomes high level.
Therefore, as shown in FIG. 4g', the second gate signal that becomes low level only during the phase shift between the internal vertical synchronizing signal and the external vertical synchronizing signal is output from the D-type flip-flop 8. be done. This second
The gate signal is applied to the dot counter 12 via the AND gate 10. Dot counter 1
2 stops counting the clock pulses from the oscillation circuit 11 only during the period when this second gate signal is at a low level. Therefore, an internal vertical synchronizing signal synchronized with the external vertical synchronizing signal appears at the output of the AND gate 10, as shown in FIG. 4h'.

In addition, during the synchronization period of the external vertical synchronization signal,
When the operation of the CRT controller 13 is stopped by the second gate signal corresponding to the phase difference between the internal vertical synchronizing signal and the external vertical synchronizing signal, the internal horizontal synchronizing signal remains at its level during that period, and the signal does not appear in the normal cycle. does not operate, but this is limited to the vertical retrace period, so it does not cause any problems as a synchronizing signal to be sent to the CRT. Furthermore, when the dot counter 12 is stopped by the first gate signal corresponding to the phase difference between the internal horizontal synchronizing signal and the external horizontal synchronizing signal during the synchronization period of the external horizontal synchronizing signal, the operation of the internal horizontal counter is stopped within the CRT controller 13. Since the internal vertical counter also stops, the vertical synchronization signal also maintains its level during this period, but this is small compared to the vertical synchronization period and is not at a level that would impair its original function. , there will be no problem as a vertical synchronizing signal to be sent to a CRT.

As described above, according to the present invention, the first flip-flop generates the first gate signal according to the phase difference between the internal horizontal synchronizing signal and the external horizontal synchronizing signal, and the second flip-flop generates the first gate signal according to the phase difference between the internal horizontal synchronizing signal and the external horizontal synchronizing signal. A second gate signal is generated according to the phase difference between the external vertical synchronization signal and the internal vertical synchronization signal, and the first and second gate signals are
Since the counter is configured to stop counting while the gate signal is being generated, the internal synchronization signal can be synchronized with the external synchronization signal with a relatively simple configuration.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram showing a state in which a conventional personal computer is connected to a color television receiver. FIG. 2 is a schematic block diagram of a CRT display control device that displays data from a personal computer superimposed on a color television broadcast screen. FIG. 3 is a detailed block diagram of one embodiment of the present invention. FIG. 4 is a time chart for explaining the operation of each part in FIG. 3. In the figure, 4, 5, 8 are D type flip-flops, 6, 7 are inverters, 9, 10 are AND
11 is an oscillation circuit, 12 is a dot counter, and 13 is a CRT controller.

Claims (1)

[Claims] 1. An oscillation circuit that generates clock pulses, a counter that counts clock pulses from the oscillation circuit and generates an output obtained by dividing the frequency of the clock pulse, and an internal horizontal counter that receives the frequency-divided output from the counter. a CRT controller that counts the internal horizontal sync signal and generates an internal horizontal sync signal, and counts the internal horizontal sync signal with an internal vertical counter to generate an internal vertical sync signal, the internal horizontal sync signal and the internal vertical sync signal respectively. A synchronization signal phase adjustment circuit for matching the phases of an external horizontal synchronization signal and an external vertical synchronization signal, the circuit receiving the internal horizontal synchronization signal as a clock signal and the external horizontal synchronization signal as a clear signal, and adjusting the phase of the internal horizontal synchronization signal. A first gate signal that outputs a first gate signal corresponding to a phase difference between a leading edge of the internal horizontal synchronizing signal and a trailing edge of the external horizontal synchronizing signal during a synchronization period of the external horizontal synchronizing signal, based on the timing of the signal. a flip-flop, which receives the internal vertical synchronization signal as a clock signal and the external vertical synchronization signal as a clear signal, and controls the internal vertical synchronization signal during the synchronization period of the external vertical synchronization signal based on the timing of the internal vertical synchronization signal; a second flip-flop that outputs a second gate signal according to a phase difference between a leading edge and a trailing edge of the external vertical synchronization signal; and during periods of the first and second gate signals;
A phase adjustment circuit for synchronizing signals, comprising means for stopping counting of the output of the oscillation circuit by the counter.