JPH0417592B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a color demodulation circuit that digitally directly separates two orthogonal components of a color signal from an NTSC composite video signal.

[Prior art] Figure 1 shows NTSC, which is commonly thought of in the past.
1 is a schematic block diagram showing a digital color demodulation circuit for a composite video signal; FIG. In the figure, the composite video signal is applied to terminal 1. A/D converter 2 performs analog/digital conversion of the composite video signal under the control of clock pulse C1 from clock pulse generation circuit 8. The digitized composite video signal is separated into a luminance signal and a color signal in a color signal separation circuit 3. The color signal separation circuit 3 generally uses a comb filter. The separated color signals are applied to buffers 4 and 5. Buffer 4 provides a color signal to output terminal 6 in response to clock signal C2 from clock pulse generation circuit 8. On the other hand, buffer 5 provides a color signal to output terminal 7 in response to clock signal C3 from clock pulse generation circuit 8.

The clock pulse C1 has a repetition frequency four times that of the color subcarrier, and is phase-controlled so that its rising edge coincides with the zero phase of the color burst. Clock pulse C2 has a repetition frequency equal to the color subcarrier and 180° of the color burst.
The phase is controlled so that the rising edges coincide with each other. Further, the clock pulse C3 has the same repetition frequency as the clock pulse C2, and is phase-controlled so that it lags the clock pulse C2 by 90 degrees in phase. Figure 2 shows the color burst and these clock pulses C1, C2 and C3.
FIG. 2 is a timing diagram showing the relationship between Under the control of these clock pulses, two orthogonal components of a color signal are output to terminals 6 and 7 in FIG. 1 through the following operations.

In operation, the composite video signal applied to terminal 1 is converted from an analog signal to a digital signal in A/D converter 2 at the instant of rising of clock pulse C1. Next, the color signal components separated in the color signal separation circuit 3 are transferred to the buffer 4.
and 5. As mentioned above, the phase of the clock pulse C1 is controlled so that the pulse rises at the zero phase of the color burst, so that the color signal component output from the color signal separation circuit 3 is as follows at the moment when the clock pulses C2 and C3 rise. These are the two orthogonal components of the color signal. Buffers 4 and 5 are each clock pulse C2
And at the instant when C3 rises, output terminal 6
Since the color signal is outputted to the output terminals 6 and 7, two orthogonal components of the color signal are obtained as digital signals at the output terminals 6 and 7.

Since the conventional digital color demodulation circuit is configured as described above, only the value of the orthogonal component of the color signal for each period of the color subcarrier is detected. As described above, the conventionally considered digital color demodulation circuit has a drawback that the demodulation cycle is long, and therefore it is difficult to perform digital RGB matrix processing.

[Summary of the Invention] Therefore, an object of the present invention is to shorten the period of demodulation of two orthogonal components of a color signal.
An object of the present invention is to provide a color signal demodulation circuit that can easily perform digital RGB matrix processing.

According to the present invention, the NTSC composite video signal has a repetition frequency four times that of the color subcarrier and is sampled corresponding to the zero phase, 90° phase, 180° phase, and 270° phase of the color burst. The sample is sampled at a phase-controlled sampling frequency so that the point position exists. The color signal is separated from the sampled composite video signal to provide a sample value sequence of the color signal. Among the sample value series, the signs of the sample values corresponding to the 180° phase and the 270° phase of the color burst are inverted. The partially sign-inverted sample value sequence is applied to a digital filter. The digital filter performs an interpolation operation on each of the two orthogonal components in the sample value series using the sample values before and after each fixed period determined by the repetition frequency twice the color subcarrier. Accordingly, the low-frequency components of each of the two orthogonal components of the color signal are output at each period determined by the sampling frequency. The output of the digital filter is switched at the sampling frequency, so that two orthogonal components of the color signal are output in parallel.

[Embodiment of the invention] Figure 3 shows a preferred embodiment of the invention.
1 is a schematic block diagram showing an NTSC digital color demodulation circuit; FIG. In the figure, the voltage applied to input terminal 1 is
The NTSC composite video signal is supplied to the A/D converter 2. The A/D converter 2 responds to the clock pulse C4 from the clock pulse generating circuit 8 and converts the applied NTSC composite video signal from an analog signal to a digital signal. The composite video signal sampled in this manner is provided to the color signal separation circuit 3. The chrominance signal separation circuit 3 separates the sampled composite video signal into a luminance signal and a chrominance signal, and supplies only the sampled value sequence of the chrominance signal to the sign inverter 10 . For example, a comb filter may be used in the color signal separation circuit 3. The sign inverter 10 receives the clock pulse F from the clock pulse generating circuit 8.
1, the sign of the sample value in the sample value series of the color signal is inverted.

The sample value sequence of the color signal from the sign inverter 10 is
It is applied to a digital filter consisting of delay circuits 11-14, adders 15-17, and arithmetic circuits 18-21. Delay circuits 11 to 14 have a delay time equal to one sampling period. Arithmetic circuit 18~
21 performs an operation to halve the applied signal. This arithmetic circuit can be configured with a shift register, for example.

The sample value sequence of the color signal from the sign inverter 10 is
Provided to delay circuit 11 and arithmetic circuit 18.
The output of delay circuit 11 is given to one input of delay circuit 12 and adder 16. The output of the arithmetic circuit 18 is given to one input of the adder 15. The output of delay circuit 12 is applied to the other input of adder 15 and delay circuit 13 . The output of the delay circuit 13 is connected to the other input of the adder 16 and the delay circuit 14.
given to. The output of the delay circuit 14 is applied to one input of the adder 17 via the arithmetic circuit 19. The output of the adder 15 is given to the other input of the adder 17 . The output of the adder 17 is sent to one input 23 of the switch circuit 22 via the arithmetic circuit 20.
given to. Further, the output of the adder 16 is applied to the other input 24 of the switch circuit 22 via the arithmetic circuit 21. The switch circuit 22 responds to the clock pulse F2 from the clock pulse generation circuit 8 by switching the signals (two orthogonal components of the color signal) applied to both inputs 23 and 24, so that the two outputs 25 and 26 output the color signal. Two orthogonal components of the signal are separated and output. The two orthogonal components of the color signal separated in this way are taken out from output terminals 6 and 7.

FIG. 4 shows the clock pulses C4, F1 and F2 invented in the clock pulse generating circuit 8.
FIG. 3 is a timing diagram showing the timing for color bursts of FIG. The clock pulse C4 applied to the A/D converter 2 has a repetition frequency four times that of the color subcarrier, and is phase-controlled so that its rising edge coincides with the zero phase of the color burst. The clock pulse F1 given to the sign inverter 10 is
It has a repetition frequency equal to the color subcarrier and has a logic value of 1 at zero phase and at 90° phase of the color burst.
with 180° phase of color burst and 270°
The phase is controlled to have a logical value of 0 at the phase. The clock pulse F2 applied to the switch circuit 22 has a repetition frequency twice that of the color subcarrier, and has a logic value of 1 at the zero phase of the color burst.
has a logical value of 0 at the 90° phase of the color burst.
The phase is controlled so that it has .

Next, the operation of the NTSC digital color demodulation circuit shown in FIG. 3 will be explained. The composite video signal applied to the input terminal 1 is converted from an analog signal to a digital signal in the A/D converter 2 at the instant when the clock pulse C4 rises. The composite video signal sampled in this manner is applied to the color signal separation circuit 3, where the color signal components are separated and a sample value sequence of the color signal is obtained. Clock pulse C4 is used at zero phase of color burst, at 90° phase, at 180° phase,
Since the phase is controlled so that the rising edges coincide at the 270° phase, the digital color signal extracted by the above operation is a repetition of two orthogonal components, ignoring the sign. That is, in the A/D converter 2, the color signal sampled at the zero phase of the color burst is "-(red difference signal)",
The color signal sampled during the 90° phase of the color burst is "-(blue difference signal)", and the color signal sampled during the 180° phase of the color burst is the "red difference signal", which is the color signal sampled during the 180° phase of the color burst. The color signal sampled at the 270° phase is the "blue difference signal."

The sample value sequence of the color signal outputted from the color signal separation circuit 3 is sign-inverted in the sign inverter 10 only when the clock pulse F1 is "1". As mentioned above, the clock pulse F1 has a logical value of 1 at the zero phase and at the 90° phase of the color burst, so the sample value series of the color signal output from the sign inverter 10 has a frequency twice that of the color subcarrier. It consists of digital values of a ``red difference signal'' and a ``blue difference signal'' that are repeated alternately at a period determined by .

This color signal sample value sequence is supplied to the input portions of the delay circuit 11 and the arithmetic circuit 18, respectively.
Delay circuits 11-14, adders 15-17, and arithmetic circuits 18-21 constitute a digital filter, which performs the following operations on a sample value series of a given color signal. In other words, the switch circuit 22
One of the input sections 23 of is inputted from the sample value S ₀ , the sample value S ₂ from two samples ago, and the sample value S ₄ from four samples ago, using the following formula (S ₀ +2S ₂ +S ₄ )/4...(1 ) is supplied. In addition, the other input section ₂₄ of the switch circuit 22 receives the sample value S ₁ one sample before the sample value and the sample value S _{3 three samples} before the sample value as follows. The value calculated by is supplied.

In equation (1), sample values S ₀ , S ₄ and sample value S ₂ have a phase difference of 180°, and in equation (2), sample value S ₁
Since the phase differs by 180° from the sample value _S3 , the high frequency components are canceled and removed in each equation. That is, a "red difference signal" and a "blue difference signal" from which high frequency components have been removed are alternately supplied to one input section 23 of the switch circuit 22 at a period determined by twice the frequency of the color subcarrier. The "blue difference signal" and the "red difference signal" interpolated from the previous and subsequent values are alternately supplied to the other input section 24 of the switch circuit 22 at the above-mentioned period.

The switch circuit 22 connects the output parts 25 and 26 to the input parts 23 and 24, respectively, when the clock pulse F2 is "1", and connects the output parts 25 and 26 to the input parts 24 and 24, respectively, when the clock pulse F2 is "0". Switch to 23. Therefore, the "red difference signal" is always output to the output section 25 of the switch circuit 22, and the "blue difference signal" is always output to the output section 26. In this way, each of the two orthogonal components of the color signal, the "red difference signal" and the "blue difference signal", is transmitted from output terminals 6 and 7 at a period determined by four times the frequency of the color subcarrier. Separated and taken out.

Note that in the above description, for the sake of simplicity, time delays in signal propagation occurring in the color signal separation circuit 3 and the like have been ignored.

Further, in the above embodiment, the digital filter includes delay circuits 11 to 14, adders 15 to 17,
and arithmetic circuits 18 to 21, but the circuit is not limited to the illustrated circuit as long as it can function as a reduction filter. Also, even if the interpolation calculation function is not provided, two orthogonal components of the color signal can be extracted at twice the period of the conventional method, but by providing the interpolation calculation function,
As described above, it is possible to extract two orthogonal components of the color signal at a period four times as long as in the conventional method.

[Effects of the Invention] As described above, according to the present invention, the period of detection of two orthogonal components of a color signal is shortened, so that digital RGB matrixing can be easily performed. At the same time, since high-frequency components of the signal are removed, high-frequency noise is removed, and a smooth demodulated output can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional NTSC digital color demodulation circuit, FIG. 2 is a timing diagram of clock pulses used in the circuit of FIG. 1, and FIG. 3 is a NTSC digital color demodulation circuit according to a preferred embodiment of the present invention. FIG. 4 is a block diagram showing the circuit, and FIG. 4 shows a timing diagram of the clock pulses used in the circuit of FIG. In the figure, 1 is a composite video signal input terminal, 2 is an A/D converter, 3 is a color signal separation circuit, 4 and 5 are buffers, 6 and 7 are output terminals, 8 is a clock pulse generation circuit, and 10 is a sign inverter. , 11-14 are delay circuits, 15-17 are adders, 18-21 are arithmetic circuits, and 22 is a switch circuit, respectively.

Claims (1)

[Scope of Claims] 1. A color demodulation circuit that receives an NTSC composite video signal and digitally extracts two orthogonal components of a color signal from the composite video signal, the circuit having a repetition frequency four times as high as the color subcarrier. In addition, the composite video signal is sampled at a phase-controlled sampling frequency such that sample point positions exist corresponding to the zero phase, 90° phase, 180° phase, and 270° phase of the color burst. means for separating a color signal from the sampled composite video signal to provide a sample value series of the color signal; receiving the sample value series of the color signal; at zero phase and 90°
means for inverting the sign of a corresponding sample value at a phase time; By performing an interpolation operation using the sample values before and after each determined period, the low frequency components of each of the two orthogonal components of the color signal are outputted at each period determined by the sampling frequency. and means for outputting two orthogonal components of the color signal in parallel by switching the output of the digital filter at the sampling frequency.
NTSC digital color demodulation circuit.