JPH0418468B2 - - Google Patents
Info
- Publication number
- JPH0418468B2 JPH0418468B2 JP60245113A JP24511385A JPH0418468B2 JP H0418468 B2 JPH0418468 B2 JP H0418468B2 JP 60245113 A JP60245113 A JP 60245113A JP 24511385 A JP24511385 A JP 24511385A JP H0418468 B2 JPH0418468 B2 JP H0418468B2
- Authority
- JP
- Japan
- Prior art keywords
- case
- corners
- silicone gel
- semiconductor device
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
- H10W76/40—Fillings or auxiliary members in containers, e.g. centering rings
- H10W76/42—Fillings
- H10W76/47—Solid or gel fillings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/547—Dispositions of multiple bond wires
- H10W72/5473—Dispositions of multiple bond wires multiple bond wires connected to a common bond pad
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5524—Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/921—Structures or relative sizes of bond pads
- H10W72/926—Multiple bond pads having different sizes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/932—Plan-view shape, i.e. in top view
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置に関し、とりわけ樹脂
封止形半導体装置のケースの改良に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor devices, and particularly to improvements in the case of resin-sealed semiconductor devices.
第４図は、従来の半導体モジユールの平面図で
あり、ここでは、１素子入り電力用半導体モジユ
ールを例にして示している。図において、１はベ
ース板、２はケース、３は絶縁基板、４はベース
電極、５はエミツタ電極、６はモリブデン板、７
はシリコンチツプ、８はベースアルミニウムワイ
ヤ、９はエミツタアルミニウムワイヤである。
FIG. 4 is a plan view of a conventional semiconductor module, and here a one-element power semiconductor module is shown as an example. In the figure, 1 is a base plate, 2 is a case, 3 is an insulating substrate, 4 is a base electrode, 5 is an emitter electrode, 6 is a molybdenum plate, and 7
8 is a silicon chip, 8 is a base aluminum wire, and 9 is an emitter aluminum wire.
第５図は、第４図の断面図であり、ベース、エ
ミツタアルミニウムワイヤ８，９をアルミニウム
ワイヤホンデイングし、ケース２を接着剤でベー
ス板１に接着した後、シリコーンゲル１０の注入
を行い、キユアー後にエポキシ樹脂１１を注入
し、キユアーを行う。 FIG. 5 is a cross-sectional view of FIG. 4, in which the base and emitter aluminum wires 8 and 9 are bonded with aluminum wire, the case 2 is bonded to the base plate 1 with adhesive, and then silicone gel 10 is injected. After curing, epoxy resin 11 is injected and curing is performed.
従来の半導体装置は、以上のように構成されて
おり、ケース２接着後、シリコンゲル１０を注入
すると、表面張力によつてケース４隅からシリコ
ンゲルがはい上がり、このため次のエポキシ樹脂
を注入した時に、ケースの４隅においてケースと
エポキシ樹脂の接着が悪くなるという問題点があ
つた。
A conventional semiconductor device is constructed as described above, and when the silicone gel 10 is injected after bonding the case 2, the silicone gel crawls up from the four corners of the case due to surface tension, which prevents the injection of the next epoxy resin. When doing so, there was a problem that the adhesion between the case and the epoxy resin deteriorated at the four corners of the case.
この発明は、上記のような問題点を解決するた
めになされたもので、ゲルのはい上がりを防止で
きる半導体装置を提供することを目的とする。 The present invention was made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor device that can prevent gel from creeping up.
この発明に係る半導体装置は、ケースの４隅の
中間高さ位置にリブを設けた、あるいは該リブを
設けるとともにケースの４隅のＲ（アール）部を
設けたものである。
The semiconductor device according to the present invention is provided with ribs at intermediate height positions at the four corners of the case, or is provided with ribs and R portions at the four corners of the case.
この発明においては、ケースの４隅の中間高さ
位置にリブを設けるか、あるいは該リブを設ける
とともにケースの４隅にＲ（アール）部を設けた
から、ゲルのはい上がりはほとんど発生しない。
In this invention, since ribs are provided at intermediate height positions at the four corners of the case, or because the ribs are provided and R portions are provided at the four corners of the case, hardly any gel creeping occurs.
以下、この発明の実施例を図について説明す
る。
Embodiments of the present invention will be described below with reference to the drawings.
第１図、第２図は本発明の一実施例の前提とな
る半導体装置を示す平面図およびそのケース部分
の詳細を示す断面図である。図中、第４図、第５
図と同一符号は同一部分を示す。第２図におい
て、２０はケースの４隅に上から下まで同じ形状
に形成したＲ（アール）部である。第３図におい
て、３０はＲ（アール）部２０の中間に設けたリ
ブである。 FIGS. 1 and 2 are a plan view showing a semiconductor device, which is the premise of an embodiment of the present invention, and a sectional view showing details of its case portion. In the figure, Figures 4 and 5
The same reference numerals as in the figure indicate the same parts. In FIG. 2, reference numeral 20 indicates R portions formed in the same shape from top to bottom at the four corners of the case. In FIG. 3, 30 is a rib provided in the middle of the R (R) portion 20. As shown in FIG.
第１図において、ベース板１上に絶縁基板３と
エミツタ電極４、ベース電極５を載せ、それらと
は別にベース板１の上に、あらかじめモリブデン
板６の上に高温ハンダ付けされたシリコンチツプ
７を載せ、同時に定温ハンダによりハンダ付けす
る。続いてベース、エミツタのアルミニウムワイ
ヤ８，９のボンデイングを行い、ケース２を接着
剤でベース板１に貼付けた後、チツプとアルミニ
ウム保護のためシリコンゲル１０を注入する。こ
のときケース２の４隅の内側をＲ（アール）にし
ていない場合は、上記従来装置のようにシリコン
ゲルの表面張力により、ケース２の上部にまでシ
リコンゲル１０がはい上がり、その後エポキシ樹
脂による封止のときにケース２とエポキシ樹脂１
１との接着が悪くなり、耐湿に関しても悪い結果
となることとなるが、このようにＲ部を設けたこ
とによりこの問題は完全に解消される。 In FIG. 1, an insulating substrate 3, an emitter electrode 4, and a base electrode 5 are placed on a base plate 1, and in addition to these, a silicon chip 7 is placed on the base plate 1 and is previously soldered at high temperature onto a molybdenum plate 6. , and solder at the same time using constant temperature soldering. Next, the aluminum wires 8 and 9 of the base and emitter are bonded, and the case 2 is attached to the base plate 1 with adhesive, and then silicone gel 10 is injected to protect the chip and aluminum. At this time, if the inside of the four corners of the case 2 are not rounded, the surface tension of the silicone gel causes the silicone gel 10 to crawl up to the top of the case 2, as in the conventional device described above, and then the epoxy resin When sealing, case 2 and epoxy resin 1
The adhesion with No. 1 will be poor, and the moisture resistance will also be poor, but by providing the R portion in this manner, this problem is completely resolved.
また、第３図は本発明の一実施例による半導体
装置を示し、これは、第４図に示すような４隅が
角になつているケースの中間高さ位置にリブ３０
を設けたものである。 Further, FIG. 3 shows a semiconductor device according to an embodiment of the present invention, in which a rib 30 is provided at an intermediate height position of a case having four corners as shown in FIG.
It has been established.
次に作用効果について説明する。 Next, the effects will be explained.
この発明の実施例によれば、エポキシ樹脂の這
い上がりが発生しやすいケースの４隅の中間高さ
位置にリブ３０を設けるようにしており、これに
より、樹脂の這い上がりが発生してもリブ３０の
ところで確実に這い上がりを止めることができ
る。 According to the embodiment of the present invention, the ribs 30 are provided at intermediate height positions at the four corners of the case where epoxy resin tends to creep up. You can definitely stop climbing at 30.
また、この実施例はリブを設けた４隅に第１
図、第２図に示すようなアールを持たせているの
で、より一層の這い上がり防止効果を得ることが
できる。 In addition, in this embodiment, first ribs are provided at the four corners.
Since it has a radius as shown in Fig. 2, it is possible to obtain a further effect of preventing creeping up.
なお、上記アール部あるいはリブはケース成形
時に同時に加工すれば、ケースの価格の上昇を招
くことはない。 Note that if the rounded portion or rib is processed at the same time as the case is molded, the price of the case will not increase.
また、上記各実施例では、１素子入りトランジ
スタモジユールの場合について説明したが、本発
明は多素子入り電力モジユールの樹脂封止形ケー
スにも適用でき、同様の効果を奏する。 Further, in each of the above embodiments, the case of a single-element transistor module has been described, but the present invention can also be applied to a resin-sealed case of a multi-element power module, and similar effects can be obtained.
以上のように、この発明に係る半導体装置によ
れば、ケースの４隅の中間高さ位置にリブを設け
るか、あるいはこのリブを設けたケースの４隅に
Ｒ（アール）部を設けるようにしたので、ゲルの
はい上がりを防止でき、ケースとエポキシ樹脂と
の接着が良好となる効果がある。
As described above, according to the semiconductor device according to the present invention, ribs are provided at intermediate height positions at the four corners of the case, or R portions are provided at the four corners of the case where the ribs are provided. This has the effect of preventing the gel from creeping up and improving the adhesion between the case and the epoxy resin.
第１図および第２図は本発明の第２の実施例に
よる半導体装置のコーナを示す平面図および断面
図、第３図は本発明の他の実施例のケースの断面
図、第４図および第５図は従来の半導体装置の平
面図および断面図である。
１はベース板、２はケース、３は絶縁基板、４
はエミツタ電極、５はベース電極、６はモリブデ
ン板、７はシリコンチツプ、８はベースアルミニ
ウムワイヤ、９はエミツタアルミニウムワイヤ、
２０はＲ（アール）部、３０ははリブ。
なお図中同一符号は同一又は相当部分を示す。
1 and 2 are a plan view and a cross-sectional view showing a corner of a semiconductor device according to a second embodiment of the present invention, FIG. 3 is a cross-sectional view of a case of another embodiment of the present invention, and FIG. FIG. 5 is a plan view and a cross-sectional view of a conventional semiconductor device. 1 is a base plate, 2 is a case, 3 is an insulating board, 4
is an emitter electrode, 5 is a base electrode, 6 is a molybdenum plate, 7 is a silicon chip, 8 is a base aluminum wire, 9 is an emitter aluminum wire,
20 is the R part, and 30 is the rib. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
け、その上に電極板、半導体チツプを順次ハンダ
付けしこれをケースに収容してシリコーンゲル及
び樹脂を用いて樹脂封止を行う半導体装置におい
て、 上記ケースの４隅内面の中間高さ位置にその表
面から突出して設けたリブからなる、上記シリコ
ーンゲルのはい上がり防止部を設けたことを特徴
とする半導体装置。 ２ 上記ケースの４隅にアール部を設けてなるこ
とを特徴とする特許請求の範囲第１項記載の半導
体装置。[Claims] 1. An insulating layer or an insulating substrate is provided on a metal base plate, an electrode plate and a semiconductor chip are sequentially soldered thereon, and this is housed in a case and resin-sealed using silicone gel and resin. A semiconductor device characterized in that the silicone gel creep-up prevention portion is provided at an intermediate height position on the inner surface of the four corners of the case, the silicone gel crawling prevention portion consisting of a rib protruding from the surface of the case. 2. The semiconductor device according to claim 1, wherein the case has rounded portions at four corners.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60245113A JPS62104145A (en) | 1985-10-31 | 1985-10-31 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60245113A JPS62104145A (en) | 1985-10-31 | 1985-10-31 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62104145A JPS62104145A (en) | 1987-05-14 |
| JPH0418468B2 true JPH0418468B2 (en) | 1992-03-27 |
Family
ID=17128814
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60245113A Granted JPS62104145A (en) | 1985-10-31 | 1985-10-31 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62104145A (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3638746B2 (en) * | 1997-01-30 | 2005-04-13 | 東レ・ダウコーニング・シリコーン株式会社 | Silicone gel composition and silicone gel for sealing and filling electric and electronic parts |
| JP3765444B2 (en) * | 1997-07-10 | 2006-04-12 | 東レ・ダウコーニング株式会社 | Silicone gel composition and silicone gel for sealing and filling electric and electronic parts |
| JP4081611B2 (en) * | 2003-11-19 | 2008-04-30 | 株式会社豊田自動織機 | Semiconductor device |
| CN106103594B (en) | 2014-01-27 | 2019-06-28 | 陶氏东丽株式会社 | Silicone Gel Composition |
| CN109661436A (en) | 2016-09-26 | 2019-04-19 | 道康宁东丽株式会社 | Curing reactive silicone gel and its use |
| JP6728374B2 (en) | 2016-09-26 | 2020-07-22 | デュポン・東レ・スペシャルティ・マテリアル株式会社 | Laminated body, manufacturing method thereof, and manufacturing method of electronic component |
| US10961419B2 (en) | 2016-10-31 | 2021-03-30 | Dow Toray Co., Ltd. | Layered body and method for manufacturing electronic component |
| CN110446766A (en) | 2017-04-06 | 2019-11-12 | 陶氏东丽株式会社 | Liquid curable silicone adhesive composition, its cured product and its use |
| EP3683246B1 (en) | 2017-09-11 | 2024-10-02 | Dow Corning Toray Co., Ltd. | Cured silicone elastomer having radical reactivity and use of same |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56167552U (en) * | 1980-05-15 | 1981-12-11 | ||
| JPS58121652A (en) * | 1981-12-11 | 1983-07-20 | Fuji Electric Co Ltd | Hybrid integrated circuit device |
-
1985
- 1985-10-31 JP JP60245113A patent/JPS62104145A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62104145A (en) | 1987-05-14 |
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