JPH0418692B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Application) The present invention relates to a semiconductor device, and particularly to a high voltage semiconductor device suitable for achieving high reliability.

(Prior Art) FIG. 1 is a cross-sectional view of a conventional high voltage PNP transistor. For high voltage ICs, the field plate structure is used as a method to achieve high voltage resistance because the manufacturing process is simple.
Widely used.

Hereinafter, a conventional field plate structure will be explained with reference to FIG.

In the figure, 1 is an emitter electrode, 2 is a collector electrode, 3, 4, and 5 are p emitter regions, and n
They are a base region and a p collector region. 6 and 7
are emitter junction and collector junction, respectively.

Further, each of the electrodes 1 and 2 is provided along the surface of the passivation film 8, and extends beyond the emitter junction 6 and the collector junction 7 onto the n-base region 4 by a length l. As is well known, this projecting portion functions as a field plate.

For example, if the field plate 2 is not provided, a depletion layer is formed as shown by the dotted line 9, and the electric field is concentrated near the surface of the collector junction 7, resulting in a significant drop in breakdown voltage.

On the other hand, if the collector electrode 2 has a structure with a field plate of length l as shown in the figure, the depletion layer will spread as shown by the dotted line 10, and the depletion layer will spread near the surface of the collector junction 7. Since the concentration of electric field at

By the way, during the operation of the transistor shown in FIG. 1, a voltage higher than the voltage of the collector electrode 2 is applied to the emitter electrode 1 and the n-base region 4, and the potential of the emitter electrode 1 is The potential may be higher than that of

If such a state continues for a long time, as shown in FIG.
It is attracted to the vicinity of the interface directly under the field plate of the emitter electrode 1, and the passivation film 8
The negative charges inside are also attracted to the emitter electrode 1 side.

Therefore, the depletion layer 10 extends directly below the field plate of the emitter electrode 1, as indicated by the dotted line 11. However, in this case, negative charges 1 induced on the surface of the n-base region 4 by the electric field of the field plate of the emitter electrode 1
2 (indicated in the figure), the extension of the depletion layer is prevented. Therefore, a decrease in breakdown voltage is prevented.

If the emitter electrode 1 does not have a field plate, there is nothing to prevent the depletion layer from extending, so a channel will eventually be formed between it and the p emitter region 3. Needless to say, this increases leakage current and causes a significant drop in breakdown voltage.

In this way, the reliability of the breakdown voltage can be improved by the electric field effect of the field plate of the emitter electrode 1. This reliability can be further increased by increasing the length of the field plate.

However, as is clear, this method also
This is a problem from the point of view of higher integration of ICs as the element area increases.

(Objective) An object of the present invention is to provide a highly integrated semiconductor device that can solve the above-mentioned problems, suppress an increase in leakage current, and improve the reliability of withstand voltage.

(Summary) The present invention enhances the electric field effect exerted on the semiconductor substrate from the tip of the field plate without increasing the length of the field plate on the emitter electrode side, thereby reducing carriers on the surface of the n-base region. It enhances the accumulation phenomenon and improves the ability to block channel entry.

Hereinafter, the present invention will be described in detail based on specific embodiments shown in the accompanying drawings.

FIG. 2 is a sectional view of the first embodiment of the present invention.

In the figure, 1 and 2 are a p-emitter electrode and a p-collector electrode, respectively, and 3, 4, and 5 are p-emitter, n-base, and p-collector regions, respectively. Also, 8 is a passivation film, 6, 7
are emitter junction and collector junction, respectively.

Note that typical numerical examples of this embodiment are as follows. The junction depth of both the p emitter region 3 and the p collector region 5 is about 10 μm. The p emitter electrode 1 and the p collector electrode 2 have an emitter junction 6 and a collector junction 7 of 20 μm and 30 μm, respectively.
It extends beyond m and extends onto the n base region 4.

The feature of this embodiment is that the thickness of the passivation film 8 interposed between the collector electrode 2 and the surface of the n-base region 4 is 2.5 μm, whereas the thickness of the passivation film 8 interposed between the collector electrode 2 and the surface of the n-base region 4 is 2.5 μm, whereas The thickness of the intervening passivation film 8 is 0.8 μm, which is approximately 1/3 as thin as 0.8 μm.

The amount of charge accumulated on the n-base surface due to the electric field effect of the emitter electrode 1 is proportional to the product of the length l of the field plate and the electric field strength generated by this electrode.

As mentioned above, the thickness of the passivation film 8 is
By decreasing from 2.5 μm to 0.8 μm, the electric field strength increases approximately three times. Therefore, the amount of accumulated charge on the n-base surface increases, and the reliability of breakdown voltage is significantly improved.

As is clear from the above, the same effect as above can also be obtained by tripling the length l of the field plate of the emitter electrode 1 in Fig. 1, but in this case, the element area increases,
It becomes impossible to achieve high integration.

FIG. 3 is a plan view of a pnp transistor designed based on the embodiment shown in FIG. 2 above. In the figure, the same reference numerals as in FIG. 2 represent the same or equivalent parts.

In addition, the numbers outside the parentheses in the drawings are the dimensions when designed according to this embodiment, while the numbers inside the parentheses are the lengths of the field plate l according to the conventional structure (as shown in FIG. 1). These are the dimensions of a PNP transistor designed to have the same reliability with the same breakdown voltage. According to this example, about 40% (about 1/1.7)
The device area can be reduced.

FIG. 4 is a sectional view of a second embodiment of the invention. In the figure, the same reference numerals as in FIG. 2 represent the same or equivalent parts.

The structural feature of this embodiment is that, as is clear from the comparison with FIG. This is because the thickness of the passivation film 8 is made thin.

According to the structure of this embodiment, the electric field intensity at the surface of the n-base region 4 immediately below, which is generated by the potential at the tip of the field plate of the emitter electrode 1, increases depending on the thickness reduction of the passivation film 8. will be strengthened.

Therefore, for the same reason as mentioned above, the amount of charge accumulated on the n-base surface facing the tip of the field plate also increases, and the deformation prevention ability of the depletion layer 11 increases accordingly. Therefore, the reliability of withstand voltage can be significantly improved.

FIG. 5 is a sectional view of a third embodiment of the invention. 1 and 2 are emitter electrodes and collector electrodes, and 3, 4, and 5 are p emitter, n base, and p collector regions, respectively. Also, 13,1
4 are passivation films made of SiO ₂ and Si ₃ N ₄ , respectively.

The structural features of this embodiment include a passivation film 13 directly under the emitter electrode 1 and a collector electrode 2.
There is a difference in the passivation film 14 immediately below.

Ratio of permittivity of SiO ₂ and Si ₃ N ₄ ε[Si ₃ N ₄ ]/ε
[SiO ₂ ] is approximately 2. Therefore, the electric field effect exerted by the field plate of the emitter electrode 1 on the n-base surface immediately below it can be approximately doubled without reducing the thickness of the passivation film between the two. As in the case of , the reliability of withstand voltage can be improved.

Furthermore, as is clear, the effects of this embodiment can be further improved by combining it with the embodiment of FIG. 2 or 4. According to experiments conducted by the present inventors, compared to the conventional example shown in FIG. 3, when the same reliability is maintained, the element area can be reduced to about 1/2.5.

FIG. 6 is a sectional view of a fourth embodiment of the invention. In this figure, the same reference numerals as in FIG. 5 represent the same or equivalent parts.

13A and 14A are passivation films, respectively, 13A is made of SiO ₂ , while 14A is a passivation film.
is composed of Si ₃ N ₄ .

The feature of this embodiment is that the passivation film directly under the field plate of the emitter electrode 1 is
The passivation film directly below the field plate of the collector electrode ₂ is composed of a double layer of SiO ₂ and Si ₃ N ₄ , whereas it is composed of a single layer of SiO 2 .

In this case, by providing SiO ₂ on the surface of the n-base region 4, the number of interface states can be reduced and reliability can be increased compared to when Si ₃ N ₄ is provided on the surface of the n-base region 4. .

According to the configuration shown in FIG. 6, the dielectric constant of the passivation film directly below the field plate of the emitter electrode 1 is smaller than that of the passivation film directly below the field plate of the collector electrode 2.

Therefore, the electric field strength on the surface of the n-base region 4 is stronger directly below the field plate of the emitter electrode 1 than directly below the field plate of the collector electrode 2. Therefore, for the same reason as mentioned above, the reliability of withstand voltage is improved.

The present invention is not limited to the pnp transistors of the above embodiments, but is also applicable to lateral pnpn thyristors, pn diodes, and the like.

FIG. 7 is a sectional view of a fifth embodiment in which the present invention is applied to a pn diode. 16 and 17 are n-type electrodes and p-type electrodes, respectively, and 18, 19, 20
are n-type, n ^- type, and p-type semiconductor regions, respectively.
is the passivation membrane.

Each of the p-type and n-type electrodes 16, 18 functions as a field plate.

The feature of this embodiment is that the thickness of the passivation film 8 directly under the field plate of the n-type electrode 16 is
This structure is thinner than the thickness of the passivation film directly under the field plate of the p-type electrode 17.

The field plate of the n-type electrode 16 is
It shows the same field effects as detailed with respect to the p-emitter electrode 1 of FIG. Therefore, in this embodiment as well, the reliability of withstand voltage is significantly improved.

(Effects) As described above, according to the present invention, it is possible to prevent the depletion layer from extending over time due to long-term voltage application without increasing the field plate length, thereby improving the reliability of withstand voltage (leakage current). It is possible to achieve both a reduction in

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a conventional lateral type PNP transistor, FIGS. 2, 4, 5 and 6 are sectional views of a PNP transistor showing different embodiments of the present invention, and FIG. 3 is a sectional view showing a conventional lateral type PNP transistor. Shown in Figure 2
A top view of a pnp transistor, FIG.
FIG. 2 is a cross-sectional view of an embodiment applied to a diode. 1... Emitter electrode, 2... Collector electrode, 3
...p emitter region, 4...n base region, 5...
... p collector region, 8 ... passivation film,
9-11...depletion layer.

Claims (1)

[Scope of Claims] 1. A first semiconductor region serving as a substrate, a semiconductor region having a conductivity type different from that of the first semiconductor region, and formed so as to be exposed on one main surface of the first semiconductor region. a second semiconductor region, a third semiconductor region formed so as to be exposed on the main surface of the first semiconductor region and to face the second semiconductor region, and on the main surface; A passivation film is provided to cover the first to third semiconductor regions, and a first film is in low resistance contact with the second and third semiconductor regions through an opening formed in the passivation film. , and second electrodes, the first and second electrodes are provided on the passivation film and extend from the exposed surfaces of the second and third semiconductor regions to above the first semiconductor region. , a semiconductor device each forming a field plate, characterized in that the thickness of the passivation film located directly under at least the tip of the field plate of the second electrode is thinner than the thickness in other parts. Semiconductor equipment. 2. The semiconductor device according to claim 1, wherein the thickness of the passivation film located directly under the second electrode is thinner than the thickness of other portions. 3. A first semiconductor region serving as a substrate; a second semiconductor region having a conductivity type different from that of the first semiconductor region and formed so as to be exposed on one main surface of the first semiconductor region; , a third semiconductor region formed so as to be exposed on the main surface of the first semiconductor region and to face the second semiconductor region; a passivation film provided to cover the semiconductor region; and first and second electrodes that are in low resistance contact with the second and third semiconductor regions through openings formed in the passivation film. The first and second electrodes are provided on the passivation film and extend from the exposed surfaces of the second and third semiconductor regions to above the first semiconductor region, respectively forming field plates. The semiconductor device is characterized in that the dielectric constant of the passivation film located directly under at least the tip of the field plate of the second electrode is smaller than the dielectric constant of the other portions. semiconductor devices. 4. Claim 3, characterized in that the thickness of the passivation film located directly under at least the tip of the field plate of the second electrode is thinner than the thickness of other parts. semiconductor devices.