JPH0418700B2 - - Google Patents

Description

[Detailed Description of the Invention] (1) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor, and more specifically, to a method for bringing disconnected wiring in a semiconductor device into a state in which electricity can be supplied. be.

(2) Background of the technology Semiconductor devices, especially semiconductor memories, are used to write information by breaking wiring, that is, by blowing fuses, and by creating rows or columns of redundant circuits (spare) to replace defective bits. are using. On the other hand, information can be written in the same way by turning the disconnected wire into a state where it can be energized.
The use of spare rows or columns is possible. Furthermore, gate array (master slice) integrated circuits are constructed by appropriately forming necessary circuit wiring patterns. In this case, a new predetermined wiring is formed, but it is possible to form the entire disconnected wiring in advance and turn the predetermined wiring into a energized state to obtain the necessary wiring pattern.

(3) Prior art and problems One way to enable current to flow through a wire in a disconnected state is to form a structure in which doped polycrystalline silicon is placed on both ends of non-doped polycrystalline silicon, and then a laser beam or other beam is applied to this structure. There is a method of locally irradiating and heating energy rays to cause re-diffusion of impurities from doped polycrystalline silicon to non-doped polycrystalline silicon, making it possible to conduct electricity (Minato etal.ISSCC1981.SESSION 1, WAM
1, 2 Hitachi).

However, this method is limited in that only doped polycrystalline silicon can be used as the conductor material, which causes problems in reducing wiring resistance.

(4) Purpose of the Invention The purpose of the present invention is to propose a method for bringing disconnected wiring into a state in which electricity can be supplied without the above-mentioned problems.

Another object of the present invention is to propose a method for manufacturing a semiconductor device by employing a method of changing the wiring from a disconnected state to a energized state in the wiring process of the semiconductor device.

(5) Structure of the Invention These objects are such that the wiring forming process of a semiconductor device is as follows (a) to (d): (a) forming electrically insulated first and second conductor layers on a substrate; (a) forming a non-doped polycrystalline silicon layer over the first and second conductor layers, and (c) forming the first,
A high melting point metal silicide layer is formed in a region corresponding to the part spanning the second conductor layer, and (d) the surface of this high melting point metal silicide layer is heated and oxidized with an energy beam in an oxidizing atmosphere to form an oxide. The present invention is achieved by a method for manufacturing a semiconductor device, which comprises forming a layer and connecting a first and second conductor layer with a high melting point metal silicide layer.

In the present invention, a high melting point silicide layer is formed on a silicon layer, and when this silicide layer is thermally oxidized, a silicon dioxide (SiO ₂ ) layer is formed on the silicide layer, and at the same time, the thickness of the silicon layer under the silicide layer is reduced. The phenomenon in which this high melting point silicide layer subsides is substantially utilized.

(6) Embodiments of the invention The present invention will be described in detail below by way of embodiments of the invention with reference to the accompanying drawings.

The wiring forming step in the method of manufacturing a semiconductor manufacturing device according to the present invention is performed as follows.

As shown in Figure 1, an insulating layer (e.g. silicon dioxide, silicon nitride) 2 is formed on a semiconductor substrate (silicon wafer or gallium arsenide wafer) 1 by thermal oxidation, chemical vapor deposition (CVD), etc. form. Next, a non-doped polycrystalline silicon layer 3 is formed on the insulating layer 2 to a thickness of about 200 nm by low pressure CVD. A photoresist layer 4 having a wiring pattern is formed on the polycrystalline silicon layer 3 in order to make a part of this polycrystalline silicon layer 3 a conductive layer for wiring by doping with impurities (As).
(Figure), using this photoresist layer 4 as a mask, impurities (As) are selectively implanted into the polycrystalline silicon layer 3 by ion implantation. As a result, conductor layers 5A and 5B as shown in FIG. 2 are formed, and non-doped polycrystalline silicon layer 3 exists as an insulator between conductor layers 5A and 5B. In this state, as seen from a plan view in FIG. 3, the polycrystalline silicon layer 3 surrounds the conductor layers 5A and 5B. Therefore, the conductor layers 5A and 5B are in a disconnected state.

After removing the photoresist layer 4, a thin non-doped polycrystalline silicon layer 6 with a thickness of 20 nm to 30 nm is formed on the polycrystalline silicon layer 3 and conductor layers 5A and 5B by low pressure CVD method (second
figure). Since this polycrystalline silicon layer 6 is non-doped, it has insulating properties, but if the thickness is thinner than 20 nm, withstand voltage becomes a problem. Furthermore, if the thickness is 30 nm or more, it will take time to oxidize in the post-process.

Next, a high melting point metal silicide layer 7 is formed on the thin polycrystalline silicon layer 6 by a sputtering method or a CVD method.
and in the corresponding region of the conductor layer portion adjacent thereto. This state is shown in FIGS. 2 and 3. The high melting point metal silicide layer 7 is made of MoSi ₂ or
It is preferably made of WSi ₂ and formed into the shape shown in FIGS. 2 and 3 by a lift-off method using photoresist. Note that the thickness of the high melting point metal silicide layer 7 is preferably 200 nm or more, since the resistance value becomes large when it is thin.

Next, in an oxidizing atmosphere, that is, in a state where oxygen is flowing, the high melting point metal silicide layer 7 and its vicinity are irradiated with an energy beam (for example, an argon laser or a YaG laser) 8 to heat them. As a result, the high melting point silicide layer 7 is oxidized and a silicon dioxide layer 9 is formed on the surface (FIG. 4).
At this time, the silicon in the high melting point metal silicide layer is oxidized and removed and absorbs the silicon in the thin polycrystalline silicon layer below, so that the thin polycrystalline silicon layer 6 below this silicide layer 7 disappears. In this way, as shown in FIG. 4, the high melting point metal silicide layer 7 comes into contact with the conductor layers 5A and 5B, and the conductor layers 5A and 5B are electrically connected. Even the thin polycrystalline silicon layer 6 is oxidized where it is hit by the laser (FIG. 4). By irradiating only the necessary portions of the large number of high-melting point metal silicide layers with energy beams, those portions change from a disconnected state to a state in which current can be applied, and a predetermined circuit configuration is completed.

In the embodiments described above, a semiconductor substrate is used, but sapphire or glass can be used as the substrate, and in this case, it is not necessary to form an insulating layer.
Furthermore, it is also possible to use metal as the substrate, in which case an insulating layer is required. The conductor layer may be made of a high melting point metal such as Mo or W instead of doped polycrystalline silicon, and the insulator portion may be made of SiO ₂ or Si ₃ N ₄ instead of undoped polycrystalline silicon. . When using these materials, it is necessary to form them through an appropriate process different from the above-mentioned forming process.

Example: By thermally oxidizing silicon wafer 1
_Two SiO layers (thickness 1 μm) 2 were formed. A non-doped polycrystalline silicon layer 3 (thickness: 200 nm) was formed on this SiO ₂ layer 2 by low pressure CVD. A conductive layer 5 of polycrystalline silicon doped by ion-implanting As ions using the photoresist layer 4 as a mask.
A, 5B were formed (ion implantation energy
150keV, dose 5×10 ¹⁵ /cm ² ). After removing the photoresist layer 4, a thin non-doped polycrystalline silicon layer 6 (thickness 20 nm) was formed on the entire surface by a low pressure CVD method. This thin polycrystalline silicon layer 6
A photoresist layer (not shown) is formed by applying photoresist on top and exposing and developing it.
Sputter two Si targets at the same time to create MoSi ₂
A high melting point silicide layer is formed on the entire surface, and the photoresist layer and the MoSi layer thereon are removed to leave the MoSi layer 7 above between the conductor layers 5A and 5B. Hold silicon wafer 1 at 450℃ and
Argon laser 8 under oxygen atmosphere on MoSi ₂ layer 7
(5W, 1 second) was irradiated. SiO ₂ on MoSi layer 7
A layer 9 (thickness 40 nm) is formed, while the thin polycrystalline silicon layer 6 is missing under the MoSi ₂ layer 7.
MoS layer 7 contacted conductor layers 5A and 5B to connect these conductors 5A and 5B.

(7) Effects of the invention The manufacturing method according to the present invention produces a fuse-cutting type.
It can form an alternative to fuses in ROM or RAM with redundant circuits. Further, the same function can be achieved without the usual process of forming a wiring pattern on the gate array (mask fabrication, Al deposition, photorin process).

[Brief explanation of drawings]

1, 2, and 4 are schematic partial sectional views of a semiconductor device illustrating a wiring formation process in a method for manufacturing a semiconductor device according to the present invention, and FIG. 3 is a plan view of FIG. 2. It is. 1... Substrate, 2... Insulating layer, 3... Non-doped polycrystalline silicon layer, 5A, 5B... Conductor layer,
6... Non-doped thin polycrystalline silicon layer, 7...
...High melting point metal silicide layer, 8... Energy beam,
9...Oxide layer.

Claims (1)

[Claims] 1 The wiring formation process for semiconductor devices is as follows (a) to (d): (a)
forming electrically insulated first and second conductor layers on a substrate; (a) forming a non-doped polycrystalline silicon layer across the first and second conductor layers; cormorant)
A high melting point metal silicide layer is formed on this polycrystalline silicon layer in a region corresponding to the portion spanning the first and second conductor layers, and (d) the surface of this high melting point metal silicide layer is placed in an oxidizing atmosphere. A semiconductor device comprising: forming an oxide layer by heating and oxidizing with an energy beam in the semiconductor device, and wherein the high melting point metal silicide layer connects the first and second conductor layers. Production method.