JPH0418751B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital phase synchronization circuit, and is intended to reduce phase shift as much as possible.

[Conventional technology]

Personal computers (PCs) display (superimpose) the internal screen (PC screen) and the on-air or VTR TV screen on the display (CRT display). In this case, it is necessary to synchronize both screens, but since the TV screen cannot be adjusted, this is done by synchronizing the computer screen with the TV screen.

To explain with reference to FIG. 4, 10 is a video signal output terminal of a television receiver or video tape recorder;
The video (TV) signal from this terminal is connected to the computer.
It is input to the synchronous separation circuit 12 and selection gate 14 on the PC side. The horizontal synchronizing signal EH and the vertical synchronizing signal EV are separated in the circuit 12, and the phase comparator circuit 16,
18. 20 is a clock oscillator, and the clock CLK output by this oscillator becomes the dot clock of the CRT display screen, and is counted to have almost the same period (slightly shorter) as the horizontal synchronization signal HS and vertical synchronization signal EV of the television signal. A horizontal synchronizing signal HS and a vertical synchronizing signal VS are generated. 22
receives the clock CLK through gate 24;
This counter outputs the horizontal and vertical synchronizing signals HS and VS, and also generates an address for accessing the screen memory (VRAM, video RAM) 30. Memory 30 is a monitor (CRT display)
When the counter 22 reads out the data at the address generated, it outputs data for multiple dots at the same time, which is stored in the shift register 28 and sequentially output using the clock CLK. parallel/serial conversion) to become an image signal (more specifically, HS and VS are added to this).
The signal is also supplied to the clock CLK or the central processing unit CPU, and the CPU writes image data into the memory 30 and the like.

The gate 14 selects and outputs either the video signal from the terminal 10 or the video signal from the shift register 28 in response to a control signal (not shown). For example, in order to superimpose the computer screen 34 on the television _{screen 32} as shown in FIG _. computer signal,
The signal from the point _P2 to the terminal E may be a television signal, but the gate 14 performs this switching.

Synchronization between the TV screen and the computer screen is performed as follows. That is, if the internal horizontal synchronizing signal HS generated on the personal computer side is generated earlier than the external horizontal synchronizing signal EH separated from the television signal, the phase comparison circuit 16 produces an output, which enters the clock stop gate 24 through the OR gate 26.
Input to clock CLK and counter 22 is prohibited. The phase comparison circuit is, for example, a flip-flop, which is set at HS and reset at EV, and has a clock stop gate 24 whose output is an AND gate.
The above operation is performed. When the external horizontal synchronizing signal EH is input, the phase comparison circuit 16 releases the clock stop, and the counter 22 starts counting the clock CLK. The period of the internal horizontal synchronization signal HS generated on the personal computer side is slightly shorter than the period of the external horizontal synchronization signal EH, so the signal HS is
It arrives slightly earlier, thus causing a clock stop, and when the signal EH arrives, the clock stop is released. The same goes for the rest, and thus the internal horizontal synchronizing signal HS is synchronized with the external horizontal synchronizing signal EH. Internal vertical synchronization signal VS is similarly synchronized with external vertical synchronization signal EV.

[Problem that the invention seeks to solve]

In the circuit of FIG. 4, the horizontal/vertical synchronizing signals are synchronized digitally, and therefore there is a quantization error. That is, at the i-th clock CLK input, the counter 22 generates a horizontal synchronizing pulse HS,
As a result, if the clock stop gate 24 is turned off and the clock supply is stopped, then if the external horizontal synchronization signal EH is input within one period of the clock CLK, the gate 24 is turned on and the clock is stopped.
Since CLK is supplied to the counter 22, it is the same as if there were no clock interruptions (there are cases where a part of the clock pulse is missing and the counter malfunctions, but this will be ignored here), and within the above period. In this case, there is no EH input, but EH is generated within the next cycle.
If , only one clock is missing, and the same applies hereafter, so synchronization of EH and HS is only possible at an integral multiple of the clock cycle.

This is because on the superimposed screen of a CRT display, each scanning line on the computer screen fluctuates from side to side with the width of one clock cycle (causing jitter).
results in lower image quality. The present invention aims to improve these points and provide the same circuit which uses digital phase synchronization but has as little phase error as possible.

[Means for solving problems]

The present invention generates an internal signal when the counter counts the clocks and reaches a constant value, stops the clock supply to the counter with the internal signal, restarts the clock supply with the external signal, and synchronizes with the external signal. In a phase-locked circuit in a device that generates internal signals, there is an n-wave generation circuit that generates multiple clocks whose phases are sequentially delayed within one clock period from the clock, and one of high and low levels for internal signal generation. and a control signal that selects the other by generating an external signal, and a selection circuit that receives the plurality of clocks and selects one wave out of n waves that continues until the control signal changes to one level, the selection circuit , a plurality of flip-flops each receiving the plurality of clocks and holding the level of the control signal in response to each of the plurality of clocks; a first gate circuit that holds the flip-flops at one level, except for the flip-flops that are at the other level at an early clock; The second gate circuit directly outputs the clock input to the flip-flop, and the output clock of the selection circuit is supplied to the counter.

[Effect]

Create multiple clocks whose phases are sequentially delayed within one clock cycle from the original clock, and
By not only stopping and restarting the clock supply to the counter using an external signal, but also switching the clock, it becomes possible to achieve phase synchronization in which even the phases can be made to match fairly well.

〔Example〕

An outline of the circuit of the present invention is shown in FIG. In the present invention, as shown in FIG.
2, the clocks are set to clocks B, C, D, etc. whose phase is slightly delayed from the output clock CLK, and 1 out of n waves is set.
The wave selection circuit 44 selects the clock closest to the external horizontal synchronizing signal EH (the clock that appeared earliest after the generation of EH) and outputs it. In this way, the larger n is, the more an internal synchronization signal that is in phase with the external synchronization signal can be obtained.

Specifically, the n-wave generation circuit 42 may be a delay circuit 52 with a tap, as shown in FIG.
D,... can be obtained. These clocks B, C, D, . . . have the same period, waveform, etc. as the original clock A, and in this example, their delay times are also the same (B lags φ with respect to A, C lags φ, . . . with respect to B. However, φ is τ/n, where τ is the clock period)
I have chosen it. FIG. 2 shows an example of this. Of course, each delay time may be different, but the delay is made to be within a clock period, that is, even the most delayed clock occurs before the occurrence of the next clock after the original clock A. Such n clocks B, C,
The selection circuit 44 selects the one of D, .
is selected and output, and this output clock G is used as the output clock of the oscillator 20 in FIG.
2. Supply to the CPU, shift register 28, etc.

The components of selection circuit 44 are shown in FIG. 1c. As shown, it consists of a flip-flop 54 and an AND gate 56, which connects the signal F to the data input terminal D.
One of the output clocks of the n-wave generation circuit 42, B in this example, is received at the clock terminal, and the clear terminal is
CLR has output J from other flip-flops.
The Q output goes to the AND gate 56 together with the input clock B, and the output becomes the reset signal R for the other flip-flops. FIG. 3 shows details of the circuit shown in FIG. 1a constructed with these components.

In FIG. 3, it is assumed that the n-wave generation circuit 42 generates four clocks B to D with the same delay time, and for these, a flip-flop 54 and an AND gate 56 (a, b, . . . are subscripts to distinguish each other,
) will be omitted as appropriate. Each flip-flop 5
Clock terminals 4a to 54d have clocks B to D.
is input, and the output R is the OR gate 58a to 58
d and input to the clear terminal of another flip-flop. Further, the outputs of the AND gates 56a to 56d are combined by an OR gate 60, and the output G of the gate 60 is used as the output clock of this circuit.

To explain the operation with reference to FIG. 2, when the external horizontal synchronizing signal EH arrives and the signal F rises, the D terminal of each flip-flop becomes H (high) level.
Thereafter, when the input clock to the clock terminal rises to H level, the H level of data terminal D is taken in, and the Q output becomes H and the output becomes L. Since the output clears other flip-flops, a flip-flop that can make such an output change is
It is only the flip-flop whose clock first rises, and in the example of FIG. 2, this is only the flip-flop 54b receiving clock C. Therefore, in this cycle, clock C is connected to AND gate 56.
b. It passes through the OR gate 60 and becomes the output clock G, and the other clocks B, D, and E are blocked by the AND gates 56a, 56c, and 56d and are not output.

The flip-flop 54b takes in data every clock cycle, and since the signal F remains high until one cycle of horizontal synchronization ends, the Q output continues to be H and the output to L, and the other flip-flops are The clear state is maintained, and the output clock G is set to the clock C.

Internal horizontal synchronization signal after one period of horizontal synchronization
When HS occurs, the signal F falls, and then when the clock C rises, the flip-flop 54b takes it in, sets the Q output to L and the output to H, closes the AND gate 56b, stops sending out the clock C, and then Clear other flip-flops. Therefore, this circuit also serves as the clock stop gate 24 in FIG. To restart clock transmission, signal F is H.
This is done when the input clock rises and then the input clock rises, and the clock selected at this time is the clock that rose earliest after the rise of the signal F. Thereafter, this is repeated to achieve as much phase alignment as possible between external synchronization and internal synchronization.

When n = 4 as in this example, there is jitter in the range of 1/4 of one clock period, but one horizontal scanning line
Variations in quarter dot width in display systems such as 512 or 1024 dots are hardly noticeable. Of course, n may be set to 8, but the circuit will be more complex and faster. In addition, this circuit is not limited to synchronizing external/internal synchronization signals of the superimpose device, but also synchronizes internal signals (corresponding to internal horizontal synchronization signal HS) in other devices with external signals (corresponding to external horizontal synchronization signal EH). to synchronize. It can also be used in digital synchronization circuits.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to reduce the phase quantization error in a digital synchronization circuit as much as possible and make it similar to an analog synchronization circuit. It has the advantage that it does not have the inconvenience of adjustment and can be easily manufactured using logic gate ICs such as gate arrays.

[Brief explanation of drawings]

FIG. 1 is a schematic explanatory diagram of the present invention, FIG. 2 is a waveform diagram for explaining operation, and FIG. 3 is a diagram showing details of FIG. 1.
Figure 4 is the main circuit diagram of superimpose, Figure 5
The figure is an explanatory diagram of the superimpose screen. In the drawing, 22 is a counter, HS is an internal signal,
EH is an external signal, B, C, . . . are a plurality of clocks whose phases are delayed, F is a control signal, 42 is an n-wave generation circuit, and 44 is a one-wave selection circuit out of n waves.

Claims (1)

[Claims] 1. When a counter counts a clock and reaches a constant value, an internal signal is generated, and the internal signal stops the clock supply to the counter, and the external signal restarts the clock supply. A phase-locked circuit in a device that generates an internal signal synchronized with the clock includes an n-wave generation circuit that generates a plurality of clocks whose phases are sequentially delayed within one clock period from the clock; A control signal that takes one level and takes the other level by generating an external signal, and a selection circuit that receives the plurality of clocks and selects one wave out of n waves that continues until the control signal changes to one level, The selection circuit includes a plurality of flip-flops that each receive the plurality of clocks and hold the level of the control signal in response to each of the plurality of clocks, and a selection circuit that determines whether the level of the control signal held in the flip-flop is one of the plurality of clocks. A first gate circuit that sets the holding state of the flip-flop to one level, except for the flip-flop which is set to the other level by the clock having the earliest phase, and the level of the control signal held in the flip-flop is set to the other level. a second gate circuit that directly outputs the clock input to the flip-flop at the time of the second gate circuit, and is configured to supply the output clock of the selection circuit to the counter.