JPH0419709B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit that enables a high-voltage and highly accurate constant current circuit.

The equivalent circuit of a conventional device of this type is shown in Figure 1 a and b.
The structure was as shown in . In this example NPN
Although a configuration using transistors is shown, as is well known, there are semiconductor integrated circuits of opposite conductivity type, so a configuration using PNP transistors is also possible. Also, although a bipolar transistor is shown as an example in the figure,
It is also possible to apply to junction type FETs and MOS type FETs. For these, in the following explanation, it is necessary to read the emitter as a source, the base as a gate, and the collector as a drain. The conventional method will be explained below with reference to the example shown in FIG.

The current I ₀ flowing from the signal line 1 flows into the diode-connected input transistor 3 (labeled Q ₀ ) and biases the emitter-base junction of Q ₀ . This bias voltage V _BEO is applied to the emitter of the output side transistor 4 (indicated as Q ₁ ) connected in parallel.
By biasing the base junction, the current flowing through Q ₁ is almost independent of the voltage of power supply 2, and the output current I ₁ is proportional to the input current. Therefore, the same output current I ₁ also flows through the load R _l 9 connected to the collector of Q ₁ . This circuit is used as a constant current circuit or a current mode amplifier circuit in an integrated circuit by utilizing the above-mentioned characteristics. In this example, the ratio of input current to output current is approximately proportional to the emitter area ratio of Q ₂ and Q ₁ . It is known that this circuit causes an error in the base current of the input/output transistor, and as a measure to reduce the error in the base current, a base current compensation transistor (Q ₂ ) 7 as shown in FIG. 1b is also used. Proposed. The conventional current mirror circuit described above has the following drawbacks. FIG. 2 shows a cross-sectional example of a semiconductor device in which this type of integrated circuit is implemented. This is an example of a dielectric isolation process suitable for high breakdown voltage and high precision, but it is
Exactly the same argument can be made for the junction separation process. In FIG. 2, a single crystal semiconductor island 12 is provided in a support substrate 10 (generally made of polycrystalline Si) with a dielectric film 11 interposed therebetween. A base-collector junction 13, an emitter-base junction 14, and a collector low resistance layer 15 are formed in the island 12, and for electrical connection with the outside,
A base electrode 16, an emitter electrode 17, and a collector electrode 18 are provided. Conventionally, since the input and output transistors are realized with the same structure, the series parasitic resistance 19 in the collector region shown in FIG. 2 exists in both. Of these, the parasitic resistance 19 of the transistor on the output side is unavoidable in order to operate the constant current circuit shown in FIG. 1 even at a high power supply voltage. When a high voltage V _C is applied,
In order to maintain the constant current property of the circuit, it is necessary to extend most of the depletion layer of the base-collector junction toward the collector side rather than toward the base side. Regarding this, N _B・X _B = N _C・X _C However, N _B ; Base impurity concentration N _C ; Collector impurity concentration X _B ; Extension of the depletion layer toward the base side X _C ; Depletion toward the collector side There is a wide relationship between layers, and in order to increase X _C , island 1
The impurity concentration N _C in 2 must be lowered,
Base-collector junction 13 and collector low resistance layer 1
It is unavoidable that the low impurity concentration region between the regions 5 and 5 becomes a series parasitic resistance during circuit operation. Collector impurity concentration N _C
Considering that the resistance is approximately 5×10 ¹⁴ -cm ^-3 , this series parasitic resistance may be 1KΩ or more depending on the element structure.
On the other hand, Q ₀ is an input side transistor, so
The voltage applied between the emitter and the collector is at most a few volts, so there is no need for a region where a depletion layer extends like the output side transistor, but rather a parasitic resistance of 19
The low impurity region forming this is harmful to circuit operation as described below. The first problem is that the signal applied to the input side is attenuated by this series parasitic resistance. If the value of the series parasitic resistance in the previous example is assumed for an input current of several mA, the signal will be attenuated by several volts, which is extremely problematic. The second problem is that the configuration shown in FIG. 1b, which is effective as a highly accurate circuit, cannot be used in an integrated circuit depending on the value of the input signal. This means that in the circuit shown in Figure 1b, if there are series parasitic resistances such as 5, 8, 9, etc. of about 1KΩ, the signal source on the input side is at most 0.7m.
This is because only about A level is allowed. If a current larger than this flows, the potential drop due to the parasitic resistance 5 of Q ₀ will occur at the emitter of the transistor (Q ₂ ) 7.
Deeply forward bias the base junction and provide large base currents to Q ₀ and Q ₁ . Since the large amount of base current flowing into Q ₀ and the signal source current are added together and bias the emitter-base junction of Q ₀ , this circuit can no longer flow an output current corresponding to the signal source current, and the original Current mirror circuit operation becomes impossible.

SUMMARY OF THE INVENTION In order to eliminate these drawbacks, it is an object of the present invention to provide a novel integrated circuit structure for a high-precision, high-voltage constant-current circuit.

To achieve the above object, the present invention includes two or more transistors dielectrically isolated from each other,
The gist of the invention is an integrated circuit device characterized in that at least one transistor has an extension of the collector low resistance layer toward the emitter region.

Furthermore, the present invention provides an integrated circuit device in a current mirror circuit consisting of a plurality of transistors, characterized in that at least in the collector region of the input side transistor there is an extended portion of the collector low resistance layer toward the emitter region. It is something to do.

Next, embodiments of the present invention will be described with reference to the accompanying drawings. It should be noted that the embodiments are merely illustrative, and it goes without saying that various changes and improvements can be made without departing from the spirit of the present invention.

FIG. 3 shows an embodiment of the invention. A major feature of the present invention is that a protrusion 20 is provided in the vicinity of the collector section of the input side transistor 3 just below the emitter so as to face the emitter region, and as a result, a region is created in which the collector low resistance layer 15 extends to just below the emitter. It's in being. The rest of the structure is the same as that shown in FIG. Therefore, the series parasitic resistance of the collector of the input side transistor is 100Ω or less even if the impurity concentration of the collector region is the same as before, and the attenuation of the input signal due to this parasitic resistance can be made negligibly small. In addition, even if a large current is passed through the input side, the collector series parasitic resistance R _CO 5 is small, so the emitter-base junction of Q ₂ will not be forward biased deeply, allowing a wide dynamic range of the input signal. be.

Hereinafter, a method for manufacturing a dielectrically isolated integrated circuit that realizes such a structure will be illustrated in FIG. 4. For example, a Si (100) substrate 21 is used as a mask material 2.
2 to etch the desired pattern. This is indicated by the dashed line in Figure 4a. If processing is performed using a well-known anisotropic etching solution,
The angle indicated by θ in the figure is approximately 35°, and there exists a relationship between the etching depth D and the width W of the mask material as follows: D=W/(2tanθ). Using this relationship, it is possible to provide the protrusion 20 directly below the emitter of the input transistor. That is, the opening 23 (width;
w), which does not introduce any process complexity. Next, after removing the mask material 22, impurities having the same conductivity type as the substrate are introduced into the entire surface, and a dielectric film 11 is further formed (fourth
(see figure b). Next, a dielectric separation process is performed in which thick polycrystalline Si, which will become the supporting substrate 10, is deposited and unnecessary Si layer 24 is removed. After this, base-collector junction, emitter-base junction, as illustrated in Fig. 3,
Once the electrodes are formed, the desired integrated circuit can be realized. As is clear from the above explanation, the stretching of the low collector layer directly under the emitter, which is a feature of the present invention, does not bring about any process complexity.In comparison, this stretching significantly improves the characteristics of the integrated circuit. It is something to improve.

Although the embodiments of the present invention have been described above with respect to an integrated circuit with a dielectric isolation structure that is often used in high-voltage integrated circuits, it can also be extended to integrated circuits with a general PN junction isolation structure. In the example shown in FIG.
A separation diffusion layer 26, a first collector low resistance layer 15, a base-collector junction 13, an emitter-base junction 14, etc. are provided on the collector low resistance layer 15 of the input side transistor 3. It is clear that by providing the second collector low resistance layer 151, exactly the same effect as in the previous example can be obtained.
This collector low resistance layer 151 may be formed by overlapping a diffusion layer 15 with a higher impurity concentration than the first collector low resistance layer 15, and in this case, the collector low resistance layer 15 of the output side transistor 3 is not necessarily required. . However, in the integrated circuit with the PN junction isolation structure described here, at least one photolithography process and one diffusion process are added, and the process has fewer advantages than the previous example. However, it has all the advantages of no attenuation of the input signal, a wide dynamic range of circuit operation, and no restrictions on increasing the voltage resistance of the circuit.

As described above, according to the present invention, an integrated circuit having a dielectric separation structure with a high withstand voltage, high precision, and a wide dynamic range can be obtained, which has a simple structure and does not require any process complexity during manufacturing. A device is obtained. Also, by adding some processes,
PN with high voltage resistance, high precision and wide dynamic range
This has the advantage that an integrated circuit with a junction-separated structure can be realized.

[Brief explanation of drawings]

1a and 1b are equivalent circuits of the semiconductor device, FIG. 2 is the structure of a conventional semiconductor device, FIG. 3 is the semiconductor device of the present invention, FIGS. 4 a to c are manufacturing steps, and FIG. 5 is the invention of the present invention. An example of applying the PN junction is shown below. DESCRIPTION OF SYMBOLS 1... Signal source, 2... Power supply, 3... Input side transistor, 4... Output side transistor, 5... Collector series parasitic resistance of input side transistor, 6...
…Collector series parasitic resistance of output side transistor,
7... Base current compensation transistor, 8... Collector series parasitic resistance of base current compensation transistor, 9... Load, 10... Support substrate, 11...
Dielectric film, 12... Single crystal semiconductor island, 13... Base-collector junction, 14... Emitter-base junction, 15... Collector low resistance layer, 16... Base electrode, 17... Emitter electrode, 18... ...Collector electrode, 19...Series parasitic resistance in collector region,
20... Protrusion, 21... Si substrate, 22... Mask material, 23... Opening of mask material, 24... Unnecessary
Si layer, 25...Substrate, 26...Separation diffusion layer, 15
1...Second collector low resistance layer.

Claims (1)

[Claims] 1. An integrated circuit device in which a current mirror circuit comprising a plurality of transistors is characterized in that a protruding portion of a low collector resistance layer is formed in the collector region of at least the input side transistor immediately below the emitter and toward the emitter region.