JPH0420271B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to semiconductor memories, particularly thyristors and
This relates to the structure of a stake memory cell constructed using MOS.

Conventional configuration and its problems In order to reduce cell size, there is an ECL memory that uses a PNP transistor as a load, as shown in Figure 1.
Figure 1 shows a PNP transistor as an active load.
1 is a general circuit diagram of an ECL memory cell.

In Figure 1, 1 and 2 are multi-emitters.
NPN transistor, 1-C, 2-C respectively
collector, 1-B, 2-B base, 1-E
1,1-E2 is the first emitter, 1-E2,2-
Let E2 be the second emitter. 3 and 4 are PNP transistors, 3-C and 4-C are collectors, 3-B and 4-B are bases, and 3-E and 4-
Let E be Emitsuta. Collector 1-C and base 1-B of transistor 1 are connected to base 3-B and collector 3-C of transistor 3, respectively, and similarly collector 2-C of transistor 2 is connected to base 2-C.
B are connected to the base 4-B and collector 4-C of the transistor 4, respectively. Furthermore, the emitters 3-E and 4-E of transistors 3 and 4 are connected to the word line 5.
, the first emitters 1-E of transistors 1 and 2
1 and 2-E1 are connected to the data lines 6 and 7, respectively.
Emitters 1-E2 and 2-E2 are connected to a constant current source (not shown) terminal 8. Further, the collectors and bases of the transistors 1 and 2 are connected to each other by wirings 9 and 10. When a constant current is applied to transistor 8 and a current is drawn from emitter 6 to turn transistor 1 into an "ON" state, the potential of the collector of transistor 1 becomes low and transistor 2 becomes an "OFF" state.
Conversely, when a current is drawn from the emitter 7, the transistor 1 is turned "OFF" and the transistor 2 is turned "ON". These two states perform the memory function.

When converting a PNP transistor-loaded ECL memory cell as shown in FIG. 1 into a semiconductor integrated circuit IC, it is formed by structurally integrating a PNP transistor and an NPN transistor.

FIG. 2 shows a surface pattern diagram of the ECL memory cell shown in FIG. 1 converted into an IC. Portions corresponding to FIG. 1 are indicated by the same numbers. The first layer wiring is indicated by hatching from the upper right to the lower left, the second layer wiring is indicated by hatching from the upper left to the lower right, and the x mark indicates a through hole that connects the first and second layer wiring.

The interconnections between transistors 1 and 3, 2 and 4 are IC
Because they are structurally connected within the IC, wiring on the IC surface is not required, allowing for high integration.

FIG. 3 is a sectional view of the memory cell shown in FIG. 2.

The state of the wiring will be explained in detail based on the ECL memory cell cross-sectional structure diagram in FIG. FIG. 3a is a cross-sectional view taken along the line A-A' in FIG. 2, and FIG. 3b is a cross-sectional view taken along the line B-B' in FIG. Portions corresponding to those in FIG. 3 are given the same numbers.

In FIG. 3, 21 is a P-type semiconductor substrate;
2 is a high concentration N ⁺ type buried layer, 23 is a high concentration P ⁺ type channel stopper, 24 is an element isolation insulator, 2
5 is an N ^- epitaxial layer, 26 is a high concentration N ⁺ type region, 27 is a P type region, 28 is a high concentration N ⁺ type region,
29 is an insulator, 30 is an insulator between wirings, and 31 is a through hole. Here, the N epitaxial layer 25 is the collector of the NPN transistor and the PNP
The P region 27 becomes the base of the transistor.
It becomes the emitter of the PNP transistor, and also the PNP
It becomes the collector of the transistor and the base of the NPN transistor, and the N ⁺ region of 28 becomes the eternity of the NPN transistor, forming a lateral type PNP transistor and a vertical type NPN transistor. First emitter 1-E of transistor 1
The electrode 1 is connected to the second layer data line 6 via a through hole 31, and this data line passes directly above the transistors 1 and 3. Further, within the memory cell, only the data lines 6 and 7 are the second-layer wiring, and the rest are all the first-layer wiring.

In the above memory cell, the PNP transistor and the NPN transistor are structurally integrated to reduce the area of the memory cell.

However, in the memory shown in Figure 1,
A total of 6 transistors, 2 PNP transistors and 4 NPN transistors, are used, and when integrated into an IC, the wiring of any structure becomes complicated, resulting in a large cell area.

OBJECTS OF THE INVENTION In view of these conventional problems, the present invention aims to reduce the size of memory cells by reducing the number of cells, thereby providing a large-capacity memory.

Configuration of the Invention The present invention changes the state of a thyristor by signals of a first gate and a second gate of the thyristor,
The state of the thyristor is read out using a MOS transistor.

DESCRIPTION OF THE EMBODIMENTS The present invention is composed of a resistor, a thyristor _Q1 , and a MOS transistor _Q2 . FIG. 4 shows the memory configuration circuit, and FIG. 5 shows the characteristics of the thyristor.

A resistor 106 (R1) is connected in series with the thyristor _Q1 , and a positive voltage V _C is applied to its end 105.
At this time, it is in the state shown as "0" in FIG. 5, and the anode 107 has a voltage of V _C -I _pff R ₁ . By applying a sufficiently lower voltage signal than the end 105 to the first gate 109 via the write bit line 103 and the second gate 110 via the write word line 102 to the thyristor Q1, the thyristor Q1 becomes conductive and enters the "1" state. Move to. At this time, the anode 107
becomes the voltage V _C −I _po R ₁ . For reading, connect the bit line 104 to the resistor 115 (R2) and apply a positive voltage to the word line 101. When the thyristor Q1 is in a conductive state, the anode voltage is low.
MOS transistor Q2 is conducting and resistor 11
Since current flows through resistor 115, approximately I _po・R ₂
voltage is generated.

Figure 6 shows the surface pattern diagram when Figure 4 is converted into an IC.
As shown in the figure. Portions corresponding to FIG. 4 are indicated by the same numbers. The first layer wiring is indicated by hatching from the upper right to the lower left, the second layer wiring is indicated by hatching from the upper left to the lower right, and the x mark indicates a through hole that connects the first and second layer wiring. The resistor 106 is made of polysilicon and is connected to the gate electrode 11 of the MOS transistor.
It is also used in 1.

FIG. 7 shows a cross-sectional view of the memory cell shown in FIG. 6, and the state of wiring will be explained based on the cross-sectional view of the memory cell shown in FIG. FIG. 7a is a cross-sectional view taken along line C-C' in FIG. 6, and FIG. 7b is a cross-sectional view taken along line D-D' in FIG. Portions corresponding to those in FIG. 6 are given the same numbers. In FIG. 7, 121 is an n-type substrate, 122 is a P-type buried layer 123 is an n-type epitaxial layer, 124 is a high concentration P-type region, 125 is a high concentration P-type region, 126
is a highly doped n-type region and is an n-type epitaxial layer 123.
127 is a polysilicon film forming the resistor 106 and gate 111, 128 is an insulator for isolation from other elements, 129 is a gate oxide film, and 130 is a region for making ohmic contact. is an insulator, 131 is a first layer wiring, 13
2 is an interlayer insulator, and 133 is a second layer wiring. Here, the P-type buried layer 122 becomes the first gate 109 of the thyristor and separates the N-well 112 of the MOS transistor from the substrate 108, and the N-type epitaxial layer 123 becomes the second gate 109 of the thyristor.
10 and MOS N-well 112, the P-type region becomes the anode 107 of the thyristor and the source 114 and drain 113 of the MOS transistor, and the polysilicon 127 becomes the electrode of the anode 107 of the thyristor, the resistor 106, and the gate electrode 111 of the MOS transistor. .

In this embodiment, an n-type substrate is used for the cathode 108, but if a bipolar IC or the like is formed at the same time, an n-type buried layer formed in a p-type substrate may be used.

This memory is made up of one thyristor and one MOS transistor, whereas conventionally it was made up of six transistors (as shown in Figure 1).
The number of elements is decreasing. In addition, whereas conventionally there were 10 contacts to connect many elements (8 transistors), in this embodiment there are only 5 contacts.
As a result, the cell size is also becoming smaller.

Another embodiment according to the invention is shown in FIG. 8th
For explanation, an equivalent circuit of the thyristor is shown in FIG. 9, and the explanation will be given with reference to FIGS. 8 and 9. Write bit line 103 and write word line 102 turn on thyristor Q1. At this time, transistors Q ₃ and Q ₄ in the equivalent circuit shown in FIG.
is in the “ON” state, and the potential of the second gate 110 is lowered by the V _BE voltage (approximately 0.7 V) due to the anode 107. Therefore, depending on the potential of the anode 110
It can be read out in the same way when used as the gate of a MOS transistor.

Effects of the Invention As described above, the present invention provides a thyristor, a resistor, and a
By using MOS transistors, the following effects can be obtained.

(1) The number of elements that make up the memory is small.

(2) Reducing the area of memory cells Since the number of elements is small, the number of contacts for wiring between elements can be reduced, and the area can be reduced.

(3) Simplification of wiring Since the number of elements is small, wiring becomes easy.

As described above, according to the present invention, high density memory,
It can be simplified and can greatly contribute to the realization of large-capacity memory.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of a conventional memory cell with a PNP transistor as a load, Figure 2 is a surface diagram of the IC pattern in Figure 1, and Figures 3a and b are A of the IC in Figure 2.
-A', B-B' line cross-sectional view, Figure 4 is a circuit diagram of a memory cell according to an embodiment of the present invention, Figure 5 is a graph showing a characteristic diagram and load curve of a thyristor, and Figure 6 is a diagram of the present invention. A surface view of an IC pattern according to one embodiment, FIGS.
FIG. 8 is a circuit diagram of a memory cell according to another embodiment of the present invention, and FIG. 9 is an equivalent circuit diagram of a thyristor. Q1...Thyristor, 107...Anode, 10
8...Cathode, 109...First gate, 110
...Second gate, Q2...MOS transistor,
111...gate, 112...well, 113...
...Drain, 114...Source, 106...Resistor.

Claims (1)

[Scope of Claims] One thyristor, a resistor, and a MOS transistor, one of the first gate or the second gate of the thyristor is connected to a write word line, the other is connected to a write bit line, and the write word line and the write bit line are connected to each other. The thyristor is switched by the signal on the bit line, one of the source or drain of the MOS transistor is connected to the read word line and the other is connected to the read bit line, and the switching state of the thyristor is controlled by the signals on the read word line and the read bit line. A semiconductor memory characterized by reading out. 2. The semiconductor memory according to claim 1, wherein the gate of the MOS transistor is drawn out from the anode. 3. The semiconductor memory according to claim 1, wherein the gate of the MOS transistor is led out from the gate closer to the anode side of the thyristor.