JPH0420490B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a main memory access method in a data processing device, and more specifically, to a method for accessing main memory in a data processing device, and more specifically, a method for accessing main memory in a data processing device, and more specifically, a method for accessing main memory in a data processing device. When sources access data in a common main storage area in conflict, the main storage is accessed while guaranteeing data consistency for accesses from each requester, i.e. from one requester. The lock bit of the data area is set to "1" while the data in the main memory that is being accessed is not completed, and when accessed by another request source, the other request source cannot access the data area. Relating to a main memory access method that improves efficiency when accessing the main memory by using a soft lock method that can recognize that another request source is in the process of updating when the lock bit is "1" .

[Conventional technology]

When request sources such as CPUs, CHPs, or CPUs and CHPs conflict with each other to access data in a common main storage area in the main storage device, the main memory access operation from one request source is If the data in the main memory being accessed is accessed by another request source while the data is still being accessed, the data obtained by the other request source will be accessed by the other request source. will result in an undesired error. Therefore, when a conflict occurs in data in a common main storage area, a main storage access method is used that guarantees data consistency for access from each request source.

3 to 6 show a data processing system that accesses main memory and a conventional main memory access method.

FIG. 3 shows a data processing system that accesses main memory. In the figure, 10
11 is a main storage device, 11 is a CPU, 12 is a channel processing unit (CHP), and CHP 12 is provided with an input/output channel (CHA) and a data transfer control unit. 1
3 and 14 are input/output control units (IOC), 15 and 16
is an input/output device (IO).

In this configuration, the CPU 11 is the main storage device 1
0 and perform data processing. on the other hand,
CHP12 sends requests from IO15 or 16 to IOC
When received from 13 or 14, it accesses the main storage device 10 and transfers the data.

FIG. 4 shows the configuration of the main storage device 10. In the figure, 17 is the main memory, which has multiple banks (BANK) that store data in an 8-byte configuration.
have. Four BANK ₀ to BANK ₃ are shown in the figure. 18 is the priority port.
The function register (PPR ₀ ) is
Function address register (FCAD ₀ ) where code FC and address AD are set and data register (DR ₀ ) where data is set.
The request data from the CPU 11 is set. 19 is also a priority port.
The function register (PPR ₁ ) is
Function address register (FCAD ₁ ) where code FC and address AD are set and data register (DR ₁ ) where data is set.
The request data from the CHP 12 is set. DR ₀ and DR ₁ both have a 16-byte configuration, and are divided into the first half 8-byte data area D _U and the second half 8-byte data area _DL , and the read data is stored in BANK 0 to BANK ₀ of the main memory 17, respectively.
Stored in BANK ₃ in 8-byte interleaved format. 20 to 23 are multiplexers (MPX)
So, MPX20 and 21 have data area D _U and data area
Select one of D _L , MPX22 is PPR ₀ 18
Select one of PPR ₁ 19, MPX23 is FCAD ₀
and FCAD ₁ , and store the data in the respective data areas D _U and _DL of DR ₀ and DR ₁ in one of BANK ₀ to BANK ₃ according to each address. 24 and 25 are request get registers (RGR ₀ , RGR ₁ ), which are used by CPU 11 and CHP 12.
Function code FC transferred from
Address AD and data are temporarily set.
26 and 27 are port input control units (PIC ₀ , PIC ₁ )
Then, transfer the data of RGR ₀ to FCAD ₀ and DR ₀ , and RGR ₁
Controls the transfer of data to FCAD ₁ and DR ₁ .

FIG. 5 shows the structure of data stored in the main memory 17. The whole is 16 bytes (0~
127 bits), but each of 8 bytes
The first 8 bytes of data are stored in BANK.
It consists of _D0 and the latter 8-byte data _D1 .
Since data is transferred from the input/output channel CHA of CHP12 using a 4-byte interface, data D ₀ and D ₁ are transferred into 4-byte units of data D _0L , D _0U and D _1L ,
D Transferred in _1U . A lock byte is provided at the beginning of data _D0 in the first half. A lock bit L is written in the first bit as a lock signal.
When the lock bit L is "0", that is, when the lock signal is released, this indicates that the data is not being updated, and each request source can use this data. When the lock bit L is "1", this indicates that the data is being updated, so each request source cannot access this data.

When this data is stored in each BANK of the main memory 17, it is stored in an 8-byte interleaved format, but when the first half data _D0 is stored, the first lock bit L is set to "0". . However, since data is stored in each BANK in an 8-byte interleaved format, it takes a long time from when data D ₀ in the first half is stored in one BANK until data D ₁ in the second half is stored in the next BANK. There is a certain distance. Therefore, one request source finishes writing the first half of data D ₀ and writes the second half of the data.
If another request source makes a fetch request for the same data area while D ₁ has not yet been written, the lock bit L is already set to "0", so the writing is completed and the area is no longer in use. It is determined that the second half of the data D1 is lost, and data is read out including the latter half of the data _D1 , resulting in inconsistent and incorrect data being read out.

Therefore, in the conventional main memory access method, when writing data, the latter half of the data is first
By writing D ₁ and then writing the first half data D ₀ , it is possible to recognize that all data has been written when the first half data D ₀ has been written and the lock bit becomes "0". method is used.

FIG. 6 illustrates a time chart of this conventional main memory access method, taking as an example the case where the main memory 17 is accessed from the CHP 12.

CHP12 includes input/output channel CHA, function code FC, descending order store instruction, address
AD and data (first half data D ₀ , second half data
D ₁ ) is transferred, the request port register (RPRCH main memory 1
The configuration is similar to PPR ₁ 19 of PPR 0). Data transfer from input/output channel CHA is 4
This is done in bytes, so 8 bytes of data
D ₀ and D ₁ are 4 bytes D _0L , D _1U and
It is transferred separately into D _1L and D _1U (Figure 6).

Function code FC has main memory 17
Information identifying whether the access to the data is an 8-byte fetch, 8-byte store, 16-byte fetch, 16-byte store, etc. is entered. In the case of Figures 4 to 6, the CHP 12, CPU 11, and main memory 10 are stored in 8-byte units.
data is transferred between the main memory 17 and
Since data is stored in BANK in 8-byte units, an 8-byte store request is written.

When data is transferred to the main storage device 10, the function code FC, address AD, and second half data _D1 are first sent to a request in register (RIRCH, not shown) in the CHP 12, _RGR1 in the main storage device 10. 25)
(Figure 6).

The FC, AD, and _D1 data transferred from the RIRCH of the CHP 12 are stored in the _RGR12 in the main storage device 10.
It is temporarily set to 5 (Figure 6).

Function code FC and address AD of RGR ₁ 25 are set to FCAD ₁ by PIC ₁ 27 and data D ₁ is set to D _U of data register DR _1.
(Figure 6).

The MPXs 21, 22, and 23 store the 8-byte second half data _D1 in a predetermined BANK according to the address of FCAD ₁ (FIG. 6).

When the storage of the data _D1 is completed, a storage completion signal is notified to the CHP 12 (FIG. 6).

When the CHP 12 receives this storage completion signal,
The first half data D ₀ is transferred to the main storage device 10 in the same procedure as the second half D ₁ described above, and stored in the BANK at a predetermined address in the main storage 17 (see FIG. 6).

When the storage of the first half data _D0 is completed, a storage completion signal is generated and notified to the CHP 12 (FIG. 6~).

By doing this, even if another request source accesses the same data area while one request source is performing data store processing to the main memory 17, the Other requesters can be aware that the data area is being updated.

However, in this main memory access method, after storing the second half data D ₁ , the first half data D ₀
Since the processing of the next data has to wait until the storage of the next data is completed, there is a problem that the data processing efficiency decreases.

[Problem that the invention seeks to solve]

In the conventional main memory access method, when the data to be stored spans multiple BANKs in main memory,
The next data processing is forced to wait until the storage of the data portion with the last lock bit is completed, and especially if there is an access from a high-priority request source, the data processing efficiency is improved. There was a problem with the decrease in

The present invention was made to solve the above-mentioned problems in conventional main memory access methods, and is a main memory access method that guarantees data consistency for access from each request source and has good data processing efficiency. The purpose is to provide

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention has a main memory device having a main memory composed of a plurality of banks, a plurality of request sources to the main memory, and a main memory device that has a main memory configured from a plurality of banks. A main memory access method for a data processing system that sets a lock bit indicating whether or not a series of data to be accessed is being accessed when an access request spans multiple banks, and accesses the main memory in bank units. The main storage device is provided with a plurality of registers for storing a series of multiple bytes of data to be accessed, and the registers contain data from each request source and an address indicating one of the banks to be accessed. ,
, create an address for each bank to be accessed from the address stored in the register, access the main memory, and finally access the bank to the data including the lock bit. do.

[Effect]

When multiple request sources make access requests to main memory where access operations consisting of multiple banks are performed on a bank-by-bank basis, and the access requests from each request source span multiple banks, the request source Continuously transfers access requests that span multiple areas to the main memory.

In the main memory, the transferred data and the address indicating one of the banks to be accessed are stored in a register.

From the address stored in the register,
Create an address for each bank to access the main memory. However, access to the main memory is processed so that bank access to data including lock bits is performed last.

As described above, the main memory is provided with a register that temporarily stores the data to be accessed and the address indicating one of the banks to be accessed,
Since access requests are continuously transferred and stored from the request source, the next access process can be started immediately after data storage in the register is completed, and the data stored in the register is data including lock bits. Since the last bank access is made, data consistency can be guaranteed and data processing can be improved.

〔Example〕

Embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is an explanatory diagram of an embodiment of the present invention, and FIG. 2 is a time chart illustrating the operation of the embodiment. Furthermore, the configuration of the data processing system shown in Fig. 3,
Since the configuration of the main memory 17 in FIG. 4 and the data configuration in FIG. 5 are common to the embodiments of the present invention, these drawings and configurations will be referred to as appropriate in the description of the embodiment of the present invention described below. Ru.

In Figure 1, 30 surrounded by a chain line is CHP,
50 is the main memory device, and each CHP1 in Fig. 3
2 and the main storage device 10.

In the CHP 30, input/output channels (CHA) 31 and 32 control data transfer between the IOCs 13 and 14. 33 is the request port register (RPR), CHA31, ie
It has a data register 34 (DR34) in which the address, data, etc. transferred from the IOC 13 are set, and a data register 35 (DR35) in which the address, data, etc. transferred from the CHA 32, ie, the IOC 14, are set. DR34 and DR35 have the same data structure, including function code (FC), address (AD), and the first 8.
16-byte data consisting of byte data _D0 and the latter 8-byte data _D1 is set. data
The configuration of D ₀ and D ₁ is as shown in FIG. In other words, data is transferred from each CHA via a 4-byte interface bus, so the first half data D ₀ and the second half data D ₁ are
D _0L , D _0U and D _1L , D _1U each in 4-byte units
It is set separately. Input/output channel (CHA)
When data is stored in the common data area of the main memory, a lock bit L is written as a lock signal in the first bit of data _D0 , that is, data _D0U .

36 is request in register (RIR)
Then, the function code FC, address AD, and 8-byte first or second half data are set. 37 is a request control unit that controls multiplexers (MPX) 38 to 41 to
34 and 35, and further selects one of its FC, AD and data D ₀ , D ₁ for the selected data register DR and sets it in RIR 36.

The function code FC contains 8 bytes.
Fetch, 16-byte fetch, 8-byte store, and 16-byte store are written.

42 is the timing register (TUR)
This is used when transferring 16 bytes of data, and in the case of normal ascending store, when transferring the first 8 bytes of data _D0 , "ON" is written by the request control unit 37, and the latter 8 bytes are “OFF” is written when transferring byte data _D1 . In the case of descending store, the latter 8 bytes of data
When transferring D ₁ , "ON" is written by the request control unit 37, and the first 8 bytes of data are
When transferring D ₀ , “OFF” is written.

When storing in descending order, the first address of the second half data _D1 is sent as the address AD.

Next, in the main memory 50, 51 is a request get register (RGR), and the CHP 30
Temporarily set the FC/AD and 8-byte data transferred from. 52 is a priority port register (PPR), which stores data with the same structure.
Has registers (DR) 53 and 54, CHP30
Set the FC, AD and 16 bytes of data transferred from. The 16-byte data is set in the data upper area (D _U ) and data lower area (D _L ) in units of 8 bytes. data register
By providing two sets of DRs 53 and 54, data of two channels can be processed in parallel. In the following explanation, it is assumed that DR53 has priority.

55 is Time Atsupah Register (TUR),
16 bytes transferred from TUR42 of CHP30.
Set the ON or OFF signal when transferring data. 56 is a port input control unit, TUR55
When is ON, the 8-byte data set in RGR51 is set to the DU area, and when it is OFF, the 8-byte data is set to the _DU area.
Set byte data to _DL area. As a result, the second half data _D1 transferred from the CHP 30 during the descending store is set in the _DU area of the DR 53, and the first half data _D0 is set in the _DL area.

57 and 58 are _DL selection timing circuits, which generate addresses for the _DL area using exclusive OR (EX/OR) circuits 59 and 60. That is, the second half data D ₁ is set in the D _U area, the first half data D ₀ is set in the D _L area, and the address of data D ₁ is set in the address AD. Since the addresses when stored in the BANK of the main memory 17 are in the order of D ₀ →D ₁ , the address of D ₁ is 8 more byte addresses than D ₀ . For example, when storing 16 bytes of data in byte addresses 16 to 31 of the main memory 17, the first byte address of _D1 is 24 and the first byte address of _D0 is 16, as shown in the figure below.

In the figure, the right end is the LSB, so when the byte address of _D1 is 24, the 27th and 28th bits are "1". The byte address of D ₀ is
Since the number is 16, which is 8 less than this, it is sufficient to change the 28th bit from "1" to "0". When storing 16 bytes of data in descending order, the first address of data _D1 is a multiple of 8, and the 29th to 31st bits are all "0". Therefore, in the descending order store mode, the 29th to 31st bits are not sent, but the 0th to 28th bits are sent, and the 28th bit is set to "1", indicating an 8-byte boundary. When the D _L selection timing circuit 57 or 58 detects a 16-byte store by the function code FC,
For the first time, select D _U and follow the AD address.
Store D _U in main memory. In the second time, _DL is selected and the "1" output is sent to the EX/OR circuit 59 or 60. The other input of EX/OR circuit 59 or 60 is connected to the boundary of address AD, that is, the 28th bit. Therefore, when storing in descending order, the EX/OR circuit 59 or 60 causes the address of the D _L area, that is, the address of _D0 , to be 8 bytes smaller than the address of the D _U area, that is, the address of _D1 , and becomes a normal address value. is generated.

63 to 67 are multiplexers (MPX),
MPX63, 64 and 67 select the data in the data register DR to access the main memory 17, MPX66 selects the address of the data, and MPX65 selects the data register DR.
Select DR function code FC.

The above was explained in relation to CHP30, but CPU1
1 in the same way, MPX65,6
6,67.

Next, the operation when storing the 16-byte data in FIG. 1 in descending order will be explained with reference to the time chart in FIG. 2. In addition, in the following explanation,
A 16-byte store request is made from CHA31 to CHP30, and the 16-byte data is stored in the DR of CHP30.
For example, when the data is set to DR53 and transferred to the main storage device 50,
The access operation to the main memory 17 will be explained.

(1) When a 16-byte store request is made,
CHA 31 sets the 16-byte store function code FC to the FC of DR 34 of RPR 33 and receives a descending store support.
Next, the address AD sent from CHA31 via the 4-byte interface bus is
First half data D _0U and D _0L to AD of DR34
Put the second half data D _1U and D _1L into D ₀ of DR34.
Set each to _D1 of DR34. (Figure 2).

(2) The request control unit 37 sends the MPX3
8 and 40, DR34 function code FC, second half data D ₁ address
Set AD to RIR36 FC and AD. Furthermore, regarding the data, first set the latter 8-byte data _D1 , turn on TUR42,
The contents of these RIR 36 and TUR 42 are transferred to the main storage device 50. In the present invention, after transferring the second half data D ₁ , the first half data D ₀ is set in RIR 36 using the same FC and AD, and TUR
42 and transfers it to the main storage device 50 (FIG. 2).

Therefore, the CHP 30 sequentially stores the 16-byte data D ₁ and D ₀ in the DR 34 into the main storage device 50.
By transferring the data to , the next data processing can be started immediately.

(3) Initially, CHP
Function code FC instructing 16-byte store from 30, address AD of second half data _D1 , and second half data _D1 are set,
An ON signal is set in TUR55. These data are input by the port input control section 56.
When transferred to PPR52, the first half of data D ₀ is subsequently transferred from CHP30 to RGR5 with the same FC and AD.
1, and TUR55 is set to OFF (Fig. 2).

(4) The port input control unit 56 controls the FC of RGR51,
Based on the contents of AD and TUR55, TUR55
When is ON, the 8-byte data of RGR51 is
Set it in the _DU area of DR53 in PPR52,
When TUR55 is OFF, the 8-byte data of RGR51 is set in the _DL area of DR53, and the FC and
AD is set as FC and AD of DR53. As a result, AD of DR53 has
The first address of D ₁ is the second half of the data in the D _U area.
_First half data _D0 is set in the D _L area (FIG. 2).

(5) When the DL selection timing circuit 57 detects a 16-byte store from the contents of the FC, the first 8 bytes are the data in the D _U area and the AD address, that is, the second half data _D1 and its address are stored in the DR5.
Read from 3 (in this case, EX/OR circuit 5
9 does not operate), MPXs 63, 65, 66, and 67 are used to store specified addresses in the main memory 17.
Store the second half of the data _D1 in BANK (Figure 6).

The DL selection timing circuit 57 reads the D _L area, that is, the first half data D ₀ from the DR 53 following the D _U area. On the other hand, regarding the address,
The 28th boundary bit of the address AD is inverted by the EX/OR circuit 59, that is, the byte address is 8 fewer than the original address AD.
An address for D ₀ is generated, and the first half of the data D ₀ is stored in the BANK at a predetermined address in the main memory 17 .

(6) When the storage of each data in the D _U area and D _L area, that is, the second half data D ₁ and the first half data D ₀ , is completed in the main memory 17, a storage completion signal is generated and notified to the CHP 30 (first Figure 6).

Upon receiving this storage completion signal, the CHP 30 moves to the next data access process. By the time the lock bit L becomes "0", all 16 bytes of data have been stored in the main memory 17, so data consistency is guaranteed even if other request sources access this data. be done.

The main memory access method of the present invention can also be effectively used when data is transferred in descending order of addresses. For example, when performing a backward read operation on a magnetic tape device, data must be stored in main memory in descending address order. At this time, if the data is 8 bytes, it can be stored in one BANK at once, so there is no problem, but when performing a 16-byte store to improve processing efficiency, after storing the latter 8 bytes, It is necessary to store 8 bytes of data. In such a case, according to the main memory access method of the present invention,
Data consistency can be maintained and 16 bytes of data can be efficiently stored in BANK of main memory.

The main memory access method for 16-byte data consisting of 8-byte units has been described above, but the present invention is applicable to 16-byte data in 8-byte units, and all data
It is not limited to 16 bytes, but is used for accessing data stored across multiple BANKs of a predetermined number of bytes, and even in descending order of addresses, release of the lock signal is the final address. If the order is descending, there is no problem even if the order of addresses of intermediate unit data is changed. Further, the order of addresses of data to be transferred to the main memory is not limited to normal address order or descending order.

〔Effect of the invention〕

As described above, according to the present invention, the main memory is provided with a register that temporarily stores data to be accessed and an address indicating one of the banks to be accessed, and access requests are continuously received from the request source. Since the data is transferred and stored, the next access process can be started immediately after the data has been stored in the register, and the data stored in the register is accessed so that the bank access to the data containing the lock bit is the last access. Therefore, data consistency can be guaranteed and data processing can be improved.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of an embodiment of the present invention, Fig. 2 is a time chart explaining the operation of the embodiment, Fig. 3 is an explanatory diagram of a system that accesses main memory and processes data, FIG. 4 is an explanatory diagram of the conventional main memory access method, FIG. 5 is an explanatory diagram of the data structure stored in the main memory, and FIG. 6 is a time chart of the conventional main memory access method. In the figure, 10 is the main memory, 11 is the CPU, 12
is a channel processing unit (CHP), 13 and 14 are input/output controllers (IOC), 15 and 16 are input/output devices (IO), 17 is main memory, 18 and 19 are priority port registers (PPR ₀ , PPR ₁ ), 20
~23 is a multiplexer (MPX), 24 and 25 are request get registers (RGR ₀ ,
RGR ₁ ), 26 and 27 are port input control units (PIC ₀ ,
PIC ₁ ), 30 is a channel processing device (CHP), 3
1 and 32 are input/output channels (CHA), 33 is request port register (RPR), 34 and 35
is a data register (DR), 36 is a request in register (RIR), 37 is a request control unit, 38 to 41 are multiplexers (MPX),
42 is a timing register (TUR),
Further, 50 is a main memory, 51 is a request get register (RGR), and 52 is a priority register.
Port register (PPR), 53 and 54 are data registers (DR), 55 is time register.
Register (TUR), 56 is port input control unit, 5
7 and 58 are D _L selection timing circuits, 59 and 60
indicates an exclusive OR circuit (EX/OR), and 63 to 67 indicate multiplexers (MPX), respectively.

Claims (1)

[Scope of Claims] 1. A main memory device having a main memory composed of a plurality of banks, and a plurality of requests to the main memory, and an access request to the main memory from each request source spans the plurality of banks. In the main memory access method of a data processing system, a lock bit is set to indicate whether or not a series of data to be accessed is being accessed, and access operations to the main memory are performed bank by bank. , comprising a plurality of registers for storing a series of multiple bytes of data to be accessed, and storing in said registers both data from each request source and an address indicating one of the banks to be accessed; The main memory is accessed by creating an address for each bank to be accessed from the address stored in the register, and the bank access to the data including the lock bit is performed last. main memory access method.