JPH04205246A - Small sized electronic computer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a small electronic calculator that uses a liquid crystal display device to display symbols during calculations.

[Prior Art] In a conventional small electronic computer with a liquid crystal display of this type, data regarding lighting and non-lighting of each symbol representing the state and mode of the computer is stored in a RAM, and the control circuit for the liquid crystal display is , as shown in FIG. 7, the data line for liquid crystal display and the address line for specifying the data area for RAM10, and the data line and address line for calculation are used in common. Switching gate 1
1a and 1b are used to switch between a normal address used in calculations and a DISP address used in display mode. For this reason, when accessing the RAM during calculations, it is not possible to access the display data for the liquid crystal, and it is therefore necessary to erase the displayed symbols while the calculations are being executed.

However, the calculation may take a relatively long time to perform,
In such cases, the user may feel uneasy. To eliminate this anxiety, for example, a symbol indicating that the calculation is in progress may be turned on while the calculation is being executed, but this poses the problem of complicating the circuit configuration.

[Problems to be Solved by the Invention] This invention was made in order to solve such problems, and it is a small electronic type that makes it possible to light up the necessary symbols during the execution of calculations without complicating the circuit configuration. Its purpose is to provide computers.

[Means for Solving the Problems] The present invention provides a display unit that drives and displays numbers and symbols using a combination of a plurality of common signals and a plurality of segment signals, and display data and calculation data displayed on the display unit. and at least one symbol display unit that is displayed in combination with a specific one of the common signals and a specific at least one of the segment signals; latch means for storing the segment signal data; means for causing the latch means to read and store symbol display data from the storage means before execution of the calculation; and storage in the latch means in synchronization with the specific common signal during execution of the calculation. The present invention is characterized by comprising means for sending the symbol display data to the symbol display section.

[Function] In this way, before executing an operation, the segment signal data of the symbol that needs to be displayed during the operation is read out from the RAM and stored in the latch, and during the execution of the operation, the segment signal data of the symbol that needs to be displayed during the operation is read out and stored. By sending display data of the symbols obtained to the display unit, the necessary symbols can be displayed even during execution of calculations.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of essential parts for explaining this embodiment, and FIG. 2 shows a liquid crystal display section of this embodiment. In addition, the symbol symbols G, R, D, S in Fig. 2
D and RD are common signal line C0M0 and segment signal line 5
The liquid crystals corresponding to any combination of EG1 to EG60 are configured to be driven and displayed.

In Figure 1, 1 is a RAM that stores input data, calculation results, and information necessary for liquid crystal display, and 2 is a RAM.
This is a DISP control unit that accesses MI to read out data necessary for display and also controls various parts necessary for display.

During the display mode, the DISP control unit 2 controls the access address of the RAMI by using the switching gates 3a and 3b.
Switch to the SP address side and address the display data. The display data read from the RAMI by the DISP control unit 2 is sent to the latch 5a via shift registers 4g and 4b, which are shifted by 4 bits by shift signals CIA and CKB of the DISP control unit 2.

5b, and is latched by the latch signal CKF of the DISP control section 2. Also,
The latched display data is sent from display drive buffers 6a and 6b to segment signal lines 5EGI to 5EG60 of the liquid crystal display section shown in FIG. 2 at necessary timings.

FIGS. 3(a) and 3(b) show the display drive buffer 6a described above.
.

6b and its detailed structure are shown.

These display drive buffers 6a, 6b are 5EG-CONT
If the signal is High (1), the output O is equal to the input IN
If UT is obtained and the 5EG-CONT signal is Low (0), the output OUT will be 5EG- regardless of the state of the input IN.
This is the OFF level.

Further, display timing signal lines RO to R7 from the DISP control unit 2 are connected to common signal lines C0M0 to C0M7 of the liquid crystal display unit shown in FIG. 2 via a display drive buffer 7 for common drive of the liquid crystal. .

FIGS. 4(a) and 4(b) show symbols of the display drive buffer 7 and their detailed structure. When the input IN of this display drive buffer 7 is High (1), the output OUT becomes the C0M-0N level, and the input IN becomes Low.
If it is (0), the output OUT will be at the C0M-0FF level.

Further, the display timing signal line RO of the DISP control unit 2 passes through an inverter 8 and forms an input of a NAND gate 9 together with the DISP OFF output line.
The output of this NAND gate 9 is the display drive buffer 6a.
, 6b is connected to the 5EG-CONT line.

In the circuit of the embodiment configured as described above, in the display mode, the C0NT output of the DISP control unit 2 becomes Low, the switching gates 3a and 3b are switched to the DISP address side, and the RAM is controlled by the DISP address.
The display data of I is read out, and shift registers 4a and 4 are activated by shift signals CKA and CKB synchronized with address changes.
b is sequentially shifted and the display data is latched 5a.

Distribute to 5b. When the display data is distributed to the last stage, a latch signal CKF is outputted from the DISP control unit 2, and the distributed display data of numbers and symbols are latched in the latches 5a and 5b.

In this display mode, the DISPOFF signal of the DISP control unit 2 is Low, so the N
Since the output 5GE-CONT of the AND gate 8 is High, the display drive buffers 6a and 6b are connected to the input IN.
The output corresponding to the segment signal line 5EG1 of the liquid crystal display section
~Send to 5EG60.

At this time, since the display drive buffer 7 is set to C0M-0N, the display timing RO to R7 is changed to the common signal lines C0M0 to C0M of the liquid crystal display section in accordance with the timing change.
7, and the liquid crystal display section is driven and displayed with one cycle from display timing RO to R7.

FIG. 5 is a timing chart showing the timing relationship of each part in each mode of this embodiment, and the timing in the above-mentioned display mode is shown in the timing division of the display mode in the same figure.

Next, the display mode shifts to the calculation mode.

When the DISP OFF command is executed,
Enter symbol display preparation mode. In this mode,
As shown in the symbol display preparation mode classification in FIG.
The C0NT output of the ISP control unit 2 remains low as in the display mode, so
The address signal line for RAMI is connected to the DISP control unit 2, and in this mode, the access address is changed to the address of symbol data to be displayed during calculation. Also, in this mode, the DI
DISPOFF signal of SP control section 2 is High
Therefore, the output of NAND9 is determined by the state value of display timing RO.

In this symbol display preparation mode, the states other than those described above are the same as in the display mode, so the symbol display data necessary during the execution of calculations in the RAMI is transferred to the latches 5a and 5b in the same manner as in the display mode described above. Latched.

When this latch operation is completed, the C0NT output of the DISP control unit 2 is set to High, and the calculation mode shown in the calculation mode classification in FIG. 5 is set.

As a result, the switching gates 3m and 3b switch the address of the RAMI to a normal operation address for executing an operation, and the operation is executed with a CPU (not shown).

In this mode, the DISP control unit 2 stops the shift signals CKA, CKB and the latch signal CKF. For this reason, the latch 5a.

The symbol display data latched in 5b is held during this calculation mode.

Also, during this calculation mode, the display timing RO is Hi.
Only when the voltage is gh, the output of the NAND gate 9 becomes High, and the output of the display drive buffer 6g.

6b is opened, the symbol display data latched by the latches 5a and 5b is sent to the liquid crystal display section, and the liquid crystal display for the desired symbol is displayed at the timing shown in FIGS. 6(a) and 6(b), that is, the display timing. Drive display is performed intermittently at the repeating timing of RO.

The display drive buffers 5a and 5b have a display timing RO of H
Since it is opened only when it is high, that is, only to the common signal line C0M0, the numeric part is not displayed while the calculation is being executed.

Note that this invention is not limited to the above embodiments.

It can be modified and implemented without changing the gist.

[Effects of the Invention] According to the present invention, the operating status can be displayed even during execution of calculations without complicating the circuit configuration, and the anxiety of the user can be eliminated.

[Brief explanation of the drawing]

Figure j11 is a circuit diagram mainly consisting of the display function section of an embodiment of the present invention, Figure 2 is an explanatory diagram of the surface mounting and driving signal lines of the liquid crystal display section of this embodiment, and Figure 3 (a) ( b) is the symbol symbol and configuration circuit diagram of the display drive buffer for driving the liquid crystal segment, FIG. 4 (a) and (b) is the symbol symbol and configuration circuit diagram of the display drive buffer for the common signal line of the liquid crystal, and FIG. 6 is a timing chart of each part in each mode of this embodiment, FIG. 6 is a display drive timing chart for the liquid crystal during calculation execution, and FIG. 7 is a circuit diagram explaining the RAM usage pattern of a conventional small electronic calculator of this type. . 1...RAM 2...DISP control unit 3a, 3b...Switching gates 4a, 4b...Shift registers 5a, 5b...Latch 6a, 6b...Display drive buffer 7...Display drive Buffer 8... Inverter 9...
・・NAND Gate Applicant Representative Patent Attorney Takehiko Suzue Figure 3 Figure 4

Claims (1)

[Claims] A display unit that drives and displays numbers and symbols using a combination of a plurality of common signals and a plurality of segment signals;
In a small electronic calculator equipped with a storage means for storing display data displayed on the display unit and calculation data, a combination of a specific one of the common signals and at least one specific of the segment signals is provided. at least one symbol display section to be displayed, a latch means for storing the segment signal data, a means for causing the latch means to read and store symbol display data from the storage means before execution of an operation, and during execution of an operation: A small electronic calculator comprising means for sending symbol display data stored in the latch means to the symbol display section in synchronization with the specific common signal.