JPH04206B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is capable of weighing a plurality of objects (hereinafter referred to as lumps) that vary in individual weight, such as confectionery, fruits, vegetables, etc., so that the weight is approximately constant. This invention relates to a combination selection circuit for a combination weighing machine, which is used when bulking items into bags.

Even if an attempt is made to group together a set weight of lumps whose individual weights vary, an error will occur between the set weight and the target weight. For this reason, a combination weighing machine has conventionally been used to always reduce the error from the set weight as much as possible and group the weights together.

In this type of conventional combination weighing machine, a plurality of lumps are _{sequentially supplied to a plurality of weighing hoppers 11 to 1o ,} as shown in Fig. The stored objects to be weighed are each weighed according to 2 ₁ to 2 _o . And each measuring instrument 2 ₁ ~
2 Input the measured value of _o into the combination selection circuit 3, and
Combination of taking one piece from the weighing hopper _o C ₁ to n
Calculate the combination weights for all combinations up to the combination _o C _o . Then, from among all the combination weights obtained through calculation, the combination of weighing hoppers that has the smallest difference from the target weight is selected and grouped together. However, this combination calculation is performed by inputting each measured value at a constant timing through serial control and calculating the values in sequence.

However, in this method, for example, the weighing hopper 1 ₁ ,
When the four combination weights of 1 ₂ , 1 ₃ , and 1 ₄ have reached the target weight, the other combination weights including 1 ₁ , 1 ₂ , 1 ₃ , and 1 ₄ are 1 ₁ , 1 ₂ , and 1 . Since the weight is always greater than the combined weight of 1 ₁ , 1 ₂ , 1 3 , _and 1 4 , all other combination operations involving 1 1 _, 1 2 , 1 ₃ , and 1 ₄ are useless. Similarly, for example, if the combined weight of the three weighing hoppers 1 ₁ , 1 ₃ , 1 ₈ reaches the target weight, 1 ₁ , 1 ₃ , 1
Since the other combination weights including ₈ are always larger than the combination weights of 1 ₁ , 1 ₃ , and 1 ₈ , all other combination calculations including 1 ₁ , 1 ₃ , and 1 ₈ are useless. However, in conventional combination selection circuits, all combinations are calculated as described above, so even after a target value is reached with a certain combination of three, for example, other measured values must be sequentially input and calculated. First, it had the disadvantage that the calculation time was extremely long.

As a technology to solve this problem,
As disclosed in Publication No. 57-141517, after dividing a plurality of measured values into groups and calculating all combined weights within the group in advance, a combination calculation is performed between the groups, and during the calculation, the combined total is calculated. Some systems were configured to move to calculations using other combinations when the value exceeds a target value.

However, this technology requires a large number of memories to store all weighing values and combined weight values within a group, resulting in an extremely large configuration and a large amount of time required to control it. There is a problem.

SUMMARY OF THE INVENTION An object of the present invention is to correct the above-mentioned drawbacks and provide a combination selection circuit for a combination weighing machine that has an extremely simple configuration and shortens calculation time.

An embodiment of the present invention shown in the drawings will be described below.

FIG. 2 shows an embodiment of the invention.

In the same figure, 11 ₁ to 11 _o are weighing hoppers 1 ₁
~1 _o are storage circuits that store measurement value signals from the weighing instruments 2 ₁ to 2 _o for measuring the weight of objects to be weighed, respectively, 12 ₁ to 12 _o are switch groups, and 13 is a switch group 12 ₁ to 12 _o to select switch groups 12 ₁ to 12 _o based on the combination pattern.
This is a switch control circuit that turns on each switch one by one.

The switch control circuit 13 includes a line selection shift register 1 in which "1" is shifted from 1 to n and outputted from output terminals 1 to n for each clock input.
4, a combination pattern creation counter 15 that increments a binary number by 1 for each clock input, with 1 being the least significant digit from the output terminals 1 to n, and a line selection shift register 14 and a combination pattern creation counter 15. and an AND gate group 16 which calculates the AND of the outputs of each of 1 to n and turns on the switch groups 12 ₁ to 12 _o , respectively. 17 to 19 constitute an arithmetic circuit of the present invention, 17 is a target weight setting circuit for setting a target weight, and 18 is input from a value temporarily stored in a register 19 via switch groups 12 ₁ to 12 _o . A subtracter 19 that sequentially subtracts the measured value of one of the storage circuits 11 ₁ to 11 _o to be stored first stores the target weight of the target weight setting circuit 17 via a switch 20 and outputs it to the subtracter 18, and then subtracts it. 23 is a register 19 which also serves as a determination circuit that stores the output value of the circuit 18 via a switch 21 and outputs a polarity detection signal "1" to the NOR circuit 22 when the stored value becomes negative.
A zero detection circuit outputs a zero detection signal "1" to the NOR circuit 22 when the stored value is zero; 24 is the NOR circuit 2;
2 and the pulse signal ψ ₂ are input, and when the stored value of the register 19 is not zero or negative, the pulse signal ψ ₂ is passed through and the switch 21 is turned on.

25 is a switch 2 which stores the maximum value preset in the maximum value setting circuit 26 via a switch 27 and is turned on when the AND circuit 28 outputs "1".
This is an old result storage circuit that updates and stores the absolute value of the value stored in the register 19 via the register 19.

30 compares the absolute value of the stored value of the register 19 with the absolute value of the stored value of the old result storage circuit 25, and if the value stored in the register 19 is smaller, the output is sent to the AND circuit 28.
is a comparator that results in

31 is an AND circuit into which the pulse signal ψ ₃ and the output of the NOR circuit 22 are input via the inverter 32;
28 is an AND circuit into which the outputs of the comparator 30 and the AND circuit 31 are input, and outputs a signal for turning on the switch 29 and a latch signal to the combination storage circuit 36;
33, when the output of the AND circuit 31 or the overflow output of the line selection shift register 14 is input, this input signal is used as a pattern update signal,
This OR circuit serves as a pattern update circuit that outputs to the clock input terminal of the combination pattern creation counter 15 and the load input terminals of the shift registers 14 and 34.

Reference numeral 34 denotes a shift register for selecting a combination result, which outputs an increment of "1" in the direction from 1 to n from the output terminals 1 to n every time a clock is input; 35, a counter 15 for creating a combination pattern; and a shift register 34 for selecting a combination result. 36 is a group of AND gates that takes the logical product of each 1 to n output of the AND gate group 35 when the output "1" of the AND circuit 28 occurs.
This is a combinational storage circuit that latches the output states of n output terminals.

37 is an inverter to which the carry output of the combination pattern creation counter 15 is input; 38 is an inverter to which the output of the inverter 32 is input; 39 is to which the inverters 37, 38 and the pulse signal ψ ₁ are input;
While the outputs of the inverters 37 and 38 are "1", an AND circuit inputs the pulse signal ψ ₁ to the clock input terminals of the shift registers 14 and 34, and 40 is an overflow output of the shift register 14 for line selection and a counter 15 for pattern creation. This is an AND circuit that calculates the AND of the carry outputs and outputs the END signal. Note that line selection shift register 1
The overflow output of No. 4 is input to the OR circuit 33 and is also used as a signal to turn on the switch 20.

As shown in FIG. 3, the pulse signals ψ ₁ , ψ ₂ , and ψ ₃ have the same frequency but are out of phase.

Next, the operation of the above embodiment will be explained.

(1) The weights of the objects to be weighed supplied to the weighing hoppers ₁₁ to _1o are weighed by the scales ₂₁ to _2o , respectively, and the measured values are stored in the storage circuits ₁₁₁ to _11o, respectively.

The combination pattern creation counter 15 is initially set by the start signal, and all outputs of 1 to n become "0". Further, the switch 27 is turned on by this start signal, and the maximum value is stored in the old result storage circuit 25. Further, the switch 20 is turned on by the overflow output of the line selection shift register 14 at the end of the previous cycle, and the target weight of the target weight setting circuit 17 is stored in the register 19. Further, this overflow output is inputted to the load input terminals of the combination result selection shift register 34 and the line selection shift register 14 via the OR circuit 33, so that the shift registers 34 and 14 are initially set and the output terminals 1 and 1 of both shift registers 34 and 14 are initially set. only “1”, others “0”
It's getting old.

(2) Since the target weight, which is a positive value, is stored in the register 19 as described above, the output of the NOR circuit 22 is "1". Therefore, the inverter 38
The output of is "1". Further, since the carry output of the combination pattern creation counter 15 is "0", the output of the inverter 37 is also "1". Therefore, the pulse signal ψ ₁ is generated by the AND circuit 39
The clock signal is inputted to the clock input terminals of the shift registers 14 and 34 through the input terminal.

Therefore, the line selection shift register 14
The output is “1” in response to the pulse signal ψ ₁ .
is shifted from output terminal 1 to the n side. Further, the output of the combination result selection shift register 34 increases by one from the output terminal 1 to the n side in response to the pulse signal ψ ₁ .

(3) Therefore, the combination pattern creation counter 1
Since the outputs of the AND gate 16 are all "0", all the outputs of the AND gate 16 are "0". Therefore, all of the switch groups 12 ₁ to 12 _o remain off. Therefore, the weighing signals from the memory circuits 11 ₁ to 11 _o are not input to the subtracter 18, so
The contents of the register 19 hold the target weight.

(4) After the output terminal n of the line selection shift register 14 becomes "1", the overflow output becomes "1" at the next clock input, and this overflow output is sent to the shift registers 14 and 3 through the OR circuit 33. It is input to the load input terminal of the counter 15 to initialize it, and at the same time, it is input to the clock input terminal of the counter 15 to increment the contents of the counter 15 by one.

(5) In this way, each time the overflow output "1" is input, the counter 15 is incremented by one from 1 in binary, and the output state changes as shown in FIG.

(6) For example, if the output of the counter 15 is "1" at only the output terminals 1, 2, 4, 5, 8, etc. as shown in FIG. 5b, then the output of the shift register 14 is "1". ” is shifted from output terminal 1 to n, so when output terminal 1 is “1”, the AND gate group 16 switches 12
Turn on ₁ . Then, the measured value stored in the memory circuit ₁₁₁ is input to the subtracter 18 and is stored in the register 1.
9 is subtracted from the target weight stored in 9.
Since the value stored in the register 19 is a positive value, the output of the NOR circuit 22 is "1", so the pulse signal ψ ₂ passes through the AND circuit 24 and turns on the switch 21. Therefore, the subtraction result from the subtractor 18 is used in the register 19 instead of the target weight.
to be memorized.

Next, when the output terminal 2 of the shift register 14 becomes "1", the switch ₁₂₂ is turned on and the measured value stored in the storage circuit ₁₁₂ is similarly subtracted from the contents of the register 19. Output terminals 4, 5, ... are "1"
A similar subtraction is performed each time.

(7) Then, when subtraction is performed sequentially and, for example, the output terminal 5 of the shift register 14 becomes "1" and the measured value in the memory circuit ₁₁₅ is further subtracted, the contents of the register 19 become zero or negative. Then, the zero detection signal "1" is output from the zero detection circuit 23 or the polarity detection signal "1" is output from the register 19, and the output of the NOR circuit 22 becomes "0".
Thereafter, the AND circuit 24 no longer passes the pulse signal ψ ₂ to the switch 21 .

The contents of register 19 are compared by comparator 30 with the maximum value stored in old result storage circuit 25. If the absolute value of the output value of the register 19 is small, an output is produced from the comparator 23. Furthermore, when the zero detection signal or polarity detection signal is output, the output of the inverter 32 input to the AND circuit 31 becomes "1", so the pulse signal ψ ₃ passes through the AND circuit 30 and an output is generated from the AND circuit 28. Therefore, the switch 28 is turned on and the output value of the register 19 is stored in the old result storage circuit 25, and the contents of the combination storage circuit 36 are latched. The AND gate group 35 outputs the logical product of the output of the combination pattern creation counter 15 and the output of the combination result selection shift register 34 to the combination storage circuit 36 . Since the output of the shift register 34 is incremented by 1 from output terminals 1 to 5 as shown in FIG. 5c, the combinational storage circuit 36 has a subtracter 18 as shown in FIG. Output terminal 1 of AND gate group 34 corresponding to the weighing hopper input to
A state in which 2, 4, and 5 are "1" and the others are "0" (ie, a combination of weighing hoppers 1 ₁ , 1 ₂ , 1 ₄ , and 1 ₅ ) is stored.

(8) Also, when the zero detection signal or polarity detection signal is output, the output of the inverter 32 becomes "1", so the output of the inverter 38 becomes "0", and the pulse signal ψ ₁ is passed through the AND circuit 39. It will not pass. At the same time, the output "1" of the AND circuit 31 is changed to the OR circuit 3 by the pulse signal ψ _3.
3 to the load input terminals of the shift registers 14 and 34 for initial setting, and input to the clock input terminal of the combination pattern creation counter 15 to increment the contents by 1. Furthermore, when the shift register 14 is initially set, an overflow output occurs and the switch 20 is turned on.
The target weight is stored in the register 19 again.

(9) Once the target weight is stored, the zero detection signal or polarity detection signal is no longer output, so the output of the inverter 38 becomes "1". Also, AND circuit 2
4 will be deregulated. Therefore, the pulse signal ψ ₁
is passed through the AND circuit 39 to the shift register 1
The pulse signal ψ 2 is input to the clock input terminals 4 and 34, and the pulse signal ψ ₂ is input to the switch 2 through the AND circuit 24.
Turn on 1.

Therefore, as the output "1" of the shift register 14 is shifted from the output terminal 1 in the n direction, based on the combination of the output state of the counter 15 increased by 1 as shown in FIG. Each metric value is sequentially subtracted until the contents of register 19 become zero or negative.

(10) In this way, every time the counter 15 increases by 1, the shift register 14 scans and subtracts, and when the subtraction result becomes zero or negative, it is compared with the old result in the comparator 29, and if the absolute value is small, The output value of the register 19 is stored in the old result storage circuit 25.
The combination is updated and stored in the combination storage circuit 36.

(11) In this way, subtraction and comparison are performed until all output terminals of the counter 15 become "1",
When the count is further increased by 1 and a carry output of 1 is generated from the counter 15, an overflow output of "1" from the shift register 14 is generated, and an END signal is output from the AND circuit 33, and the combination selection is completed.

(12) As a result, the plurality of weighing hoppers according to the combinations finally latched in the combination storage circuit 36 are released, and the objects to be weighed discharged from them are grouped together. After being discharged, the weighing hoppers are again supplied with the objects to be weighed, a start signal is generated again, and the next combination is selected.

In the above embodiment, the objects to be weighed that are supplied to the weighing hopper are combined, but the hopper of the present invention may be of any type as long as it can accommodate and discharge the objects to be weighed, and may be directly connected to the weighing instrument. It is not limited only to the weighing hopper. Further, in the above embodiment, the calculation is terminated when the result of subtraction from the target weight becomes zero or negative in the calculator, but as shown in FIG. 7, the adder 41
The comparator 43 compares the addition result stored in the register 42 with the target weight set in the target weight setting circuit 17, and determines whether the addition result is equal to or greater than the target weight. By using the output "1" of the comparator 43 that occurs when the circuit is in the same state as the zero detection signal or the polarity detection signal in the embodiment described above, it is also possible to operate the circuit in the same way as the circuit shown in FIG.

As explained above, in the combination selection circuit of the combination weighing machine of the present invention, in the combination calculation of the weighing values of the objects to be weighed of each hopper, if the total value of the combination reaches the target value, the hopper of the combination is included. Since there is no need to perform all other combinational calculations, calculation time can be significantly reduced, and the number of memories can be reduced by
Only a few pieces are required for calculation, the configuration is extremely simple, and the control can be done in a short time.

[Brief explanation of drawings]

Fig. 1 is a schematic configuration diagram showing a combination selection device for a conventional combination weighing machine, Fig. 2 is a block diagram showing an embodiment of the present invention, and Fig. 3 shows pulse signals ψ ₁ , ψ ₂ ,
ψ ₃ time chart, Figure 4 is a diagram showing the output status of the combination pattern creation counter, Figure 5 is a diagram showing an example of the output status of terminals 1 to n, and column a in the figure shows line selection. shift register 14, b
The column shows the state of the combination pattern creation counter 15, the c column shows the state of the combination result selection shift register 34, and the d column shows the state of the combination storage circuit 36. Figure 6 shows the combination pattern creation counter 15 that has increased by 1.
FIG. 7 is a block diagram showing another embodiment of the present invention. 1 ₁ - 1 _o ... Weighing hopper, 2 ₁ - 2 _o ... Measuring instrument, 3 ... Combination selection circuit, 11 ₁ - 11 _o ... Memory circuit, 12 ₁ - 12 _o ... Switch group, 13 ...
Switch control circuit, 14... Line selection shift register, 15... Combination pattern creation counter, 16... AND gate group, 17... Target weight setting circuit, 18... Subtractor, 19... Register,
23...Zero detection circuit, 25...Old result storage circuit,
26... Maximum value setting circuit, 34... Shift register for selecting combination results, 35... AND gate group,
36...Combination memory circuit.

Claims (1)

[Scope of Claims] 1. n memory circuits that store measurement value data of objects to be measured measured by a plurality of measuring instruments; and selection signals for the n memory circuits are input to the first stage each time a clock signal is input. a line selection shift register that sequentially shifts and outputs one by one up to n stages; a combination pattern creation counter that outputs the count output as an n-bit combination pattern signal; the output of the line selection shift register; and the combination pattern signal. Outputting the bit-to-bit logical product with the pattern output of the pattern creation counter sequentially selects and outputs the measurement value data corresponding to the combination pattern output from among the measurement value data stored in the storage circuit. Each time it receives weighing value data selected and output one by one from the switches according to one combination pattern, the total value or the difference between this total value and a predetermined target value is digitally calculated. an arithmetic circuit that performs calculations; a determination circuit that receives a calculation result calculated each time the measurement value data is input in the calculation circuit and determines that the sum of the measurement value data has become larger than the target value; and the line selection. and a pattern update circuit that inputs a signal indicating that a shift of the shift register for use in the transfer circuit has completed one cycle, or a judgment signal from the judgment circuit to the count input terminal of the pattern creation counter as a pattern update signal. Combination selection circuit.