JPH04212077A - Semiconductor measuring device - Google Patents

Abstract

PURPOSE:To enable a data for outputting a test pattern and an object file of an expected value from a loaded memory to be read and converted to a source file in a specified format and then to be transplanted to another device easily. CONSTITUTION:An address generator 2, an I/O pattern memory 3, an I/O switching control 4, a mask memory 5, and a data reading device 14 are connected by switches 15-18. Then, as in an actual logic function test, a timing generator 1 and a generator 2 are operated and data is output in sequence from the memories 3-5. The device 14 reads these data through the switches 16-18 and stores data by updating and address in sequence every time an address signal from the generator 2 is changed. Also, the device 14 converts it into a standard source file which can be used easily for another semiconductor measuring device based on the read data. It is stored in an external memory device such as a disk and transplant to another device can be made easily.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor measuring device for testing the logic functions of semiconductor integrated circuits.

0002

2. Description of the Related Art FIG. 6 is a block diagram showing the configuration of one terminal of a logic function test section in a conventional semiconductor measuring device of this type. As shown in the figure, the output of a timing generator 1 that generates basic timing for a logic function test is input to an address generator 2 that generates an address signal. Further, the output of the address generator 2 is input to the input/output pattern memory 3, the I/O switching control memory 4, the mask memory 5,
It is input to the PASS/FAIL output section 6.

The input/output pattern memory 3 stores an input pattern (test pattern) to be input to a semiconductor integrated circuit under test (not shown) and a pattern that should be output from the semiconductor integrated circuit under test when the input pattern is applied. The output pattern (expected value) is memorized. The I/O switching control memory 4 inputs an input pattern to the semiconductor integrated circuit under test;
Switching is performed between outputting test result data from the semiconductor integrated circuit under test. The mask memory 5 stores a mask pattern for masking a specific portion of the measurement result obtained by comparing the test result data from the semiconductor integrated circuit under test with an expected value by the comparator 10. The measurement results are recorded in the measurement result recording section 12 for all patterns. The PASS/FAIL output section 6 outputs pass or fail information from the contents of the measurement result recording section 12 to the outside together with information on the fail pin and the failed pattern address.

Furthermore, the output of the timing generator 1 is also given to the control input of a phase generator 7, and this phase generator 7 executes the basic phase of the logic function test based on the basic timing generated by the timing generator 1. generate. The input/output pattern from the input/output pattern memory 3 is sent to the phase generator 7.
The formatter 8 inputs the data format into, for example, RZ (Return to Zero) or N
It is matched with the semiconductor integrated circuit under test by converting it to RZ (non-return-to-zero). The output of the formatter 8 is given to an input of a driver 9 and one input of a comparator 10. Further, the output of the driver 9 is applied to a test terminal 11, and the test terminal 11 is connected to a semiconductor integrated circuit under test (not shown).

[0005] Also, the test terminal 11 is connected to a comparator 10.
is connected to the other input terminal of the comparator 10.
The output is input to the measurement result recording section 12. Further, the output of the I/O switching control memory 4 is applied to the control terminals of the driver 9 and comparator 10 in order to control their activation and deactivation.

In addition, the reference voltage source 13 is used to match the input and output levels of the driver 9 and comparator 10 with those of the semiconductor integrated circuit under test.
0 reference voltage terminal.

Next, the operation will be explained. The address generator 2 sequentially generates address signals based on the basic timing output from the timing generator 1. This address signal is input to the input/output pattern memory 3, I/O switching control memory 4, mask memory 5, and PASS/FAIL output section 6. In response to the address signal, input/output patterns, I/O switching control data, and mask patterns are sequentially read out from the input/output pattern memory 3, I/O switching control memory 4, and mask memory 5, respectively.

The input/output pattern read from the input/output pattern memory 3 is applied to an input of a driver 9 and one input of a comparator 10 via a phase generator 7 and a formatter 8. At the same time, I/O switching control data output from the I/O switching control memory 4 is applied to the control terminals of the driver 9 and the comparator 10.

The driver 9 has I applied to its control terminal.
In the mode activated by the /O switching control data, test pattern data is applied to the semiconductor integrated circuit under test via the driver 9 and the test terminal 11. At this time, the comparator 10 becomes inactive by the I/O switching control data applied to its control terminal.

Conversely, in a mode in which the comparator 10 is activated by the I/O switching control data applied to its control terminal, the comparator 10 is activated by the expected value data applied to one of its input terminals and the test terminal 11.
It compares the test result data from the semiconductor integrated circuit under test that is applied to the other input terminal via the input terminal, and outputs the measurement result to the measurement result recording section 12. At this time, the driver 9 becomes inactive due to the I/O switching control data applied to its control terminal.

If the measurement result is not masked by the mask data input from the mask memory 5, the measurement result recording section 12 stores the measurement result as it is in the mask memory 5.
If the pattern is masked by the mask data input from the pattern, the measurement result is regarded as OK and recorded for all patterns, regardless of the content of the measurement result.

The PASS/FAIL output section 6 outputs pass or fail information to the outside, along with information on the fail pin and the failed pattern address, depending on the contents of the measurement result recording section.

[0013]

SUMMARY OF THE INVENTION Since the conventional semiconductor measuring device is constructed as described above, it has the following problems. That is, the contents of memories such as the input/output pattern memory 3, the I/O switching control memory 4, and the mask memory 5 are written in a source language specific to this semiconductor measuring device. Generally, before actual measurement, the exact contents of memory are finally determined by debugging an object file generated from a source language. In this case, even if the semiconductor measurement equipment has a function to convert an object file into a source file, that is, a decompiler function, by decompiling it using the decompiler function, the contents of the memory can be converted into a source language specific to this semiconductor measurement equipment. However, it is difficult to directly port it to other semiconductor measurement devices with different source languages.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to obtain a semiconductor measuring device in which the contents of a memory such as an input/output pattern memory can be easily transferred to another semiconductor measuring device. It is an object.

[0015]

[Means for Solving the Problems] A semiconductor measuring device according to the present invention inputs a test pattern to a semiconductor integrated circuit,
In a semiconductor measurement device that tests the logical function of a semiconductor integrated circuit by comparing data output from the semiconductor integrated circuit according to a test pattern with an expected value, a memory loaded with an object file of the test pattern and the expected value; It is configured to include a data reading device that reads test pattern and expected value data output from this memory and converts it into a source file in a predetermined format.

[0016]

[Operation] In this invention, the data output from the memory into which the test pattern and expected value object files have been loaded is read by the data reading device and converted into a source file in a predetermined format. By using files that are applicable or easy to apply to other semiconductor measurement devices as much as possible, it becomes easy to port this source file to other semiconductor measurement devices.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing the configuration of one terminal of a test section in a semiconductor measuring device according to an embodiment of the present invention. As shown in the figure, a data reading device 14 for reading data to be output during a logic function test in the same order as when executing the logic function test is connected to a switch 15 for switching to the data reading device 14. The address generator 2, the input/output pattern memory 3, the I/O switching control memory 4, and the mask memory 5 are connected via 18, respectively. The rest of the configuration is the same as that in FIG. 6, so the explanation will be omitted.

Next, the operation will be explained. During normal testing, the address generator 2, input/output pattern memory 3, I/O switching control memory 4, mask memory 5, and data reading device 14 are insulated by switches 15 to 18. The operation in this case is the same as described above with reference to FIG. 6, so the explanation will be omitted.

Next, the switches 15 to 18 are used to control the address generator 2, input/output pattern memory 3, I/O switching control memory 4, mask memory 5, and data reading device 1.
A case will be explained in which 4 is connected. Note that the switches 15 to 18 may be turned on in the same way as normal tester control (ie, programming).

In this mode, an actual logic function test is not performed, but the timing generator 1 and address generator 2 are operated in the same way as during the actual logic function test.
Data is sequentially output from the input/output pattern memory 3, the I/O switching control memory 4, and the mask memory 5. The data reading device 14 reads these data via the switches 16 to 18, respectively, updates the address sequentially every time the address signal from the address generator 2 changes, and stores the data.

The data reading device 14 has an input/output pattern memory 3, an I/O switching control memory 4, and a mask memory 5.
The timing to read the contents of may be the timing actually used for the test, but since this timing may be at an extremely high frequency (for example, 50 MHz), the timing generator 1 is different from the timing actually used for the test. The data reading device 14 may read data at a low speed by slowing down the basic timing signal to be generated and slowing down the operation of the semiconductor measuring device. By doing this, the switch 15
There is no need to prepare a special one for high frequencies as 1 to 18, and a general switch can be used, making it extremely easy to apply the invention.

FIGS. 2 to 5 are data image diagrams showing a series of data strings in this embodiment. First, the source file image in FIG. 2 shows source files for pattern control data, input/output pattern memory 3, I/O switching control memory 4, and mask memory 5 that are created in advance for actual testing. . Here, the pattern control data is stored in the address generator 2 and is data for determining in what order addresses are to be generated based on the basic timing from the timing generator 1.

In the example of FIG. 2, the pattern control data is executed from address 2 to address 5 after executing address 1.
Since the address generator 2 is programmed to repeat twice twice and then execute address 6 and subsequent addresses, after generating address 1, address generator 2 repeats addresses 2 to 5 twice and then generates addresses 6 and subsequent addresses.

The source file shown in FIG. 2 is converted into an object file shown in the object file image in FIG. 3 using a compiler normally installed in the semiconductor measuring device, and then stored in the input/output pattern memory 3, I/O Loaded into the switching control memory 4 and mask memory 5. Debugging is then performed to determine the final memory contents. The steps up to this point are those performed in normal testing.

In this embodiment, as described above, the final memory contents are sequentially output from the input/output pattern memory 3, the I/O switching control memory 4, and the mask memory 5, and the data reading device 14 outputs them in parallel. and read it. Figure 4
is the data image read by data reading device 14. The data image read by the data reading device 14 is the object file shown in FIG.
Addresses 1 to 5 shown in the image are the same, but starting from address 6, addresses 2 to 5 are repeated again, and then address 7 appears, resulting in a so-called solid writing description.

The data reading device 14 also reads the data in the input/output pattern memory 3, I/O switching control memory 4, and mask memory 5 based on the data read in, for example, as shown in FIG.
The source file is converted into a standard source file that can be easily used in other semiconductor measurement devices as shown in FIG. 2, and is stored in an external storage device (not shown) such as a disk.

As this standard source file, one is selected that has a format that is as easy to apply to other semiconductor measuring devices as possible. For example, in the example shown in FIG. 5, the address generator 2 does not have a loop based on the pattern control data shown in FIG. In addition, in the mask memory 5, the unmasked bit positions shown in FIG. 2 are expressed as "0", but the masked bit positions are expressed as "M" instead of "M" It is expressed as “1”.

Note that the method of representation in the input/output pattern memory 3 and the I/O switching control memory 4 is the same as that shown in FIG. That is, in the input/output pattern memory 3, what is designated as input by the I/O switching control data (test data) is expressed as "0" and "1", and the I/O
The output (expected value) specified by the /O switching control data is expressed as "L" and "H", and in the I/O switching control memory 4, the input is "I" and the output is "O". It is expressed as.

In other general semiconductor measurement equipment, by creating a source file for the semiconductor measurement equipment based on a standard source file stored on an external disk or the like, or by using the standard source file if possible. The same test can be performed by applying the source file directly. It is relatively easy to create a source file for a specific semiconductor measuring device from the standard source file.

As explained above, the object files generated by compiling the source language specific to the semiconductor measuring device are read by the data reading device 14 in the same order as they are output when executing the logic function test, and Since the data is converted into a standard source file that is easily applicable to other semiconductor measurement devices, it is easy to port this source file to other semiconductor measurement devices.

[0031] If this data reading device 14 is provided in a semiconductor measuring device that does not have the function of converting an object file into a source file, another advantage is that this conversion function can be added.

[0032]

As described above, according to the present invention, a test pattern is input to a semiconductor integrated circuit, and data output from the semiconductor integrated circuit according to the test pattern is compared with an expected value to determine whether the semiconductor integrated circuit In semiconductor measurement equipment that tests the logic functions of a semiconductor device, a memory loaded with test pattern and expected value object files and a reading device that reads the test pattern and expected value data output from the memory and converts it into a source file in a predetermined format. By using a predetermined format that is applicable or easy to apply to other semiconductor measurement devices, it is possible to easily port this source file to other semiconductor measurement devices. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a semiconductor measuring device showing an embodiment of the present invention.

FIG. 2 is a diagram showing an example of data used in the semiconductor measuring device according to the present invention.

FIG. 3 is a diagram showing an example of data used in the semiconductor measuring device according to the present invention.

FIG. 4 is a diagram showing an example of data used in the semiconductor measuring device according to the present invention.

FIG. 5 is a diagram showing an example of data used in the semiconductor measuring device according to the present invention.

FIG. 6 is a block diagram showing a conventional semiconductor measuring device.

[Explanation of symbols]

1 Timing generator 2 Address generator 3 Input/output pattern memory 4 I/O switching control memory 5 Mask memory 11 Test terminal 14 Data reading device 15-18 Switch

Claims (1)

[Claims] 1. A semiconductor measuring device that inputs a test pattern to a semiconductor integrated circuit and compares data output from the semiconductor integrated circuit with an expected value according to the test pattern to test the logical function of the semiconductor integrated circuit. And,
A semiconductor comprising a memory loaded with an object file of the test pattern and the expected value, and a data reading device that reads data of the test pattern and the expected value output from the memory and converts it into a source file in a predetermined format. measuring device.