JPH0422344B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a hot electron transistor (hereinafter referred to as HET).

[Summary of the invention]

The present invention provides an alloy electrode structure in HET in which the emitter barrier layer is provided extending over the base electrode extraction part, and the base electrode is alloyed through the extended part of the emitter barrier layer.
The aim is to simplify manufacturing and reduce the base width (base thickness), thereby improving transportation efficiency, reducing base series resistance, and improving reliability.

[Conventional technology]

Conventionally, normal HETs are, for example, n-type low resistivity ones, as shown in a schematic enlarged cross-sectional view in Figure 4.
A collector 2 made of an n-type GaAs layer on a GaAs substrate 1, a collector barrier layer 3 made of a non-doped AlGaAs layer on top of this, a base 4 made of an n-type GaAs layer, and a collector 2 made of a non-doped AlGaAs layer. An emitter barrier layer 5 and an emitter 6 made of an n-type GaAs layer are sequentially laminated.

7, 8 and 9 indicate a collector electrode, a base electrode and an emitter electrode, respectively. E, B and C indicate its emitter, base and collector terminals, respectively.

In the HET with this configuration, the emitter terminal E is grounded and +Vcc is applied to the collector terminal C. Then, by applying a predetermined on-voltage V _BE between each emitter-base terminal E-B, the majority carriers (electrons) are injected from the emitter 6 into the base layer 4. FIG. 5 is a model diagram showing the energy level at the bottom of the conduction band of this HET, and in the figure, the chain line indicates the Fermi level B _F. FIG. 5A schematically shows a state in which no voltage is applied to each terminal. FIG. 5B is a model showing a state in which a voltage Vcc is applied between the emitter terminal E and the collector terminal C, with the collector C side being positive. Furthermore, in FIG. 5B, the broken line indicates a state in which no voltage is applied between the emitter terminal E and the base terminal B. The solid line in the figure shows a state in which a required on-voltage V _BE for correcting the base side is applied between the emitter and the base. When the voltages Vcc and _VBE are applied, as shown by the solid line in FIG. This carrier is injected into the base layer 4. In this case, the emitter barrier layer has a barrier height such that a thermionic emission current can be ignored compared to a tunnel current. At this time, when the on-voltage V _BE is applied, electrons with large kinetic energy, so-called hot electrons, injected into the base head toward the collector, but at this time, some of these electrons are scattered in the base. As a result, the electrons change direction, lose energy, and fall to the bottom of this base conduction band, which becomes the base current I _B. Other electrons that cross the collector barrier layer and reach the collector become the collector current I _C. At this time, the emitter current I _E
is I _E = I _B + I _C , and the current gain β is β = I _C / I _B. Note that when the voltage V _BE is not applied between BE and E, the carriers injected from the emitter layer to the base layer decrease. At the same time, the height of the barrier of the collector barrier layer against the injected carriers increases, thereby blocking the carriers toward the collector, thereby suppressing the collector current I _C . Therefore, depending on the voltage applied to the base B, the transistor is turned on and off in the same manner as in a normal transistor.

To manufacture an HET with such a structure, normally first, a collector 2, a collector barrier layer 3, a base 4, an emitter barrier layer 5, and an emitter 6 are sequentially formed on a substrate 1.
Each semiconductor layer is grown using, for example, metal organic chemical vapor deposition (MOCVD).
Continuously formed by CVD process (Vapor Deposition). Next, the emitter 6 on the lead-out portion of the base electrode 8 relative to the base 4 and the emitter barrier layer 5 below this are partially removed. This partial elimination of the emitter 6 and the emitter barrier layer 5 results in
First, the emitter 6 is etched away by dry etching that allows flat etching, such as reactive ion etching using CCl ₂ F ₂ gas or CCl ₂ F ₂ +He gas, and then the emitter barrier is removed by wet etching or dry etching. A method is used in which the layer 5 is removed to expose the base electrode extraction portion of the base 4 to the outside.

In this dry etching, the etching speed of the emitter barrier layer 5 made of AlGaAs is extremely slow, about 1/200 of that for the emitter 6 made of GaAs. When the depth of etching reaches the emitter barrier layer 5, the etching apparently stops or suddenly stops, so if dry etching is stopped at that point, the emitter 6 can be removed reliably and selectively as a flat surface. If wet etching or dry etching is subsequently performed on the emitter barrier layer 5, the surface of the base electrode extraction portion of the base 4 will be much smaller than when wet etching is performed on both the emitter 6 and the emitter barrier layer 5. can be exposed as a relatively flat surface.

However, even in the case of such a method, it is difficult to remove the emitter barrier layer with good controllability, and it is inevitable that some degree of uneven etching progresses, that is, unevenness of the etched surface occurs.

Therefore, the thickness of the base 4 must be selected to be about 500 to 1000 Å so that the etching does not penetrate through the base 4 at the extraction portion of the base electrode.

In addition, a depletion layer due to surface levels spreads on the surface of the base 4 exposed to which the base electrode 8 is actually attached, and this causes the base electrode 8 and the operating region of the base, that is, the portion directly below the emitter 6, to The substantial width (thickness) between the two is narrowed by the surface depletion layer, which increases the base series resistance, so from this point of view as well, the thickness of the base 4 cannot be made sufficiently small. Therefore, in this type of HET, there are restrictions on reducing the base width of the base 4, and the carrier transport efficiency here cannot be sufficiently increased, resulting in the problem that the aforementioned current gain β cannot be sufficiently improved. be.

[Problem that the invention seeks to solve]

As mentioned above, in conventional HETs, it is not possible to make the base width sufficiently small, or if the base width is made small, the reliability may decrease due to penetration at the base electrode extraction part, or the base series resistance may increase. There are problems such as compatibility.

In the present invention, these problems are solved and the base width is made sufficiently small to improve the current gain and current amplification factor that increases the carrier transport efficiency to the collector. The object of the present invention is to provide a semiconductor device, particularly an HET, which can avoid a decrease in reliability and an increase in base resistance despite the above-mentioned characteristics.

[Problem that the invention seeks to solve]

Referring to FIG. 1, a semiconductor device according to the present invention, namely
Explain HET. In FIG. 1, parts corresponding to those in FIG. 3 are given the same reference numerals.

In the present invention, an emitter barrier layer 5 and a collector barrier layer 3 are provided between an emitter 6, a base 4, and a collector 2 in a semiconductor device, that is, an HET, on a portion of the base 4 on which a base electrode is attached, that is, on a base electrode extraction portion. Emitsuta barrier layer 5
The base electrode 8 is formed by an alloy electrode which is formed by extending the base electrode 8 on the extending portion 5a to a depth that penetrates through the entire thickness of the extending portion 5a and reaches the base 4.

[Effect]

According to the HET according to the above-described structure of the present invention, the emitter barrier layer 5 is extended to the base 4 where the base and the electrode 8 are attached, that is, the base electrode extraction part, which makes it easy to manufacture this HET. All selective etching is performed only on emitter 6,
Since etching is not necessary for the emitter barrier layer 5, it can be eliminated only by the selective dry etching mentioned at the beginning, and furthermore, by controlling the concentration of the emitter barrier layer, the surface of the base 4 can be removed from the outside. The effect of the surface depletion layer caused by exposure to water can be reduced.
The thickness of the base 4 can be reduced to a sufficiently small thickness of 200 Å or less, for example, about 100 Å, thereby increasing the carrier transport efficiency and increasing the current gain and current amplification factor.

〔Example〕

Further, referring to FIG. 1, the HET according to the present invention will be explained in detail. In this example as well, for example, an n-type low resistivity GaAs substrate 1 is provided, and on this
A 3000 Å thick n-type GaAs semiconductor layer doped with Si, for example, which constitutes the collector 2, and a 1500 Å thick semiconductor layer made of, for example, non-doped Al _0.35 Ga _0.65 As, which constitutes the collector barrier layer 3 on top of this. On top of this, for example, a 300 Å thick Si-doped n-type GaAs semiconductor layer forming the base 4, and further above this a 120 Å thick undoped Al _0.35 Ga forming the emitter barrier layer 5. A _0.65 As semiconductor layer and a 300 Å thick Si-doped n-type GaAs semiconductor layer constituting the emitter 6 are epitaxially grown on this layer by MOCVD in one operation. Thereafter, the GaAs layer of the emitter 6 on the surrounding base electrode extraction part is selectively etched by a well-known dry etching process, for example, with CCl ₂ F ₂ or CCl ₂ F ₂ , leaving the central transistor operating area.
Remove with +He gas. In this case, by applying dry etching, i.e. emitter 6
Utilizing the difference in etching speed between the GaAs of the emitter barrier layer 5 and the AlGaAs of the emitter barrier layer 5, only the emitter barrier layer 5 is selectively removed. A layer extension 5a is formed. Even though the surface of the extended portion 5a of the emitter barrier layer 5 from which the emitter 6 has been removed is partially dry-etched, the composition AlGaAs of the emitter barrier layer 5 and the composition of the emitter 6 may be removed as described above. By utilizing the difference in etching speed with GaAs, it is possible to easily perform etching that selectively and reliably removes only the emitter 6 and reliably leaves the emitter barrier layer 5. When dry etching is performed, the surface of the extending portion 5a exposed by removing the emitter 6 is left as a flat surface, in other words, the extending portion 5a is left with uniform thickness at each portion.

Moreover, the emitter 6 and the back surface of the board 1 have respective
An emitter electrode 9 and a collector electrode 7 having a multilayer structure of Au/AuGe/Ni are ohmicly deposited.

In particular, in the present invention, an Au/AuGe/Ni metal electrode is similarly alloyed as the base electrode 8 on the extending portion 5a to a depth that penetrates through the extending portion 5a and reaches the base 4, thereby achieving an ohmic structure. Conktat.

FIG. 2 shows the grounded emitter transistor characteristics with the base current I _B as a parameter in this HET, and a grounded emitter current amplification factor β of 2.0 or more is obtained. In this case, the emitter area is 80μm
At ×40 μm and 77K, β was found to be approximately 1.6 or more.

In each of the above-described examples, the HET has an emitter structure having a heterojunction structure, but by making the emitter a shot-key junction structure, the etching process for extracting the base electrode described above can be omitted. An example of this case is shown in FIG. In FIG. 3, parts corresponding to those in FIG. 1 are given the same reference numerals, and redundant explanation will be omitted as much as possible. In this case, continuously on the substrate 1,
The collector 2, the collector barrier layer 3, the base 4, and the emitter barrier layer 5 are grown epitaxially, but the semiconductor layer constituting the emitter 6 is not formed, and the collector electrode 7 and the base electrode 8 are first alloyed, respectively. These electrodes 7 and 8 are made of, for example, Ni,
It has a multilayer structure of Au/AuGe/Ni, in which AuGe and Au are sequentially deposited, and is alloyed at approximately 420°C in an H ₂ atmosphere. Next, an emitter electrode 9 made of a vapor-deposited layer of Schottky metal such as Au is placed on the emitter barrier layer 5.
form. In this case as well, the base electrode 8
The extending portion 5a of the emitter barrier layer 5 is present in the portion where the emitter barrier layer 5 is to be formed, so that even if the base 4 has a sufficiently small thickness, an ohmic electrode can be provided on the base.

In addition, in the above example, GaAs/
This is a case where the present invention is applied to an HET with an AlGaAs/GaAs/AlGaAs/GaAs structure or a metal/AlGaAs/GaAs/AlGaAs structure, but
HET For example, the base is doped with In and GaAs (or metal)/AlGaAs/InGaAs/AlGaAs/GaAs
The structure has a low base resistance. HET according to Japanese Patent Application No. 59-224090 filed by the present applicant,
Or InGaAs (or metal)/InP/InGaAs/
The present invention can also be applied to HETs with an InP/InGaAs structure. Further, in the above-mentioned example, the emitter barrier layer is formed of a non-doped layer, but in some cases, it may be doped with an appropriate impurity, and various other changes may be made.

[Effects of the Invention] As described above, in the present invention, the extension portion 5a in which the emitter barrier layer 5 is extended to the attachment portion of the base electrode to the base 4, that is, the base electrode extraction portion.
By forming an emitter barrier layer to prevent the base 4 from being directly exposed to the outside between the transistor operating section immediately below the emitter and the base electrode 8, the concentration of the emitter barrier layer can be controlled. Since it is possible to suppress the generation of a surface depletion layer between the transistor operating region immediately below, the expansion of this depletion layer causes the narrowing of the current path between the transistor operating region and the base electrode, and the resulting Increase in base resistance can be suppressed.

In addition, when the manufacturing process involves an etching process for the semiconductor layer forming the emitter 6, for example, and when the base electrode 8 is alloyed to the base 4, even if the thickness of the base 4 is reduced, an emitter barrier is formed at the base electrode extraction part. Extension 5 of layer 5
By extending a, the inconvenience of the etching penetrating through the base 4 can be avoided, so that the thickness of the base 4 can be formed to be 300 Å or even smaller as in the above example. This makes it possible to increase the carrier transport efficiency to the collector, thereby improving the current gain and therefore the current amplification factor, and obtaining a highly reliable HET despite reducing the thickness of the base 4. The benefits of doing so are huge.

When the emitter is formed by Schottky bonding as in the example explained in FIG. 3, selective etching is avoided, and manufacturing can be simplified and planarized, making it advantageous to integrate the emitter into an integrated circuit.

[Brief explanation of drawings]

FIG. 1 is a schematic enlarged cross-sectional view of an example of a semiconductor device according to the present invention, FIG. 2 is a characteristic curve diagram of a grounded emitter transistor thereof, and FIG. 3 is a schematic enlarged cross-sectional view of another example of a semiconductor device of the present invention. FIG. 4 is a schematic enlarged sectional view of a conventional semiconductor device, and FIG. 5 is an energy band model diagram thereof. 1 is a substrate, 2 is a collector, 3 is a barrier layer, 4 is a base, 5 is an emitter barrier layer, 5a is an extension thereof, 6 is an emitter, 7 is a collector electrode, 8 is a base electrode, and 9 is an emitter electrode.

Claims (1)

[Claims] 1. In a semiconductor device having an emitter barrier layer and a collector barrier layer between an emitter, a base, and a collector, the emitter barrier layer extends over the base electrode extraction portion of the base, and the base electrode extends over the extending portion of the emitter barrier layer. A semiconductor device comprising an alloy electrode that penetrates and reaches the base electrode extraction portion of the base.