JPH0423424B2 - - Google Patents

Description

Detailed Description of the Invention The present invention relates to an insulated gate field effect transistor (hereinafter, MISFET-Metal-
Insulator Semiconductor Field Effect
Transistor- refers to. ) and a capacitor provided on the same substrate.

For example, Switched
In the capasitor) circuit, a pair of N-channel MISFETs are installed on one main surface of a common silicon substrate.
Formed as one constituent element, and paired MOS
The basic configuration is that a capacitor provided on the field SiO ₂ film adjacent to the MISFET is connected between the ground level and the MISFET. This actually constitutes a filter by being built into the input side of an operational amplifier.

By the way, in this filter circuit, the ratio ( _Cf /
C ₁ ) determines its frequency characteristics and gain (output voltage/input voltage = V ₂ /V ₁ ). The above capacitor usually uses a poly-Si film created in the same process as the MISFET poly-Si gate electrode as the lower electrode, and is patterned at the same time as the poly-Si gate electrode, after which impurities are introduced using the poly-Si gate electrode as a mask. It is formed by doping the same impurity into the poly-Si film when forming the source and drain regions by ion implantation (for example, ion implantation). Therefore, the bottom electrode of the capacitor is
It consists of a poly-Si film doped with the same impurity species and the same concentration as the source and drain regions of the MISFET.

However, since the lower electrode obtained in this manner is formed to have an impurity concentration of only about 10 ¹⁹ /cm ³ , which is the same as that of the source and drain regions, it has been found that this is not sufficient as a poly-Si film for an electrode.
In other words, if a capacitor is created by laminating a dielectric film (SiO ₂ film) and an upper electrode (aluminum electrode) on the lower electrode, the low concentration of poly-Si in the lower electrode causes A depletion layer extends into the poly-Si film from the interface with the dielectric film, and the capacitance due to this depletion layer enters in series with the original capacitance.

As a result, the capacitor capacitance changes in response to voltage fluctuations, which causes the ratio (Cf/C ₁ ) itself to fluctuate, making it unusable for circuits that require relative accuracy. . For example, the above-mentioned filter circuit has disadvantages in that its frequency characteristics change, and its output voltage (V ₂ ) is distorted, resulting in a deterioration of the S/N ratio.

Therefore, an object of the present invention is to reduce the voltage dependence of a capacitor as described above, increase its relative accuracy, and improve circuit characteristics. The gist of the present invention for achieving this object is that impurities are introduced into the semiconductor substrate on both sides of a gate electrode made of a polysilicon material, thereby forming source and drain regions in self-alignment with the gate electrode. A semiconductor device comprising: an insulated gate field effect transistor; and a capacitor formed by laminating a second electrode material layer on a first electrode material layer made of the same material as the gate electrode with a dielectric film interposed therebetween. A manufacturing method, wherein a field oxide film is formed to surround an element formation region in which the insulated gate field effect transistor is to be formed on a main surface of a semiconductor substrate, and the element in which the insulated gate field effect transistor is to be formed is formed. forming a gate oxide film thinner than the field oxide film in the formation region; depositing a polysilicon film so as to cover the entire surface of the gate oxide film and the field oxide film; patterning the polysilicon film; After forming a gate electrode of an insulated gate field effect transistor on the gate oxide film and a first electrode material layer of a capacitor on the field oxide film, form source and drain regions of the insulated gate field effect transistor on the entire surface. a step of introducing an impurity into the first electrode material layer of the capacitor by covering the gate electrode and the source and drain regions of the insulated gate field effect transistor with a mask; selecting an impurity having the same conductivity type as the source and drain regions; 1. A method of manufacturing a semiconductor device, comprising the steps of:

Embodiments of the present invention will be described in detail below with reference to the drawings.

The structure of the semiconductor device according to this example will be explained along the manufacturing process for easy understanding. First, as shown in FIG. field of
After forming the SiO ₂ film 2 and further forming the gate oxide film 3, polySi is deposited on the entire surface using CVD (chemical vapor deposition technology).
A film 4 is applied.

Next, as shown in FIG. 1B, the poly-Si film 4 is patterned by photoetching and processed into the gate electrode 5 of the MISFET and the lower electrode 6 of the capacitor, and then an ion beam 7 of N-type impurity (for example, As) is applied to the entire surface. irradiate. As a result, an impurity concentration of 10 ¹⁹ /cm ³ is applied to both sides of the gate electrode 5 as a mask.
At the same time, the same impurity (for example, (As)) is doped into the poly-Si film 6 to a concentration of about 10 ¹⁹ /cm ^{3 .} So, that poly Si
Reduce the resistance of the film 6 (make it N ⁺ type). Note that the resistance of the gate electrode 5 is also reduced by doping with the same impurity.

Next, as shown in FIG. 1C, the MISFET section is selectively covered with a photoresist 10, and using this as a mask, an ion beam 7 of an N-type impurity (for example, As) is irradiated to introduce the impurity into the poly-Si film 6. Increase quantity. As a result of this additional impurity introduction process, the poly-Si film 6 becomes N ⁺⁺ type with an impurity concentration of about 10 ²¹ /cm ³ (concentration at or near the solid solubility limit),
It exhibits a sufficiently low resistance value as the lower electrode of a capacitor.

Next, as shown in FIG. 1D, the phosphor glass film 11 formed on the entire surface by CVD is photoetched to remove the portion above the upper and lower electrodes 6, and then heat treatment (for example, in dry O 2 ) in an oxidizing atmosphere (especially dry O ₂ ) is performed. 1000℃,
75 minutes) to oxidize the exposed surface of the poly-Si film 6, and then a SiO ₂ film 12 as a dielectric film is oxidized thereon by, for example, 800 〓
Grow to a thickness of .

Next, as shown in FIG. 1E, the phosphor glass film 11 is processed by photoetching to form openings 13 and 14 on the source and drain regions, and the first F.
As shown in the figure, each aluminum electrode (or wiring) 15, 16, 17 is formed by patterning aluminum deposited by vacuum evaporation technique by photo etching.

The device obtained as described above is used, for example, in the switched capacitor circuit shown in FIG. In the diagram, C ₁ is the above capacitor, Q ₁ to _{Q 4} are pairs
The above MISFET is used as a MOS.

In the element structure according to this example, the capacitor
The lower electrode 6 of _C1 has an impurity concentration several orders of magnitude higher than that of the source and drain regions because impurities are further introduced in the step of FIG. 1C. Therefore, when operating as a capacitor, the dielectric film 1
Since the depletion layer is difficult to extend from the interface with 2 into the poly-Si film 6, and the depletion layer capacitance is small even when the voltage changes, the overall capacitor capacitance (C ₁ )
fluctuations will be suppressed. Therefore, the above-mentioned ratio (Cf/C ₁ ) can always be maintained at a constant value, and when used in a filter circuit, the frequency characteristics can be improved, and the S/N ratio can also be improved.

In this way, without changing the characteristics of MISFET,
Since the voltage dependence of the capacitor can be reduced, MIS type circuits that require capacitors with high relative accuracy can be realized.

In this sense, it is applicable not only to the above-mentioned switched capacitor circuit but also to, for example, a weighted capacitor circuit. In a weighted capacitor circuit, the output voltage characteristics (i.e., A/
D or D/A conversion accuracy) is determined, but for the same reason as mentioned above, each conversion accuracy is improved because the voltage dependence of the capacitor is small.

Further, according to the present invention, since the capacitor is formed on a thick field insulating film, stray capacitance between the semiconductor substrate and the capacitor can be reduced, and the capacitor can be completely insulated from the substrate.

Note that the process of introducing impurities into the poly-Si film 6 may be performed by other methods, such as a vapor phase diffusion method, or
Alternatively, the type of impurity introduced may be changed (for example, P-type impurity may be introduced). Alternatively, the gate electrode 5 described above may be formed of a first layer of poly-Si, and the lower electrode 6 of the capacitor may be formed of a second layer of poly-Si. Furthermore, the upper electrode 17 of the capacitor may be formed of poly-Si.

[Brief explanation of drawings]

1A to 1F are cross-sectional views showing a semiconductor device according to an embodiment of the present invention in the order of manufacturing steps, and FIG. 2 is a circuit diagram of an example of its application. 5... Gate electrode, 6... Lower electrode, 7... Impurity ion, 8, 9... Source or drain region, 12... Dielectric film, 17... Upper electrode.

Claims (1)

[Claims] 1. An insulated gate field effect transistor in which source and drain regions are formed in self-alignment with the gate electrode by introducing impurities into a semiconductor substrate on both sides of a gate electrode made of a polysilicon material; A method for manufacturing a semiconductor device comprising a capacitor formed by laminating a second electrode material layer on a first electrode material layer made of the same material as the electrode with a dielectric film interposed therebetween, the method comprising: A field oxide film is formed to surround an element formation region where an insulated gate field effect transistor is to be formed, and a gate oxide film thinner than the field oxide film is formed in the element formation region where the insulated gate field effect transistor is to be formed. a step of depositing a polysilicon film so as to cover the entire surface of the gate oxide film and the field oxide film; and a step of patterning the polysilicon film to form an insulated gate field effect transistor on the gate oxide film. After forming a gate electrode and a first electrode material layer of a capacitor on the field oxide film, a step of introducing impurities to form the source and drain regions of the insulated gate field effect transistor on the entire surface; A step of selectively introducing impurities having the same conductivity type as the source and drain regions into the first electrode material layer of the capacitor by covering the gate electrode and the source and drain regions of the field effect transistor with a mask. A method for manufacturing a semiconductor device.