JPH0423452B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a decoding device, and particularly to a decoding device, in particular, a decoding device that decodes an equivalent code bit obtained by erasing code bits at a specific position from a time series of convolutional code symbols with a low coding rate. The present invention relates to a decoding device that performs maximum likelihood decoding of high coding rate code symbols.

[Conventional technology]

In order to improve transmission quality by correcting transmission errors on a digital transmission path, an error correction method that combines convolutional coding and maximum likelihood decoding is used. The error correction ability of such an error correction method increases as the coding rate becomes smaller (the redundancy becomes higher) and as the code constraint length becomes longer. As the coding rate increases, the number of bits in the code symbol increases. On the other hand, it is known that the hardware size of a decoding device that performs maximum likelihood decoding, such as a Viterbi decoding device, increases exponentially as the number of bits of a code symbol and the code constraint length increase. For wireless transmission channels with strict bandwidth limitations, it is desirable to increase the coding rate to reduce redundancy in the transmission channel as much as possible from the viewpoint of effective use of the bandwidth, and to use an error correction method with high error correction capability. In terms of hardware scale, if the coding rate exceeds 3/4, it becomes prohibitively difficult to implement a Viterbi decoding device.

To solve this problem, we use relatively small hardware scale encoding circuits and decoding circuits for low coding rates, add simple peripheral circuits to these, and convert them to high coding rates on the transmission path. An error correction method has been proposed that uses code symbols with an equivalent high coding rate. (Unexamined Japanese Patent Publication 1987)
−155857). This error correction method, its encoding device, and decoding device will be explained below.

FIG. 4 is a block diagram showing an example of an encoding device used in this error correction method.

The encoding circuit 11 convolutionally encodes the bit string B1, which is a time series of information bits to be transmitted, at a coding rate of 1/2 and a code constraint length of 7, and then convolutionally encodes two code bits constituting one code symbol in parallel. Output as bit strings P1 and Q1. The bit erase circuit 12 erases the bit string.
The code bits at the positions determined by the erasure pattern are erased from P1 and Q1, the speed is converted, and the coding rate is 3/4.
Or the time series of 7/8 code symbols as a bit string
Output as P2 and Q2.

FIG. 5 is an explanatory diagram of erasure patterns, where a shows the case where the coding rate is 3/4 and b shows the case where the coding rate is 7/8.

In the case of a coding rate of 3/4, the 6 code bits (3 code symbols) in 3 consecutive time slots of bit strings P1 and Q1 are represented as shown on the left side of Figure 5a, and the circles in these 6 frames are The pattern at the position of the marked frame is called an erasure pattern. The bit erasing circuit 12 erases the code bits Q12 and P13 marked with circles from the bit strings P1 and Q1, arranges the remaining 4 code bits as shown on the right side of Figure 5a, converts the speed, and outputs them. . The remaining four code bits correspond to three information bits, so they are code symbols with a coding rate of 3/4. In the case of a coding rate of 7/8, as shown in Figure 5b, the 6 code bits marked with a circle are erased from the 14 code bits in 7 consecutive time slots of bit strings P1 and Q1, and the remaining 8 code bits are erased. Rearrange the code bits to create a code symbol with a coding rate of 7/8. As seen in Figure 5, bit string P1
The sign bit of bit string P2 as well as bit string
Since the bits may also be arranged in Q2, the bit erasing circuit 12 performs bit erasing after converting the bit strings P1 and Q1 into series, and then converting them into parallel bits to form the bit strings P2 and Q2.

The time series of received data corresponding to each code bit of the bit strings P2 and Q2 transmitted through the transmission path is decoded by the decoding device as described below.

First, an arbitrary dummy bit corresponding to the code bit erased by the encoding device is inserted into the received data string to create a data string corresponding to the bit strings P1 and Q1. This operation is the reverse operation of the bit erasure circuit 12, and for the same reason that the bit erasure circuit 12 serializes each code bit and then erases the bit, it is necessary to serialize each received data before performing the bit erasure. There is. The dummy bit insertion pattern has a one-to-one correspondence with the erasure pattern, but since the correct phase of the insertion pattern with respect to the (serial) received data string is not known at the time of dummy bit insertion, it is necessary to find the correct phase by trial and error. There are 6 types of insertion pattern phases in the data string into which dummy bits are inserted when the coding rate is 3/4 and 14 types when the coding rate is 7/8, so this phase synchronization (hereinafter referred to as code synchronization) requires If the coding rate is 3/4, a maximum of 6 trials are required, and if the coding rate is 7/8, a maximum of 14 trials are required.
The data string into which dummy bits have been inserted is serially and parallel-converted into two strings. There are two types of frequency division phase uncertainties in serial-parallel conversion of one column and two columns, but conventional decoding devices also perform frequency division phase synchronization to remove this uncertainty by trial and error.

Two data strings corresponding to bit strings P1 and Q1 are Viterbi decoded by a decoding circuit. This decoding circuit is
This circuit is the same as the normal Viterbi decoding circuit corresponding to the encoding circuit 11, except that a constant likelihood value is given to the dummy bit. When inserting a dummy bit into a received data string, a timing signal indicating the insertion position of the dummy bit is generated, and the decoding circuit uses this timing signal to identify the dummy bit from the input data string.

Trials of code synchronization and frequency division phase synchronization are performed as described below.

The bit string decoded and output by the decoding circuit is encoded by the same encoding circuit as the encoding circuit 11, and the example output bits are used as hard decisions (bits indicating) and bits of the data excluding dummy bits in the data string input to the decoding circuit. compare. If code synchronization and frequency division phase synchronization are both correctly achieved, bit comparison will show a match except for transmission errors, so the frequency of mismatch will be extremely small. If at least one of code synchronization or frequency division phase synchronization is incorrect, the frequency of occurrence of mismatch becomes extremely high. When the frequency of mismatches exceeds a certain threshold, code synchronization and frequency division phase synchronization are retried, resulting in a maximum of (6 x 2 =) 12 trials when the encoding rate is 3/4 and 7 times when the encoding rate is 7. /8
In this case, code synchronization and frequency division phase synchronization will definitely be established if a maximum of (14×2=) 28 trials are performed.

After the data input to the decoding circuit is decoded and then encoded by the encoding circuit, it takes approximately 60 bits when the encoding rate is 3/4, and approximately 120 bits when the encoding rate is 7/8. There is a delay. Therefore, it is necessary to delay the hard decision of each data in the data string input to the decoding circuit by this delay before comparing the bits. The hard decision of the data is delayed by a delay circuit consisting of a number of flip-flops equal to the number of delay bits. To eliminate bit comparisons against dummy bits, it is necessary to identify the dummy bits during delayed hard decisions. Conventional decoding devices delay a timing signal generated when inserting a dummy bit using a delay circuit with the same configuration as a hard decision delay circuit, and identify the dummy bit from the delayed hard decision using the timing signal delayed by this delay circuit. ing.

The error correction method described above uses a relatively small scale of hardware, for example, an encoding circuit with a coding rate of 1/2 and an encoding circuit, and adds simple peripheral circuits to these circuits so that, for example, a code It is known that it can be converted and transmitted at a conversion rate of 3/4 or 7/8, and its error correction ability is sufficiently high. In addition, by configuring the encoding device and decoding device so that the erasure pattern can be switched, the optimum encoding rate can be set depending on the transmission path condition, for example, 1/2, 3/4, 7/
It is also possible to use a variable coding rate error correction system in which 8 can be selected.

[Problem that the invention seeks to solve]

The conventional decoding device for the above-mentioned error correction method includes a delay circuit consisting of a large number of flip-flops for delaying the hard decision of the received data string into which dummy bits have been inserted, and a delay circuit having the same configuration as this delay circuit to indicate the insertion position of the dummy bits. Since two sets of delay circuits are used to delay the timing signal, there is a drawback that a large number of flip-flops are required and the configuration becomes complicated.

An object of the present invention is to provide a decoding device with a simple configuration.

[Means for solving problems]

The decoding device of the present invention convolutionally encodes a time series of transmission information bits to obtain a time series of first code symbols, and convolutionally encodes a time series of transmission information bits to obtain a time series of first code symbols that constitute a predetermined number of continuous first code symbols. serially inputting received data corresponding to each of the second code bits constituting a time series of second code symbols obtained by erasing the first code bits at positions determined by the erasure pattern from the group; Controlled by a control signal, synchronizing with the erasure pattern by trial and error, inserting an arbitrary dummy bit at the position where the first code bit has been erased, and outputting it together with a first timing signal indicating the insertion position of this dummy bit. a dummy bit insertion circuit that performs serial-to-parallel conversion on the time series of the received data into which the dummy bits have been inserted and the first timing signal, and converts the time series of parallel data corresponding to the time series of the first code symbols and the a serial-to-parallel conversion circuit that outputs a parallel second timing signal indicating an insertion position of the dummy bit in a time series of parallel data; and a serial-parallel conversion circuit that identifies the dummy bit from the time series of parallel data using the second timing signal. a maximum likelihood decoding circuit that gives a predetermined likelihood value to the identified dummy bits to maximum likelihood decode the time series of the parallel data and outputs a time series of decoded information bits; an encoding circuit that encodes the time series of the decoded information bits into a time series of a third code symbol by the same convolutional encoding as the time series of the first code symbol; a first delay circuit that delays a time series of bits indicating a hard decision of at least one column of data by the delay caused by the maximum likelihood decoding circuit and the encoding circuit; a second delay circuit that delays a column corresponding to the time series of the bits inputted to the first delay circuit by a predetermined time shorter than the repetition period; The dummy bits are identified from the time series of the bits output by the first delay circuit, and each bit of the time series of the bits excluding the identified dummy bit is compared with the corresponding bit of the time series of the third code symbol. However, when the frequency of occurrence of mismatched bits exceeds a predetermined value, the dummy bit insertion circuit is controlled by the control signal to cause the synchronization trial and error to be repeated.

〔Example〕

The present invention will be described in detail below with reference to drawings showing embodiments.

FIG. 1 is a block diagram showing one embodiment of the decoding device of the present invention, and FIG. 2 is a block diagram showing a dummy bit insertion circuit in the embodiment shown in FIG.

In the embodiment shown in FIG. 1, the encoding device shown in FIG. Data string DP1, which is a series,
This is a decoding device that decodes DQ1 and outputs a bit string B2, which is a time series of decoded information bits, and converts the data strings DP1 and DQ1, each of which is 3-bit parallel, into parallel-to-serial conversion to create 3-bit parallel data strings D1 and A clock signal that is the clock for data string D1
A parallel-to-serial conversion circuit 1 outputs CL1, inputs a data string D1, a clock signal CL1, and a control signal CT, and outputs a data string D2 and timing signals T1, T.
A dummy bit insertion circuit 2 that outputs 2 and a data string D2 and timing signals T1 and T2 are input and outputs a data string DP2 and DQ2 and a timing signal.
A serial/parallel conversion circuit 3 that outputs TP, TQ, data strings DP2, DQ2 and timing signals TP,
A Viterbi decoding circuit 4 inputs TQ and outputs bit string B2, an encoding circuit 5 inputs bit string B2 and outputs bit string P3, and a delay circuit 6 inputs the most significant bit string of data string DP2. , an exclusive OR circuit 7 which inputs the output bit string of the delay circuit 6 and the bit string P3, a delay circuit 8 which inputs the timing signal TP, and output signals of the delay circuit 8 and the exclusive OR circuit 7. error counter 9
and a control circuit 10 which inputs the output signal of the error counter 9 and outputs a control signal CT.

The dummy bit insertion circuit 2 receives the clock signal CL.
4 frequency divider circuit 21 that divides 1 into 4, and a clock signal
A divide-by-6 circuit 22 divides the frequency of CL2 by 6, a PLL circuit 23 inputs the output signals of the divide-by-4 circuit 21 and the divide-by-6 circuit 22 and outputs the clock signal CL2, and a PLL circuit 23 which outputs the clock signal CL2. A modulo 6 hexadecimal counter 24 which is controlled to count the clock signal CL2 and output a count value, and a timing signal T2, T which is addressed by the output value of the counter 24.
ROM 25 for reading 3, and a flip-flop 26 for inputting timing signal T3 using clock signal CL2 as a clock and outputting timing signal T1.
, clock signal CL2 and timing signal T
Outputs the logical sum of 3 as clock signal CL3.
The data string D1 is written using the OR circuit 27 and the clock signal CL1 as the write clock, and the clock signal CL1 is used as the write clock.
The FIFO (first in first out) memory 28 reads out the data string D2 using CL3 as a readout clock.

FIG. 3 is a time chart for explaining the operation of the embodiment shown in FIG. The operation of the embodiment shown in FIG. 1 will be explained with reference to FIG.

Received data DP11, DP12 and
DQ11, DQ13 are converted into series by parallel-serial conversion circuit 1, and DP11, DQ11, DP12, DQ
13 are sequentially written into the FIFO memory 28 of the dummy bit insertion circuit 2.

The PLL circuit 23, together with the 4 frequency divider circuit 21 and the 6 frequency divider circuit 22, generates a clock signal CL2 whose synchronization _t2 is 4/6 of the synchronization _t1 of the clock signal CL1 and which is synchronized with the clock signal CL1. ROM25 is the time
Timing signals T2 and T3 having the waveform shown in FIG. 3 are output every _6t2 . Clock signal CL3
As shown in FIG. 3, the number of received data read from the FIFO memory 28 during period 6t ₂ is less than the number of received data written during this period (6t ₂ = 4t ₁ ). It is equal to the number of , which is 4. ,
FIG. 3 shows timing signals T2 and T3 when the initial phase of the counter 24 is correct.
In this case, the received data DP11, DQ every time _t2
11 and DP12 are read out sequentially, and received data DQ13 is read out after a time interval _{of 3t2} . The read reception data DP12 has a time width of _3t2 , but if this is regarded as the reception data DP12, dummy bit QD, and dummy bit PD every time _t2 (the data string D2 in Fig. 3 is ),
This means that dummy bits QD and PD are inserted between the received data DP12 and DQ13. Since the timing signal T1 is a signal obtained by delaying the timing signal T3 by the time _t2 , the position of "1" in the timing signal T1 indicates the insertion position of the dummy bits QD and PD.

The serial/parallel conversion circuit 3 serializes the data string D2 so that the data at the position where the timing signal T2 is "1" is arranged in the data string DP2, and the data immediately following it is arranged in the same time slot of the data string DQ2. Convert in parallel. Data string DP2, DQ
2 corresponds to the bit strings P1 and Q1, as can be seen by comparing FIG. 3 and FIG. 5a. Therefore, the timing signal T2 corresponds to the break between the coding rate 1/2 code symbols in the data string D2. The timing signal T1 is also serial-parallel converted into the timing signals TP and TQ in the same way as the serial-parallel conversion of the data string D2, so the position where the timing signals TP and TQ are "1" is the data string DP.
2. Indicates the insertion position of dummy bits PD and QD in DQ2.

The Viterbi decoding circuit 4 receives timing signals TP,
Dummy bits are identified from data strings DP2 and DQ2 using TQ, a constant likelihood value is given to the identified dummy bits, data strings DP2 and DQ2 are maximum likelihood decoded, and the decoded information bits are output as bit string B2. do. Except for giving a constant likelihood value to the dummy bit, the Viterbi decoding circuit 4
As already mentioned, the same circuit as the normal Viterbi decoding circuit corresponding to the encoding circuit 11 in the figure may be used.

The encoding circuit 5 is the encoding circuit 1 in FIG.
This circuit has exactly the same function as 1, and encodes bit string B2 and encodes bit string P3 and bit string
Output Q3 (not shown). However, bit string Q3
is not used. Data string DP2 (indicates hard decision)
The most significant bit is delayed by a delay circuit 6 by an amount corresponding to the bit delay caused by the Viterbi decoding circuit 4 and the encoding circuit 5, and then compared in bits with the bit string P3 by an exclusive OR circuit 7. Only when the comparison result is a mismatch, the exclusive OR circuit 7 outputs "1". The delay circuit 8 delays the timing signal TP so that it outputs "1" when the delay circuit 6 outputs the dummy bit. The error counter 9 is a counter that counts the number of times the exclusive OR circuit 7 outputs "1", is reset at regular intervals, and stops counting while "1" is being input from the delay circuit 8. be. Therefore, the count value of the error counter 9 indicates the frequency of occurrence of mismatches in the bit comparisons between the hard decisions of the data string DP2 and the bit string P3, excluding the bit comparisons of dummy bits. The control circuit 10 is
When the count value of the error counter 9 exceeds a certain value, the control signal CT controls the counter 24 of the dummy bit insertion circuit 2 to shift its output value by "1".

Now, if the initial value of the counter 24 is greater than the correct value by, for example, "1", the timing signal T3 (and T2) will have a waveform that is ahead of the waveform shown in FIG. 3 by a time _t2 , and in the data string D2. A dummy bit is inserted between received data DQ11 and received data DP12. If a dummy bit is inserted in the wrong position in this way, the data
DP2 and DQ2 no longer correspond to bit strings P1 and Q1, and as a result, the Viterbi decoding circuit 4
decoding errors occur frequently, and the frequency of occurrence of mismatches in the bit comparison by the exclusive OR circuit 7 increases, the output value of the counter 24 is shifted by "1", and the phase of the timing signal T3 is shifted by an amount equivalent to time _t2 . . Since the timing signal T3 is a repetitive signal with a period of _6T2 , by repeating the phase shift by an amount corresponding to the time _t2 six times, all possible phases are taken and the signal returns to the original phase. Since there is a correct phase between these phases, code synchronization can always be achieved by repeating the trial of shifting the output value of the counter 24 by "1" (trial of code synchronization) up to six times.

The timing signal T2 that determines the frequency division phase of the serial-parallel conversion circuit 3 is determined by the output value of the counter 24.
Since it is read out from the ROM 25 together with the timing signal T3 and has a period with the timing signal T3, if the code period in the dummy bit insertion circuit 2 is correct, the frequency division phase synchronization in the serial/parallel conversion circuit 3 is also correct at the same time. As a result, there is no need to repeat trials of only frequency-divided phase synchronization, so the embodiment shown in FIG. 1 also has the effect of shortening the synchronization pull-in time.

Approximately 60 flip-flops are required to configure the delay circuit 6, and the conventional decoding device replaces the delay circuit corresponding to the delay circuit 8 with the delay circuit 6.
I have already mentioned that it has the same configuration as . However, since the timing signal TP delayed by the delay circuit 8 is a repeating signal that repeatedly synchronizes the three time slots of the data string DP2, it is necessary to output the timing signal TP as it is or to use one or two flip-flops. data column
If the timing signal TP is delayed by one time slot or two time slots of DP2 and output, either of these outputs will correctly become "1" when the delay circuit 6 outputs the dummy bit. Therefore, the delay circuit 8 is configured with two or less (including zero) flip-flops.

Above, an embodiment has been described in which a time series of code symbols with a code ratio of 3/4 is created from a time series of code symbols of a convolutional code with a code ratio of 1/2.

Note that when the received data is input in series from a transmission path, the parallel-to-serial converter 1 is not necessary.

In the case of a coding rate of 7/8, the 4 frequency divider 21 is changed to an 8 frequency divider, the 6 frequency divider 22 is changed to a 14 frequency divider, the counter 24 is changed to a hexadecimal counter with a modulus of 14, and the ROM 25 is changed. The ROM is changed to one corresponding to the erasing pattern shown in FIG. 5b. In this case, the delay circuit 8 can be composed of six or fewer flip-flops.

As explained above, the second delay circuit (delay circuit 8 in the embodiment shown in FIG. 1) in the decoding device of the present invention uses the second timing signal (delay circuit 8 in the embodiment shown in FIG. 1) that delays its delay time. In the embodiment shown, the delay time is shorter than the repetition period of the timing signal TP), so that the delay time is the first delay circuit (delay circuit 6 in the embodiment shown in FIG. 1).
For example, if it is made up of flip-flops, it can be made up of far fewer flip-flops than the first delay circuit requires.

〔Effect of the invention〕

As explained above, the decoding device of the present invention has a second
The delay time of the delay circuit is not equal to the delay time of the first delay circuit, but is shorter than the repetition period of the second timing signal that it delays, and is much larger than the delay time of the first delay circuit. Since it is short, the structure of the second delay circuit can be simplified.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the decoding device of the present invention, FIG. 2 is a block diagram showing a dummy bit insertion circuit in the embodiment shown in FIG. 1, and FIG. FIG. 4 is a time chart for explaining the operation of the embodiment; FIG. 4 is a block diagram showing an example of an encoding device in an error correction system in which the present invention is used; FIG. 5 is an explanatory diagram of an erasure pattern; If the coding rate is 3/4, b is the coding rate 7/8
The case is shown below. 1...Parallel-serial conversion circuit, 2...Dummy bit insertion circuit, 3...Serial-parallel conversion circuit, 4...Viterbi decoding circuit, 5...Encoding circuit, 6, 8...Delay circuit, 7...Exclusive OR circuit, 9... error counter, 10... control circuit.

Claims (1)

[Claims] 1. A time series of transmission information bits is convolutionally encoded to form a time series of first code symbols, and first code bits constituting a predetermined number of continuous first code symbols are provided. A second code symbol constituting a time series of second code symbols obtained by erasing the first code bits at positions determined by the erasure pattern from the group of
Serially input received data corresponding to each of the first code bits, synchronize with the erasure pattern by trial and error under the control of a control signal, and insert an arbitrary dummy bit at the position where the first code bit was erased. and a dummy bit insertion circuit that outputs the first timing signal together with a first timing signal indicating the insertion position of the dummy bit; a serial-to-parallel conversion circuit that outputs a time series of parallel data corresponding to a time series of code symbols and a parallel second timing signal indicating the insertion position of the dummy bit in the time series of the parallel data; The dummy bits are identified from the time series of the parallel data using a signal, a predetermined likelihood value is given to the identified dummy bits, the time series of the parallel data is maximum likelihood decoded, and a time series of decoded information bits is output. a maximum likelihood decoding circuit; and converting the time series of the decoded information bits into third code symbols by the same convolutional encoding as the time series of the first code symbols from the time series of the transmitted information bits. an encoding circuit that encodes a time series of bits representing a hard decision of at least one column of the parallel data, and a circuit that delays a time series of bits indicating a hard decision of at least one column of the parallel data by a delay caused by the maximum likelihood decoding circuit and the encoding circuit. a second delay circuit that delays a column of the second timing signal that corresponds to the time series of the bits input to the first delay circuit for a predetermined period shorter than its repetition period; and identifying the dummy bits from the time series of the bits output by the first delay circuit using the output signal of the second delay circuit, and identifying each bit in the time series of the bits excluding the identified dummy bits. The bits are compared with corresponding bits in the time series of the third code symbol, and if the frequency of occurrence of mismatched bits exceeds a predetermined value, the dummy bit insertion circuit is controlled by the control signal to repeat the trial and error synchronization. A decoding device characterized by comprising a control circuit that allows