JPH04239751A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent an electric interference between interconnections by forming a shielding layer at the side of a lower layer interconnection buried in an interlayer insulating film through an insulating film in a self-alignment manner. CONSTITUTION:An insulating film 2, lower layer interconnections 3 are formed on a semiconductor substrate 1. An insulating film 4 of a thickness of half or less of a minimum interval of the interconnections 3 is deposited on the interconnections 3. Then, a shielding layer 5 is deposited, and a photoresist 10 is selectively formed. The layer 5 is etched back by anisotropically etching, and the side of the film 4 and the layer 5 of a region covered with the photoresist 10 remain. As a result, the layer 5 is formed through the film 4 at the interconnections 3 in a self-alignment manner. Then, after an interlayer insulating film 6 is formed, an opening 7 reaching the interconnections 3 and the layer 5 is selectively formed, Al is deposited, and then patterned thereby to form an upper layer interconnection 8 to be connected to the interconnections 3 and the layer 5.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly to a method for manufacturing a semiconductor integrated circuit that prevents electrical interference between adjacent wires in the same wiring layer.

0002

2. Description of the Related Art As semiconductor integrated circuits become faster and more highly integrated, not only elements become finer, but also wiring becomes finer and multilayered.

The manufacturing process of a two-layer wiring according to the prior art will be explained with reference to FIGS. 14 to 16.

First, as shown in FIG. 14, a first insulating film 2 made of a silicon oxide film is deposited by CVD on a semiconductor substrate 1 on which a diffusion layer has been formed, and then openings (not shown) are selectively formed. do.

Next, the lower wiring 3 is formed by depositing aluminum by sputtering or vapor deposition and selectively etching it.

Next, as shown in FIG. 15, an interlayer insulating film 6 made of polyimide or the like is spin-coated and planarized by heat treatment.

Next, as shown in FIG. 16, an opening 7 reaching the lower layer wiring 3 is selectively formed, and a wiring metal is deposited and patterned to form an upper layer wiring 8.

[0008]

Problems to be Solved by the Invention As wiring becomes finer, the width of the wiring approaches the thickness of the wiring, and the distance between adjacent wirings becomes narrower. Therefore, of the parasitic capacitance caused by wiring, the ratio of capacitance between adjacent wirings increases, and the ratio of wirings within the same layer increases, resulting in electrical interference (crosstalk) between wirings.
is occurring.

For example, the lower aluminum wiring has a film thickness of 1.0
μm, width 1.0 μm, and spacing 1.0 μm, 50% of the total parasitic capacitance is in the part that does not intersect with the upper layer aluminum wiring.
The capacitance between adjacent lower layer wirings accounts for the above amount.

0010

[Means for Solving the Problems] A method for manufacturing a semiconductor integrated circuit according to the present invention includes a step of forming a multilayer wiring structure on one main surface of a semiconductor substrate, a step of forming arbitrary wiring except for the uppermost layer wiring; The insulating film is separated by a step of depositing an insulating film on the entire surface with a thickness less than half of the minimum spacing between the wirings, and depositing a conductor to serve as a shield layer on the entire surface and then etching back with anisotropic etching. and leaving a sidewall made of the conductor on the side surface of the wiring.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to the plan view of FIG. 1 and FIGS. 2 to 7, which are sectional views taken along the line AB.

First, as shown in FIG. 2, a first insulating film 2 made of a silicon oxide film is deposited by CVD on a semiconductor substrate 1 on which a diffusion layer has been formed, and selectively opened (not shown).
form.

Next, lower layer wiring 3 is formed by depositing aluminum to a thickness of 1.0 μm by sputtering and patterning it.

Next, as shown in FIG.
An insulating film 4 is deposited.

Next, as shown in FIG. 4, a shield layer 5 made of a tungsten film having a thickness of 0.5 to 1.0 μm is deposited by the CVD method with excellent step coverage.

Next, as shown in FIG. 5, a photoresist 10 is selectively formed.

Next, as shown in FIG. 6, Cl2 /O2
The shield layer 5 is etched back by anisotropic etching using a mixed gas, leaving the side surface of the second insulating film 4 and the shield layer 5 in the area covered with the photoresist 10. A shield layer 5 is formed in a self-aligned manner with respect to the lower wiring 3 with the second insulating film 4 interposed therebetween.

Next, as shown in FIG. 7, after removing the photoresist 10, polyimide is spin-coated and planarized by heat treatment to form an interlayer insulating film 6.

Next, an opening 7 reaching the lower wiring 3 and the shield layer 5 is selectively formed, and aluminum is deposited to a thickness of 1.0 μm and then patterned to connect to the lower wiring 3 and the shield layer 5. Upper layer wiring 8 is formed.

By providing the shield layer 5, the capacitive coupling between adjacent wires can be reduced to 10% or less when the wire width is 1.0 μm and the wire spacing is 1.0 μm.

Next, a second embodiment of the present invention will be described with reference to sectional views of FIGS. 8 to 13.

First, as shown in FIG. 8, a first insulating film 2 made of a silicon oxide film is deposited by CVD on a semiconductor substrate 1 on which a diffusion layer has been formed, and openings (not shown) are selectively formed. .

Next, aluminum 3a having a thickness of 1.0 μm is deposited by sputtering to form the lower wiring.

Next, a third insulating film 9 made of a plasma silicon nitride film having a thickness of 0.5 μm is deposited.

Next, as shown in FIG. 9, after patterning the third insulating film 9 by photolithography, the aluminum 3a is etched using the third insulating film 9 as a mask, thereby forming the lower wiring 3 made of aluminum 3a. do.

Next, a second insulating film 4 made of a plasma oxidized silicon film having a thickness less than half the minimum spacing between the lower interconnections 3 is deposited.

Next, as shown in FIG. 10, the second insulating film 9 is etched back by anisotropic etching such as RIE using CF4, and the lower wiring 3 and the third insulating film 9 are etched back.
The second insulating film 4 is left on the side surface of the second insulating film 4.

Next, the thickness is 0.5 to 1.0 by CVD method.
A shield layer 5 made of a μm thick tungsten film is deposited.

Next, as shown in FIG. 11, a photoresist 10 is selectively formed.

Next, as shown in FIG. 12, the shield layer 5
is etched back to leave the side surfaces of the second insulating film 4 and the shield layer 5 in the area covered with the photoresist 10.

Next, as shown in FIG. 13, after removing the photoresist 10, an interlayer insulating film 6 made of polyimide is formed.

Next, openings 7 reaching the lower layer wiring 3 and the shield layer 5 are selectively formed, and the upper layer wiring 8 connected to the lower layer wiring 3 and the shield layer 5 is formed.

In this embodiment, since the shield layer 5 can cover the bottom of the lower wiring 3, an even better shielding effect can be obtained.

In addition, in both the first and second embodiments, it is sufficient to form contact openings only in the shield layer on the side surfaces of the wiring where crosstalk particularly affects the device characteristics, and contact openings are formed in the other shield layers. There is no need to form.

[0035]

Effects of the Invention: A shield layer is formed in a self-aligned manner on the side surface of the lower layer wiring embedded in the interlayer insulating film, with the insulating film interposed therebetween. As a result, without restricting wiring miniaturization,
We were able to realize highly reliable multilayer wiring without electrical interference (crosstalk) between wirings.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing a first embodiment of the present invention.

FIG. 2 is a sectional view showing a first embodiment of the present invention.

FIG. 3 is a sectional view showing a first embodiment of the present invention.

FIG. 4 is a sectional view showing a first embodiment of the present invention.

FIG. 5 is a sectional view showing a first embodiment of the present invention.

FIG. 6 is a sectional view showing a first embodiment of the present invention.

FIG. 7 is a sectional view showing a first embodiment of the present invention.

FIG. 8 is a sectional view showing a second embodiment of the invention.

FIG. 9 is a sectional view showing a second embodiment of the invention.

FIG. 10 is a sectional view showing a second embodiment of the present invention.

FIG. 11 is a sectional view showing a second embodiment of the invention.

FIG. 12 is a sectional view showing a second embodiment of the invention.

FIG. 13 is a sectional view showing a second embodiment of the invention.

FIG. 14 is a cross-sectional view showing a manufacturing process of a two-layer wiring according to the prior art.

FIG. 15 is a cross-sectional view showing a manufacturing process of a two-layer wiring according to the prior art.

FIG. 16 is a cross-sectional view showing a manufacturing process of a two-layer wiring according to the prior art.

[Explanation of symbols]

1 Semiconductor substrate 2 First insulating film 3 Lower layer wiring 3a Aluminum 4 Second insulating film 5 Shield layer 6 Interlayer insulation film 7 Opening 8 Upper layer wiring 9 Third insulating film 10 Photoresist

Claims (1)

[Claims] Claim 1: A step of forming a multilayer wiring structure on one principal surface of a semiconductor substrate, including the step of forming any wiring except for the top layer wiring, and the step of forming an insulation layer on the entire surface with a thickness of less than half the minimum spacing between the wirings. a step of depositing a film, and a step of leaving a side wall made of the conductor on the side surface of the wiring separated by the insulating film by depositing a conductor to become a shield layer on the entire surface and etching back by anisotropic etching. A method for manufacturing a semiconductor integrated circuit, comprising: