JPH0424732B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a microcomputer having interrupt enable flag bits for controlling enable and disable of interrupts for each of a plurality of interrupt causes.

(b) Conventional technology In general, microcomputers are
Although it has an interrupt function based on multiple interrupt factors such as timer factors, in order to deal with these multiple interrupt factors, the microcomputer is provided with an interrupt request flag and an interrupt permission flag corresponding to each interrupt factor. . Therefore, when a certain interrupt factor occurs, the interrupt request flag corresponding to that factor is set, but in this case, the interrupt is accepted only if the interrupt enable flag corresponding to this factor is set.

On the other hand, some microcomputers are provided with a master interrupt enable flag. The master interrupt enable flag is a flag that controls enabling and disabling all interrupts. In this case, when the interrupt request flag is set due to the occurrence of an interrupt factor, the corresponding interrupt enable flag and the master interrupt enable flag are set. Interrupts are accepted only if the flag is set.

FIG. 2 is a block diagram of the above-mentioned microcomputer, in which interrupt request register 1 a,
b, c are used as interrupt request flags corresponding to interrupt causes A, B, C, and a', b', c' of interrupt enable register 2 are used as interrupt enable flags corresponding to interrupt causes A, B, C. be done. The outputs of the interrupt request flags a, b, and c and the outputs of the interrupt permission flags a', b', and c' are connected to AND gates 3 and 3, respectively.
The outputs of the AND gates 3, 4, and 5 are applied to the interrupt control circuit 6. Further, d' of the interrupt permission register 2 is used as a master interrupt permission flag, and the output of the interrupt permission flag d' is applied to the AND gate 7 together with the output of the interrupt control circuit 6, and the output of the AND gate 7 is used as the master interrupt permission flag. Output as signal INT. Furthermore, the interrupt request register 1 and the interrupt permission register 2 are connected to a bus line 8, and data is set and read therefrom. In particular, writing and reading of the interrupt permission register 2 is performed by a flag set instruction and control signals EI and DI applied during execution of the flag set instruction.

The configuration similar to the microcomputer described above is
It is described on page 40 of the microcomputer data series No. 12B "LC5800 Series User's Manual" published by the applicant on March 1, 1985.

(c) Problems to be Solved by the Invention However, in the microcomputer shown in FIG. 2, the interrupt permission register 2 consists of 4 bits, so the master interrupt permission flag d' is If provided, the interrupt enable flag corresponding to the interrupt factor is limited to 3 bits. Furthermore, since the interrupt request flag also has 3 bits, 1 bit of the interrupt request register 1 consisting of 4 bits becomes vacant, and the usage efficiency of the interrupt request register 1 deteriorates. Furthermore, if the master interrupt permission flag is provided independently in a portion other than the interrupt permission register 2, the number of interrupt factors can be increased, but an instruction to set and reset the master interrupt permission flag is required.

(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned points, and it provides separate interrupt enable flags and master interrupt enable flags corresponding to interrupt factors, and Providing means for detecting that the operands of the flag set and reset instructions have contents that do not affect the contents of the interrupt enable flag,
By setting and resetting the master interrupt permission flag using this means, it is possible to set and reset the master interrupt permission flag without adding any instructions.

(E) Effect According to the above-mentioned means, when an interrupt permission flag setting or setting instruction is executed, the interrupt permission flag specified by the operand is set or reset, but if the operand does not set the interrupt permission flag, If the content is not specified, for example, if each bit of the 4-bit operand is “0”,
The detection means detects that all "0"s are present, and the master interrupt permission flag is set and reset based on the detection output. That is, the master interrupt permission flag is set and reset using an interrupt permission flag set and reset instruction.

(F) Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention. The interrupt request register 9 is composed of 4 bits, and a, b, c, and d correspond to interrupt causes A, B, and
It is used as an interrupt request flag corresponding to C and D, and the interrupt enable register 10 is also composed of 4 bits, and a', b', c', and d' are used for interrupt causes A and D, respectively.
It is used as an interrupt permission flag corresponding to B, C, and D. These interrupt request flags a, b,
Each output of c, d and interrupt enable flags a', b', c',
Each output of d' is connected to an AND gate 11, 12, 1, respectively.
3, 14, AND gates 11, 12,
The outputs of 13 and 14 are applied to an interrupt control circuit 15. The interrupt control circuit 15 sets priorities for each interrupt factor, creates an interrupt vector address corresponding to each interrupt factor, and outputs an interrupt signal INT'.

On the other hand, it is provided separately from the master interrupt enable flag 16, interrupt enable register 10, and interrupt request register 9, and its output is applied to the AND gate 17 together with the interrupt signal INT' of the interrupt control circuit 15, and the output of the AND gate 17 is It is supplied inside the microcomputer as the signal INT.

By the way, the instruction decoder 18
The system inputs instruction codes that are sequentially read from a program memory (not shown) and is applied, decodes the instruction specified by the code, and executes the operation specified by the instruction. Outputs various control signals to. Here, the instruction that operates the interrupt permission register 10, that is, the interrupt permission flag set instruction DIX (mnemonic) or the interrupt permission flag set instruction EIX (mnemonic)
When is applied to the instruction decoder 18, the instruction decoder 18 outputs a control signal EI or DI. This command
In EIX and DIX, the part represented by X is
This is an operand consisting of 4 bits and expressed in hexadecimal. This operand represents the bit to be set or reset in the interrupt permission register 10. For example, if X is "1", it is the interrupt permission flag a', and if X is "2", it is the interrupt permission flag b. If 'X' is "3", interrupt permission flags a' and b' are designated.

In addition, the 4-bit operand included in the instruction code is supplied to the zero detection circuit 19, and the 4-bit operand included in the instruction code is
Or DIX is the instruction decoder 18
When decoded, it is determined whether the operand X is "0" or not, and if it is detected as "0", a detection output MA is output. The detection output MA is applied to an AND gate 20 to which a control signal EI output from the instruction decoder 18 is applied, and an AND gate 21 to which a control signal DI is applied. The output of this AND gate 20 is connected to the set terminal of the master interrupt enable flag 16,
The output of AND gate 21 is connected to the reset terminal. On the other hand, the control signals EI and DI of the instruction decoder 18 are applied to the interrupt enable register 10 via the OR gate 22, and are controlled to write the data sent to the 4-bit bus line 23 into the interrupt enable register 10. do.

Therefore, when the interrupt enable flag set instruction EIX or the interrupt enable flag reset instruction DIX whose operand is not "0" is decoded by the instruction decoder 18, the zero detection circuit 19
Since the detection output MA is at “0” level,
The control signal EI or DI that becomes “1” level is
Interrupt enable register 10 via OR gate 22
instructs to write data. At this time, if the set instruction is EIX, an arithmetic circuit (not shown) calculates the logical sum of the 4-bit data previously held in the interrupt permission register 10 and the operand X, and the result is sent to the bus line. I will send it out on the 23rd. As a result, the interrupt enable flag specified by operand X is set. on the other hand,
When the reset instruction is DIX, the logical product of the inverted 4-bit data held in the interrupt permission register 10 and the operand X is calculated in advance in an arithmetic circuit, and the result is sent to the bus line 23. . As a result, the interrupt enable flag specified by operand X is reset. still,
This arithmetic operation is automatically performed based on the control signal of the instruction decoder 18 in the first half of the instruction cycle in which the instruction EIX or DIX is executed.

Additionally, when instruction EIX with operand X being “0” is executed, instruction decoder 1
Since the control signal EI of 8 and the detection output MA of the zero detection circuit 19 are at the "1" level, the master interrupt permission flag 16 is set by the output of the AND gate 20. On the other hand, when the instruction DIX with the operand
The master interrupt enable flag 16 is reset by the output of the NAND gate 21. If such instruction EIX or DIX is executed, the detection output
Together with MA, the control signal EI or DI goes to the “1” level, and a write operation to the interrupt permission register 10 is performed. At this time, the data held in the interrupt permission register 10 and the “0” of the operand The result of calculating the data in the arithmetic circuit as described above does not change from the data previously held in the interrupt permission register 10, so the status of each interrupt permission flag a', b', c', and d' does not change. do not have.

Even if the master interrupt enable flag 16 is provided independently in this way, the operand X of the interrupt enable flag set instruction EIX and reset instruction DIX
The master interrupt permission flag 16 can be set and reset by entering a value "0" that does not change the contents of the interrupt permission flags a', b', c', and d'.

(G) Effects of the Invention As described above, according to the present invention, it is possible to increase the number of interrupt request flags to the number of bits constituting the interrupt request register, improving register utilization efficiency, and furthermore, the master interrupt Since the permission flag setting and reset instructions are common to the interrupt permission flag setting and reset instructions, there is no need to increase the number of instructions. Therefore, it has the advantage of providing an easy-to-use microcomputer.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional example. 9...Interrupt request register, 10...Interrupt permission register, 11 to 14...AND gate, 1
5... Interrupt control circuit, 16... Master interrupt permission flag, 17... AND gate, 18... Instruction decoder, 19... Zero detection circuit, 20, 21... AND gate, 22... OR gate, 23...Bus line.

Claims (1)

[Claims] 1 A plurality of interrupt enable flag bits corresponding to a plurality of interrupt requests, a master interrupt enable flag that controls enabling and disabling of interrupts for all of the plurality of interrupt requests, and the same number of operands as the plurality of interrupt enable flag bits. In a microcomputer equipped with an instruction to set or reset the interrupt enable flag bit specified by the operand, the plurality of interrupt enable flag bits and a master interrupt enable flag are separately provided, and the operand of the instruction is set or reset. A microcomputer, comprising means for detecting that the content does not affect a permission flag, and the means sets or resets the master interrupt permission flag.