JPH0424779B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a time base corctor for removing a time base error in a signal having a time base error, such as a playback signal of a video tape recorder or an audio tape recorder.

In general, the configuration of this type of time base collector is such that an input signal with a time base error is
The time axis error is removed by writing into the memory using a write clock that has the same time axis error as this input signal, and reading this written input signal using a reference read clock that does not have a time axis error. It has become a thing. By the way, in this case, if you try to read the signal written to the memory immediately, that is, if you make the initial values of the write address and read address the same, the read will be faster than the write due to the time axis error, and the As a result, the read signal will be completely different from the original signal. This phenomenon is generally called memory overflow. Conventionally, in order to prevent the memory from overflowing in this way, the read address is usually delayed by an amount that takes into account the time axis error relative to the write address. If the amount of deviation between the read address and the write address is too large, the memory capacity will increase accordingly, so set an appropriate value that will allow for the maximum time axis error and prevent the memory capacity from becoming too large. It is to be selected.

However, even if the maximum value of the time axis error is taken into account and the amount of deviation between the read address and the write address is taken into account, there may be a large dropout in the reproduced signal, or there may be cases where, for example, external force is applied to the rotating system. , when the servo goes out of order, you will not be able to get a playback signal.
Since this is treated as a time axis error, the memory may still overflow. In other words, input dropouts or variations in the servo system are directly detected as time axis errors.
If this becomes larger than the difference between the memory's write address and read address, the memory will overflow.

Conventionally, in consideration of such overflows such as dropouts, negative feedback is applied to the tape recorder itself before the memory overflows to prevent the memory from overflowing.

In view of the above points, the present invention attempts to propose a system that can prevent memory overflow using only a time base collector without applying negative feedback to the tape recorder.

Hereinafter, some embodiments of the present invention will be described with reference to the drawings.

In FIG. 1, 1 is an input terminal to which an input signal SA having a time axis error, such as a playback signal from a tape recorder, is supplied, and the signal SA through this input terminal 1 is supplied to an A/D converter 2. and is also supplied to the write clock generator 4. The write clock generator 4 obtains a write clock Wck which has a frequency that is more than twice the highest frequency of the input signal and has the same time axis error as the input signal. This writing clock Wck
is supplied to the A/D converter 2, and the input signal
SA is sampled and converted to a digital signal DA. This digital signal DA is supplied to the memory 3. On the other hand, the write clock Wck is supplied to the write address counter 5, and the write address of the digital signal DA to be written into the memory 3 is set, and the digital signal DA is sequentially stored at a predetermined address in the memory 3.

The input signal SA is also fed to a readout clock generator 6, which generates a readout clock Rck which is synchronized to the input signal frequency but is not responsive to the phase or time axis error component of the input signal.
is obtained. In this example, the read clock frequency is assumed to be the same as the write clock frequency.
This read clock Rck is supplied to the read address counter 7, and the information written in the memory 3 is sequentially read out based on the read address information from the read address counter 7.
The read digital signal is supplied to the D/A converter 8. A read clock Rck is supplied to this D/A converter 8, and the read digital signal is returned to the original analog signal.
It is led out to the output terminal 9. In this case, the start value of the read address is shifted from the write address as shown in Figure 2, and the amount of shift is determined to maximize the time axis error in the input signal as described above. has been done. Second
In the figure, for example, the write address is [000...0]
If it starts from , the read address is [100...
...0], that is, the read address is set to start from the center address value of the total capacity of the memory 3. In other words, reading is delayed by that amount.

In the present invention, the following considerations are made in order to eliminate overflows due to dropouts and the like. That is, write address information from the write address counter 5 and read address information from the read address counter 7 are supplied to the subtracter 10. In this subtracter 10, the difference between both address information (digital signals) is taken, and an analog voltage corresponding to the difference is obtained as an output. The output SB of this subtracter 10 is supplied to one input terminal of comparators 11 and 12. Comparator 11
Comparison reference voltages E ₁ and E ₂ are supplied to the other input terminals of 1 and 12, respectively. In this case, for example, E ₁ >E ₂ is satisfied.

The outputs of these comparators 11 and 12 are supplied to a control signal generator 13, and the output clock frequencies of the write clock generator 4 and the read clock generator 6 are controlled by the output of the control signal generator 13. That is, when the difference between the write address and the read address becomes smaller than a predetermined value by the subtracter 10, that is, when there is a risk that the memory 3 will overflow, the write clock frequency and the read clock frequency are simultaneously lowered to effectively reduce the clock frequency. In other words, the capacity of the memory 3 is apparently increased. In this example, this predetermined address difference is divided into two stages, and when the analog voltage SB corresponding to the address difference, which is the output of the subtracter 10, has a value between voltages _E1 and _E2 ,
The write clock frequency and the read clock frequency are set to frequencies slightly lower than the original frequencies, and when the voltage SB becomes lower than the voltage _E2 , the write clock frequency and the read clock frequency are controlled to be even lower frequencies. Ru.

Next, a description will be given of the return to the original clock frequency from a state where the clock frequency has decreased. In FIG. 1, the write address counter 5 and the read address counter 7 have an input terminal 14.
A reset signal SR is supplied from With this reset signal SR, the addresses of both counters 5 and 7 are
At the same time as being reset to the initial value shown in FIG. 2, the voltage SB returns to a value higher than the voltage _E1 , and by the output of the control signal generator 13, the once lowered write clock and read clock frequencies return to their original values. The write clock generator 4 and the read clock generator 6 are controlled to return to the frequency of . Note that the above-mentioned reset is a period in which time axis error correction is not necessary, such as a vertical blanking period in the case of a video signal or a period of synchronization block data in the case of an audio signal, and the reset signal SR in these cases includes: A vertical synchronization signal and a predetermined block synchronization signal are used, respectively.

FIG. 7 shows another embodiment in which the frequencies of the write clock and read clock are restored to their original frequencies. Below, with reference to this Figure 7,
Although other embodiments will be described, parts corresponding to those in FIG. 1 will be denoted by the same reference numerals, and detailed explanation thereof will be omitted.

Here, the counter 15 is a counter that counts a predetermined time from the time when a control signal for lowering the clock frequency is generated from the control signal generator 13, and outputs a reset signal SR. The value of the read address counter 7 is cleared, and the value at which the difference between the write address and the read address is the maximum is set. In other words, this value is a value whose difference is 1/2 the distance of the memory capacity on the address, and the write address counter 5
It is obtained by subtracting the value of 1/2 of the memory capacity from the output using the subtracter 16. In this case, the address before new data is written will be designated as the read address from the memory 3, so the same data will be read twice.

Specific examples of the write clock generator 4 and read clock generator 6 are shown in FIGS. 3 and 4, and the above circuit operation will be explained in more detail.

That is, FIG. 3 shows a specific example of the write clock generator 4, and FIG. 4 shows a specific example of the read clock generator 6.
Examples of specific examples are shown below.

Write clock generator 4 and read clock generator 6 have variable frequency oscillators 45 and 65, respectively. And input terminals 41 and 6
1 is supplied to phase comparators 43 and 63 through gate circuits 42 and 62. The gate circuits 42 and 62 are for gating a typical signal having a time axis error component of the input signal, and an example of a signal extracted as a signal having a time axis error is, for example, when the reproduced signal is a video signal. A color burst signal is used for this. Further, for example, in the case of a PCM audio signal, a block synchronization signal is used. The output signals of the variable frequency oscillators 45 and 65 are supplied to the other input terminals of the phase comparators 43 and 63 after being divided into frequencies equal to those of the signals passed through the gate circuits 42 and 62. The comparison outputs are supplied to variable frequency oscillators 45 and 65 through low-pass filters 44 and 64 to control their oscillation frequencies, and their oscillation outputs are led out to output terminals 40 and 60 through frequency dividers 49 and 69. In this case, the time constant τ ₁ of the low-pass filter 44 is made relatively small, and the variable frequency oscillator 4 is applied to the input signal frequency.
The output frequency of variable frequency oscillator 45 is synchronized with the phase of the input signal. In other words, the output of the variable frequency oscillator 45 is locked to the frequency and phase of the input signal and has a time axis error component of the input signal. On the other hand, the low-pass filter 64 has a relatively large time constant τ ₂ , and therefore the variable frequency oscillator 65
The output signal is synchronized only with the input signal frequency and not with its phase. In other words, although the output signal of the variable frequency oscillator 65 is locked to the frequency of the input signal, it does not have the time axis error of the input signal.

In the present invention, the oscillation frequency of the variable frequency oscillators 45 and 65 is lowered by the signal from the control signal generator 13 as described above when the write address and the read address become less than a predetermined difference. Control. That is, in this example, as frequency dividers for dividing the oscillation outputs of the variable frequency oscillators 45 and 65, frequency dividers 46A and 66A with a frequency division ratio of 1/n, and a frequency divider with a frequency division ratio of 1/n-1 are used. Frequency dividers 46B, 66B and frequency dividers 46C, 66C with a frequency division ratio of 1/n-2 are provided.
The output signals of 46B and 46C are selectively taken out in a switch circuit 47 by a signal from the control signal generator 13 through a terminal 48 and supplied to a phase comparator 43. Further, the output signals of the frequency dividers 66A, 66B, and 66C of the read clock generator 6 are selectively taken out in the switch circuit 67 by the signal from the control signal generator 13 through the terminal 68, and are supplied to the phase comparator 63. be done.

When the difference between the write address information and the read address information is more than a predetermined value, the frequency dividers are selected to be 46A and 66A, respectively, and the signal (frequency f _A ) having a time axis error from the gate circuit 42 and the variable frequency oscillator are selected. The outputs of the variable frequency oscillators 45 and 65 are compared with a signal whose frequency is divided by 1/n, and based on the comparison output, the frequency of the output signal of the variable frequency oscillators 45 and 65 is set to a predetermined frequency according to the frequency division ratio of 1/n. The frequency is controlled to be nf _A.

When the time axis error becomes apparently large due to dropout or the like, the write clock generator 4 quickly follows this because the time constant of its low-pass filter 44 is small, and the cycle of the write clock _WCK becomes longer in that part. On the other hand, since the read clock generator 6 has a large time constant of its low pass filter 64, the read clock frequency hardly changes. Therefore, the read address value approaches the write address value, and the output of the subtracter 10
SB will be lower.

At this time, when the voltage value of the output SB is smaller than the voltage _E1 and larger than the voltage _E2 , the output of the comparator 11 is low level, the output of the comparator 12 is high level, and the control from the control signal generator 13 is Switch circuits 47 and 67 depending on the signal
is connected to the terminal in the middle of the figure, and the frequency dividers 46B and 66B with a frequency division ratio of 1/n-1 are selected. Therefore, the output oscillation frequency of the variable frequency oscillators 45 and 65 is lower than nf _A (n-
1) Lowered to f _A.

The address difference is quite small, and the output of subtractor 10
When the voltage value of SB becomes lower than the voltage _E2 , the outputs of the comparators 11 and 12 both become low level, and the switch circuit of the write clock generator 4 is activated by the control signal from the control signal generator 13. 47 and the switch circuit 67 of the read clock generator 6 are switched to the bottom terminals in the figure to select the frequency dividers 46C and 66C with a frequency division ratio of 1/n-2. Therefore, the output oscillation frequency of the variable frequency oscillators 45 and 65 is set to still lower (n-2) _fA .

As described above, if the clock frequency is lowered, the speed at which the write address and read address change becomes slower, and the time it takes for the difference between the two addresses to narrow accordingly becomes longer. Therefore, apparently,
This is equivalent to increasing the memory capacity, and overflow of the memory 3 is prevented. In this case, as in the above example, if the degree to which the clock frequency is lowered is varied depending on the address distance, the original accuracy of the time base collector will not be significantly impaired. However, both clock frequencies are
Even if this is lowered, the frequency must be at least twice the highest frequency of the input signal.

The above example is an example in which a RAM (random access memory) or the like is used as the memory, but a shift register can also be used as the memory. FIG. 5 shows an example of such a case, in which a shift register is used as the memory 22. As an example of the structure of the memory 22 in this case, the one shown in FIG. 6 is used. That is, three shift registers 221 and 2 with the same capacity are used as the memory 22.
22, 223 are provided.

A digital signal (e.g.
The PCM audio signal) is sequentially switched by the switch circuit 224 by the capacity of each shift register 221, 22.
2,223. The writing clock is
formed in the write clock generator 23;
With the configuration shown in FIG. 3, the frequency and phase of the gated signal from among the input digital signals through the input terminal 21 are synchronized. Then, this write clock is transmitted through a terminal 229 to three
shift registers 221, 222, 223,
The capacity is sequentially supplied for each period. That is, the write clock is never supplied to multiple shift registers at the same time, but is always supplied to only one shift register. By interlocking the switching between the switch circuit 224 and the switch circuits 226, 227, 228, each shift register 221, 222, 22
3, input digital signals are sequentially written in each capacity.

On the other hand, the readout clock generator 24 has a configuration as shown in FIG. 4, and it generates a readout clock that locks only to the frequency of the gated signal from among the input digital signals and does not include the time axis error of the input digital signal. can get. This readout clock is connected to a switch circuit 226 through a terminal 220.
227 and 228, the signal is supplied to the shift register which is not in the writing state among the three shift registers 221 to 223 and to which writing has been completed before, and these switch circuits 226, 227, 228 A readout output is taken out to an output terminal through a switch circuit 225 which is switched to select the shift register to which the readout clock is supplied in conjunction with the switching of the readout clock.
In this case, as shown in FIG. 6, writing is performed from the first register position of the shift register, and reading is performed from the central register position of each shift register.

In this example, the following steps are taken to prevent each shift register from overflowing. That is, the write clock signal is supplied to the write address counter 25. Also, the read clock signal is input to the read address counter 2.
6. The counter 25 starts counting from a count value corresponding to the initial writing phase of the shift register, and the counter 26 starts counting from a count value corresponding to the initial writing phase corresponding to the initial reading phase of each shift register, and the counter 26 starts counting from a count value that is different by a predetermined value from the count value corresponding to the initial writing phase corresponding to the initial reading phase of each shift register. Start counting from. The count information of these counters 25 and 26 is supplied to a subtracter 27, and a voltage E _S corresponding to the difference is supplied to a comparator 28, where it is compared with a reference voltage E ₀ for comparison.
When E _S becomes smaller than the voltage E ₀ , that is, when the write and read address distance becomes smaller than a predetermined value, the output of the comparator 28 lowers the frequencies of the write clock and read clock in the same manner as in the previous example. , the shift register is prevented from overflowing for the same reason as mentioned above.

In the above example, three shift registers were provided, but
This is because there is a time axis error in the input signal, so it is impossible to write and read the input digital signal by alternately switching the two shift registers.

As described above, according to the present invention, the address distance between write and read is monitored, and when this address distance becomes less than a predetermined value, the memory overflows by lowering the write and read clocks. can be avoided. Furthermore, even if the clock frequency is lowered, if the clock frequency is set to be at least twice the highest frequency of the input signal, the effect as a time base collector can be maintained for the most part.

Note that in the above example, the write clock frequency and the read clock frequency are set equal, but when considering time base compression or time base expansion at the same time as time base correction, the write clock frequency and read clock frequency Both frequencies may be changed without changing the ratio to the frequency.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an example of the present invention, FIG. 2 is a diagram for explaining an example of its essential parts, FIGS. 3 and 4 are block diagrams showing the configuration of an example of its essential parts, and FIG. FIG. 6 is a block diagram of another example of the present invention, FIG. 6 is a block diagram of one example of the main part thereof, and FIG. 7 is a block diagram showing another embodiment of the present invention.

Claims (1)

[Claims] 1 A memory to which an input signal having a time axis error is supplied, a write clock generator that generates a write clock for this memory, a read clock generator that generates a read clock for the memory, and a clock that counts the write clock. A first counter that determines a write address of the memory, and a second counter that counts the read clock and determines a read address, and the write clock generator has a variable frequency oscillator that controls the frequency of the input signal. and its write clock is locked to the phase
The read clock generator also has a variable frequency oscillator whose read clock is adapted to lock only to the frequency of the input signal, the input signal being written to the memory by the write clock and being clocked by the read clock. in which the time axis error is removed by reading from the memory, a difference between the address values of the first and second counters is detected;
The time base collector is configured to lower the output frequencies of the write clock generator and the read clock generator without changing the ratio thereof when the difference becomes less than a predetermined value.