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JPH0424860B2 - - Google Patents
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JPH0424860B2 - - Google Patents

Info

Publication number
JPH0424860B2
JPH0424860B2 JP17555285A JP17555285A JPH0424860B2 JP H0424860 B2 JPH0424860 B2 JP H0424860B2 JP 17555285 A JP17555285 A JP 17555285A JP 17555285 A JP17555285 A JP 17555285A JP H0424860 B2 JPH0424860 B2 JP H0424860B2
Authority
JP
Japan
Prior art keywords
etching
groove
semiconductor board
mesa
linear
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP17555285A
Other languages
Japanese (ja)
Other versions
JPS6235642A (en
Inventor
Kenji Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP60175552A priority Critical patent/JPS6235642A/en
Publication of JPS6235642A publication Critical patent/JPS6235642A/en
Publication of JPH0424860B2 publication Critical patent/JPH0424860B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Weting (AREA)
  • Dicing (AREA)

Description

【発明の詳細な説明】[Detailed description of the invention] 【発明の属する技術分野】[Technical field to which the invention pertains]

本発明は、半導体板の片面あるいは両面よりメ
サ溝を形成したのち、ダイシング等によりメサ溝
部で分割して素子片を形成する半導体素子の製造
方法に関する。
The present invention relates to a method for manufacturing a semiconductor device, in which a mesa groove is formed on one or both sides of a semiconductor board, and then the semiconductor board is divided at the mesa groove portion by dicing or the like to form device pieces.

【従来技術とその問題点】[Prior art and its problems]

半導体板にメサ溝を形成する方法としては、弗
酸、硝酸、酢酸などの混酸をエツチング液として
用い、その中に表面を樹脂膜等によつて保護し、
メサ溝形成部のみを露出させた半導体板を浸漬
し、揺動することによつてエツチングする方法が
多用されている。ところが、この場合エツチング
条件、すなわち半導体板の枚数、メサ溝のパター
ン、エツチング液の配合あるいは温度、エツチン
グ液量、揺動方法等が明らかに異なる時はもちろ
ん、それらの微小な差異あるいはばらつきによつ
てもエツチング速度が変化し、同一時間エツチン
グを行つても形成されるメサ溝深さが異なつてし
まうことが多い。メサ溝深さが異なると各素子片
のメサ溝形状あるいは面積に差が生じ、所望の特
性が得られなくなる。従つて、メサ溝が深くなり
過ぎることを防止するため、エツチングを途中で
中断し、エツチングで生じた溝深さを測定してか
ら再エツチングするというサイクルを何度か繰り
返して目標のメサ溝深さを得るという方法を取ら
ざるを得なかつた。このため、常に均一なメサ溝
深さを得るためには、メサ溝形成に要する時間が
非常に多くなるという欠点があつた。
A method for forming mesa grooves on a semiconductor board is to use a mixed acid such as hydrofluoric acid, nitric acid, and acetic acid as an etching solution, and then protect the surface with a resin film or the like.
A commonly used method is to immerse and oscillate a semiconductor board with only the mesa groove forming portion exposed for etching. However, in this case, not only when the etching conditions, such as the number of semiconductor boards, the pattern of the mesa groove, the composition or temperature of the etching solution, the amount of etching solution, and the method of rocking, are clearly different, but also due to minute differences or variations in them, However, the etching speed changes, and even if etching is performed for the same time, the depth of the mesa groove formed often differs. If the mesa groove depths differ, there will be differences in the mesa groove shape or area of each element piece, making it impossible to obtain desired characteristics. Therefore, to prevent the mesa groove from becoming too deep, the target mesa groove depth is achieved by repeating the cycle of stopping etching midway through, measuring the groove depth created by etching, and re-etching. I had no choice but to find a way to get more. Therefore, in order to always obtain a uniform mesa groove depth, there is a drawback that it takes a very long time to form the mesa groove.

【発明の目的】[Purpose of the invention]

本発明は、上述の欠点を除いてエツチング深さ
の測定、再エツチングの繰り返しをすることな
く、短時間のエツチング操作により常に均一なメ
サ溝深さを形成し、所望の面積およびメサ形状を
有する素子片を得ることができる半導体素子の製
造方法を提供することを目的とする。
Except for the above-mentioned drawbacks, the present invention can always form a uniform mesa groove depth through a short-time etching operation without repeating etching depth measurement or re-etching, and has a desired area and mesa shape. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can obtain a device piece.

【発明の要点】[Key points of the invention]

本発明によれば、半導体板の縁部に、半導体板
の裏面から所定の深さを有し、半導体板の周辺か
ら周辺まで達する線状溝を機械加工により形成
し、表面からエツチングによるメサ溝形成を行な
う際に、同時に前記線状溝に対向する線状表面部
分からもエツチングして、エツチングにより線状
部分が貫通し、半導体板の縁部が分離した時点で
エツチングを停止することによつて上記の目的が
達成される。
According to the present invention, a linear groove having a predetermined depth from the back surface of the semiconductor board and reaching from the periphery of the semiconductor board to the periphery is formed at the edge of the semiconductor board by machining, and a mesa groove is formed by etching from the surface. When forming, the linear surface portion facing the linear groove is etched at the same time, and the etching is stopped when the linear portion penetrates and the edge of the semiconductor board is separated. Thus, the above objectives are achieved.

【発明の実施例】[Embodiments of the invention]

第1図a,bおよび第2図は本発明の一実施例
を示す。第1図aに示すように半導体板1の下面
をレジスト2で覆い、ダイシングにより深さtの
溝3を形成する。次に上面に従来のメサ溝形成と
同様な線状露出パターン4を有するレジスト2を
塗布する。この場合、ダイシング溝3に対向する
上面側にも直線露出パターン5を形成する。この
直線パターン5およびその下側の溝3は第2図に
示すように半導体板の縁部に設けられる。このよ
うにレジストで被覆した半導体板1を混酸内に浸
漬すると、第1図bに示すようにエツチングによ
りメサ溝6が形成されるが、同時に直線パターン
5から形成された溝7とダイシング溝3からのエ
ツチングの進行により形成された溝8とがつなが
り、直線パターン5より外側の半導体板部分11
が分離する。この分離を作業者が認めてエツチン
グを停止する。このあとダイシングまたは折り曲
げによつてメサ溝6の部分で半導体板1を分離し
て素子片を得る。直線パターン5およびダイシン
グ溝3は半導体板の余白部に設けられているか
ら、素子片の取れ数には影響を与えない。エツチ
ング時には、上述のようにダイシング溝3からも
エツチングが進行するので、半導体板の縁部11
の分離するまでに形成されるメサ溝6の深さとダ
イシング溝3の深さtの関係を予め調べ、第3図
のような線図を得ておけば、ダイシング溝深さt
の設定により常に所望の深さのメサ溝6を形成す
ることができる。 第4図a,bは別の実施例を示し、この場合は
両メサ形状の素子が製造される。第4図aに示す
ようにダイシング溝3を予め形成しておき、レジ
スト2の露出パターン51がダイシング溝3の露
出部分にも設けられている。第4図bに示すよう
に、上面からのエツチング溝7とダイシング溝3
から進行したエツチング溝8の接続により半導体
板の縁部11が分離し、それによりエツチングの
終期を決定して均一な深さのメサ溝6を両面から
形成することができる。
Figures 1a, b and 2 show an embodiment of the invention. As shown in FIG. 1a, the lower surface of the semiconductor substrate 1 is covered with a resist 2, and a groove 3 having a depth t is formed by dicing. Next, a resist 2 having a linear exposed pattern 4 similar to the conventional mesa groove formation is applied to the upper surface. In this case, the linear exposed pattern 5 is also formed on the upper surface side facing the dicing groove 3. This linear pattern 5 and the groove 3 below it are provided at the edge of the semiconductor board, as shown in FIG. When the semiconductor board 1 coated with resist is immersed in a mixed acid, mesa grooves 6 are formed by etching as shown in FIG. The grooves 8 formed by the progress of etching from
is separated. The operator recognizes this separation and stops etching. Thereafter, the semiconductor board 1 is separated at the mesa groove 6 by dicing or bending to obtain element pieces. Since the linear pattern 5 and the dicing groove 3 are provided in the margin of the semiconductor board, they do not affect the number of element pieces that can be obtained. During etching, the etching progresses from the dicing groove 3 as described above, so the edge 11 of the semiconductor board is etched.
If the relationship between the depth of the mesa groove 6 formed before separation and the depth t of the dicing groove 3 is investigated in advance and a diagram as shown in FIG. 3 is obtained, the dicing groove depth t can be determined.
By setting , it is possible to always form the mesa groove 6 with a desired depth. FIGS. 4a and 4b show another embodiment in which both mesa-shaped elements are manufactured. As shown in FIG. 4A, the dicing grooves 3 are formed in advance, and the exposed pattern 51 of the resist 2 is also provided in the exposed portions of the dicing grooves 3. As shown in Figure 4b, etching grooves 7 and dicing grooves 3 are formed from the top surface.
The edges 11 of the semiconductor board are separated by the connection of the etched grooves 8 which have proceeded from the beginning, thereby determining the final stage of etching and making it possible to form mesa grooves 6 of uniform depth from both sides.

【発明の効果】【Effect of the invention】

本発明によれば、半導体板へのエツチングによ
るメサ溝形成時に予め裏面より半導体板の周辺か
ら周辺に達する線状溝を形成しておき、表面側か
らのエツチング溝がその線状溝から進行したエツ
チング溝とつながることによつてエツチング終期
を決定することにより、エツチングの中断、エツ
チング深さの測定の繰り返しの必要がなくなり、
メサ溝形成時間を大幅に短縮できる。そしてエツ
チング条件が異なつても常に所定の深さのメサ溝
が形成でき、特性均一の半導体素子の製造に対し
て極めて有効である。
According to the present invention, when forming a mesa groove by etching on a semiconductor board, a linear groove reaching from the periphery of the semiconductor board to the periphery is formed in advance from the back side, and the etching groove from the front side advances from the linear groove. By determining the final stage of etching by connecting with the etching groove, there is no need to interrupt etching or repeatedly measure the etching depth.
Mesa groove formation time can be significantly shortened. Even if the etching conditions are different, a mesa groove of a predetermined depth can always be formed, which is extremely effective for manufacturing semiconductor devices with uniform characteristics.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例におけるメサ溝形成
の工程を示す断面図、第2図は第1図aに対応す
る平面図、第3図は形成されるメサ溝深さとダイ
シング溝深さの関係線図、第4図は異なる実施例
におけるメサ溝形成の工程を示す断面図である。 1:半導体板、2:レジスト、3:ダイシング
溝、4,5:露出パターン、11:半導体板分離
部。
FIG. 1 is a sectional view showing the mesa groove forming process in an embodiment of the present invention, FIG. 2 is a plan view corresponding to FIG. 1a, and FIG. 3 is a mesa groove depth to be formed and a dicing groove depth. FIG. 4 is a cross-sectional view showing the process of forming a mesa groove in a different embodiment. 1: Semiconductor board, 2: Resist, 3: Dicing groove, 4, 5: Exposed pattern, 11: Semiconductor board separation part.

Claims (1)

【特許請求の範囲】[Claims] 1 半導体板の表面よりエツチングによりメサ溝
を形成したのちメサ溝部で半導体板を分割して素
子片を得る方法において、半導体板の縁部に、半
導体板の裏面から所定の深さを有し、半導体板の
周辺から周辺まで達する線状溝を機械加工により
形成し、メサ溝形成のためのエツチング時に同時
に前記線状溝に対向する線状表面部分からもエツ
チングして、エツチングにより線状部分が貫通
し、半導体板の縁部が分離した時点でエツチング
を停止することを特徴とする半導体素子の製造方
法。
1. In a method of forming a mesa groove from the surface of a semiconductor board by etching and then dividing the semiconductor board at the mesa groove to obtain element pieces, the edge of the semiconductor board has a predetermined depth from the back surface of the semiconductor board, A linear groove reaching from the periphery to the periphery of the semiconductor board is formed by machining, and at the same time when etching is performed to form a mesa groove, the linear surface portion facing the linear groove is also etched, so that the linear portion is removed by etching. A method for manufacturing a semiconductor device, characterized in that etching is stopped when the edge of the semiconductor board is separated.
JP60175552A 1985-08-09 1985-08-09 Manufacture of semiconductor element Granted JPS6235642A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60175552A JPS6235642A (en) 1985-08-09 1985-08-09 Manufacture of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60175552A JPS6235642A (en) 1985-08-09 1985-08-09 Manufacture of semiconductor element

Publications (2)

Publication Number Publication Date
JPS6235642A JPS6235642A (en) 1987-02-16
JPH0424860B2 true JPH0424860B2 (en) 1992-04-28

Family

ID=15998074

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60175552A Granted JPS6235642A (en) 1985-08-09 1985-08-09 Manufacture of semiconductor element

Country Status (1)

Country Link
JP (1) JPS6235642A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5593815A (en) * 1989-07-31 1997-01-14 Goldstar Co., Ltd. Cleaving process in manufacturing a semiconductor laser

Also Published As

Publication number Publication date
JPS6235642A (en) 1987-02-16

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