JPH0424866B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device such as a power transistor or a semiconductor integrated circuit.

Transistors in semiconductor integrated circuits are called PN
A structure in which the emitter, base, and collector electrodes are formed in island-like regions separated by bonding and taken out from the surface of the semiconductor substrate is well known. When a transistor with this structure is used for power purposes and can draw a large output current, a low-resistance collector region is buried at the bottom of the island-like region, and highly concentrated impurities are diffused from the surface of the semiconductor substrate to form the buried collector region. A commonly used method is to form a collector draw-out area that reaches . However, as long as the collector electrode is formed on the surface of the semiconductor substrate, the current path for the collector current becomes quite long, and there is a limit to reducing the resistance value of this path. Therefore, the collector saturation voltage V _CE (sat) of the transistor becomes large, resulting in a drawback that power loss within the semiconductor substrate is large. Furthermore, since a considerable area is required for the collector electrode, there is also the disadvantage that the area of the semiconductor substrate (chip size) becomes large.

As a structure that can overcome these drawbacks, a structure in which a collector electrode is taken out from the back surface of a semiconductor substrate, like a discrete power transistor, is known. An integrated circuit having this structure is formed as shown in FIGS. 1 to 4.

That is, first, as shown in FIG. 1, a high resistivity N type semiconductor region 2 is formed on an N ⁺ type semiconductor substrate 1 by epitaxial growth. Next, a P-type conductivity type region 3 is formed by diffusion in a portion of the region 2 where a plurality of circuit elements (here, small signal transistors and resistors) are to be formed. Furthermore, an N ⁺ type region 4 which will become a buried collector region of a small signal transistor and an N ⁺ type region 5 which will serve as a region for preventing parasitic leakage current of the resistor are formed in the region 3 by diffusion.

Next, as shown in FIG.
4 and 5), a high resistivity N-type semiconductor region 6 is formed by epitaxial growth.

Next, as shown in FIG. 3, a P-type region 7, which will become the base region of the power transistor, is formed in the region 6 where the power transistor is to be formed (the tip of the region 7 reaches the region 2). ing). Also, an N-type region 6a, which is a part of the region 6, in which a small signal transistor is to be formed, and an N-type region 6b, in which a resistor is to be formed.
P-type region 8 is formed by diffusing impurities from surface 6 of region 6 so that P-type region 8 is obtained separately from region 2.

Next, as shown in FIG. 4, there is an N + type region 10 which becomes the collector lead-out region of the power transistor, and an N ⁺ type region 10 which becomes the collector lead-out region of the small confidence transistor ^.
A mold region 11 is formed in region 7 and region 6a, respectively, by diffusion. Next, a P-type region 12 that will become a base region of a small signal transistor and a P-type region 13 that will become a resistance region are formed in the regions 6a and 6b, respectively, by diffusion. Furthermore, an N ⁺ type region 14, which will become the emitter region of the small signal transistor, is formed by diffusion. Finally, the emitter, base, and collector electrodes 15, 16, and 17 of the power transistor, and the emitter, base, and collector electrodes 18, 19, and 2 of the small signal transistor.
The surface of the semiconductor substrate on which the resistor electrodes 21 and 22 are formed is covered with a SiO ₂ film 23 for protection.
Note that in FIGS. 1 to 3, the SiO ₂ film used as a mask for selective diffusion is omitted. Further, in FIG. 4, wiring electrodes connecting each element inside the semiconductor integrated circuit are omitted. In such a semiconductor integrated circuit, regions 1 and 2 serve as substrates on which a plurality of circuit elements are constructed, and also serve as collector regions of power transistors. Therefore, the collector saturation voltage of the power transistor V _CE
(sat) can be made as small as an individual element, and the chip size does not increase due to the area required for the collector electrode of the power transistor.

However, there are still problems to be solved.
That is, regions 2 and 6 are usually so-called double epitaxial regions in which two layers of regions grown by the emipaxial growth method are stacked. In region 6, which is the epitaxial region of the second layer, more crystal defects (dislocations, stacking faults, etc.) occur than in region 2, which is the first layer. Conventionally, power transistors and active regions of a plurality of circuit elements were formed in this region 6 with poor crystallinity. The poor crystallinity of the region 6 has little effect on small-signal circuit elements that do not require a very high breakdown voltage, but it does have a considerable effect on power transistors that have a relatively high breakdown voltage and a large area. In power transistors in particular, the adverse effect appears as a deterioration of the withstand voltage characteristics between the collector and base.
This is a cause of a significant decrease in manufacturing yield. Note that there is also a method of forming region 1 by performing high concentration diffusion for a long time in a high resistivity N type substrate and forming the remaining region 2, and according to this method, there is no need to perform double epitaxial growth. However, even in this case, especially when a large number of various processing steps such as diffusion are required, such as in the case of semiconductor integrated circuits,
A considerable number of crystal defects (dislocations, stacking faults, scratches, etc.) occur near the surface of region 6, which is the top layer. The poor crystallinity near the surface of the region 6 causes deterioration of the breakdown voltage characteristics of the power transistor and a decrease in manufacturing yield, as described above.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device that can increase the manufacturing yield of transistors or integrated circuits and improve the characteristics of transistors.

The first invention of the present application to achieve the above object will be described with reference to the reference numerals in FIGS. 5 to 11 showing embodiments for ease of understanding.
preparing a substrate having a first conductivity type low resistance collector region 31 and a first conductivity type high resistance collector region 32 adjacent to the low resistance collector region 31; a second conductivity type opposite to the first conductivity type; A part of the base region 33 of the mold is the high-resistance collector region 3.
2, the high resistance collector region 32
forming in the high resistance collector region 32;
forming an epitaxial growth layer 37 of a first conductivity type and having a high resistivity so as to cover the main surface of the substrate where the base region 33 and the base region 33 are exposed; forming a base lead-out region 38 of a second conductivity type so as to directly or indirectly surround an emitter region 40 (described later); and after or before forming the base lead-out region 38, the epitaxial growth layer 37 By diffusing or implanting conductivity type determining impurities from the surface side, the epitaxial growth layer 37 with high resistivity does not remain between the base region 33 and the base deriving region 3.
8, an emitter region 40 of a first conductivity type and low resistivity is formed so as to be surrounded by the base region 33 and the base lead-out region 38 with no remaining epitaxial growth layer 37 having a high resistivity. forming a collector electrode 45 connected to the low resistance collector region 31, a base electrode 46 connected to the base lead-out region 38, and the emitter region 40.
The present invention relates to a method of manufacturing a semiconductor device including forming an emitter electrode 47 connected to the emitter electrode 47 . In addition, to explain the correspondence between the above invention and the embodiments described later, the low resistance collector region is the first semiconductor region 31, the high resistance collector region is the second semiconductor region 32, and the base region is the third semiconductor region 3.
3. The base conductivity type region is the fifth semiconductor region 38,
The emitter region corresponds to the seventh semiconductor region 40.

The second invention of the present application relates to a method for manufacturing an integrated circuit including the transistor according to the first invention, and includes forming a fourth semiconductor region 34, as will be clear from the examples described below. forming a sixth semiconductor region 39; and forming a semiconductor circuit element in a region surrounded by the sixth semiconductor region 39.

According to the present invention, since the active region of the transistor is formed away from the surface of the semiconductor substrate, the adverse effects of crystal defects that are likely to occur near the surface of the semiconductor substrate are reduced, and the deterioration of the breakdown voltage characteristics of the transistor and the manufacturing process are reduced. Decreased yield and other disadvantages are reduced. In addition, since the impurity concentration distribution in the base region of the transistor is different from that of a normal diffused base transistor, when trying to obtain a constant current amplification factor, it is possible to make the base width wider than that of a normal diffused base transistor. . This means that breakdown resistance can be improved by alleviating current concentration.

Hereinafter, a method and structure for manufacturing an integrated circuit according to an embodiment of the present invention will be described with reference to FIGS. 5 to 11.

FIGS. 5 to 11 show cross sections at various steps in forming an integrated circuit including power transistors using a semiconductor silicon substrate. First, as shown in FIG. 5, on a first semiconductor region 31 made of an N ⁺ type (first conductivity type) substrate with a thickness of approximately 250 μm, a second N type semiconductor region lightly doped with phosphorus is grown by epitaxial growth. A semiconductor region 32 is formed.
The first and second semiconductor regions 31 and 32 not only function as a substrate for an integrated circuit, but also function as a collector region of a power transistor. Note that the resistivity of the region 32 is as high as 10 to 15 Ω·cm, and the thickness is about 40 μm. Next, in the area 32 where the power transistor is to be created,
A P-type (second conductivity type) third semiconductor region 33 is formed to serve as a base region of a power transistor.
In addition, a plurality of circuit elements in the region 32 (normally a large number of circuit elements such as transistors, diodes, and resistors are formed, but here, to simplify the explanation, a simple example of one small signal transistor and one resistor is used. A P-type fourth semiconductor region 34 is formed in a portion where a P-type semiconductor region 34 is to be formed. Regions 33 and 34 are formed simultaneously by diffusing boron, which is a P-type impurity, from the surface of region 32, and the surface impurity concentration is approximately 5×.
The concentration is 10 ¹⁶ atoms/cm ³ and the depth is approximately 15 μm. In addition,
The regions 31 and 32 immediately below the region 33 and their surrounding regions become the collector region of the power transistor.

Next, as shown in FIG. 6, an N ⁺ type semiconductor region 35 which becomes the buried collector region of the small signal transistor
An N ⁺ type semiconductor region 36 is formed in the region 34 to serve as a region for preventing parasitic leakage current of the resistor. Area 3
5 and 36 are simultaneously formed by diffusing antimony or arsenic, which are N-type impurities, from the surface of the region 34, and the surface impurity concentration is approximately 2×10 ¹⁹ atoms/cm ³ .
The depth is approximately 5 μm.

Next, as shown in FIG. 7, an N-type epitaxial growth layer 37 lightly doped with phosphorous is formed on the regions 32 to 36 by an epitaxial growth method.
The resistivity of this epitaxial growth layer 37 is about 10~
It has a high resistivity of 15Ωcm and a thickness of approximately 20μm.

Next, as shown in FIG. 8, a P-type fifth semiconductor region 38 that is connected to the third semiconductor region 33 that becomes the base region of the power transistor and becomes the base lead region is diffused into the region 37. Twist and form. This region 38 is an epitaxial growth layer 37
An N-type island-shaped semiconductor region 37a, which is a part of the semiconductor region 37a, is annularly surrounded, and the region 37a is isolated from the collector region of the power transistor (PN junction isolation, the same applies hereinafter). In the island-shaped semiconductor region 37a surrounded by the region 38, a seventh semiconductor region 40 shown in FIG. 9 will be formed in a later step. Further, a P-type semiconductor region 39 that is connected to the fourth semiconductor region 34 and becomes an isolation region is formed in the epitaxial growth layer 37. Region 39 is epitaxial growth layer 37
N-type island-shaped semiconductor regions 37b and 37c in which a plurality of small-signal semiconductor circuit elements are to be formed are surrounded in an annular manner, and this portion is insulated and isolated from the collector region of the power transistor. Further, the region 39 also insulates and isolates the plurality of island-shaped semiconductor regions 37b and 37c from each other. The regions 38 and 39 are simultaneously formed by diffusing boron, which is a P-type impurity, from the surface of the epitaxial growth layer 37, and the surface impurity concentration is approximately 2×10 ¹⁹ atoms/cm ³ and the depth is approximately 15 μm ( Since the regions 33 and 34 expand upward, the thickness may be shallower than the thickness of the epitaxial growth layer 37).

Next, as shown in FIG. 9, in the region 37a there is a ^seventh
A semiconductor region 40 is formed. This region 40 is formed so that its bottom surface coincides with the boundary surface between the region 37a and the region 33. Also area 40 and area 3
A slight region 37a remains between the regions 8 and 8.
This example has a multi-emitter structure, and a plurality of regions 37a and 40 (in the drawing, two regions are shown for simplicity) are formed. Also, area 3 is added to area 37b.
5, an N ⁺ type semiconductor region 41 is formed to serve as a collector lead-out region of the small signal transistor.
The regions 40 and 41 are simultaneously formed by diffusing phosphorus, which is an N-type impurity, from the surface of the epitaxial layer 37, and the surface impurity concentration is approximately 2×10 ²⁰ atoms/cm ³ .
The depth is approximately 12 μm.

Next, as shown in FIG. 10, a P-type semiconductor region 42, which will become a base region of a small signal transistor, is formed in region 37b. Further, a P-type region 43 which becomes a resistance region is formed in the region 37c. Areas 42, 43
is simultaneously formed by diffusing boron, which is a P-type impurity, from the surface of the epitaxial growth layer 37, and the surface impurity concentration is approximately 5×10 ¹⁸ atoms/cm ³ and the depth is approximately
It is 3 μm.

Next, as shown in FIG. 11, phosphorus, which is an N type impurity, is diffused from the surface of the region 42 to form an N ⁺ type region 44 which will become the emitter region of the small signal transistor in the region 42. The surface impurity concentration of the region 44 is about 2×10 ²⁰ atoms/cm ³ and the depth is about 1.5 μm.
Next, the collector electrode 45 of the power transistor is placed in the first semiconductor region 31, the base electrode 46 of the power transistor is placed in the fifth semiconductor region 38, the emitter electrode 47 of the power transistor is placed in the sixth semiconductor region 40, and the small signal The emitter, base, and collector electrodes 48, 49, and 50 of the transistor and the resistor electrodes 51 and 52 are respectively formed by vapor deposition of aluminum. The surface of the semiconductor substrate is a SiO ₂ film 5
3 and protected. In addition, Figures 5 to 1
In Figure 0, the SiO ₂ film formed for use as a selective diffusion mask is omitted. Further, in FIG. 11, wiring electrodes connecting each element inside the semiconductor integrated circuit are omitted.

Here, the formation of the seventh semiconductor region 40 will be explained. In this embodiment, the bottom surface of region 40 coincides with the boundary surface between region 37a and region 33. However, in cases where it is desired to obtain an even larger current amplification factor, deeper diffusion is performed so that the bottom surface of region 40 shown in FIG. 14 approaches the bottom surface of region 33 beyond the above boundary surface. It's good to wear. Conversely, it is also conceivable to perform shallow diffusion so that the bottom surface of the region 40 remains within the region 37a, as shown in FIG. In this case, the emitter area is
It has an N ⁺ −N structure, and the LEC transistor (Low
This is a structure known as an Emitter Concentration Transistor (see, for example, Japanese Patent Publication No. 54-37797).
However, with the LEC transistor structure, the boundary between the N ⁺ type region 40 and the N type region 37a approaches the surface of the epitaxial layer 37 with poor crystallinity, making it impossible to achieve the object of the present invention. Also,
In the case of the power transistor according to the present invention shown in FIG. 11, it is possible to obtain a current amplification factor h _FE of approximately 50, while in the case of the power transistor having the structure shown in FIG. 15, the current amplification factor h _FE is It will be about 10.

On the other hand, in the above embodiment, the region 37a remains between the region 40 and the region 38. In this way,
Base drawer area and emitter area are P-N-N ⁺
By forming the structure and selecting the remaining width of region 37a, which is an N-type region, the emitter-base voltage can be reduced.
V _EBO can be adjusted. That is, the area 37a
By choosing a large residual width, it is possible to increase V _EBO to 100V or more. Of course, if V _EBO of several V is sufficient, the area 37a as shown in FIG.
The remaining width of the region 40 and the region 38 may be made to be in direct contact with each other by setting the remaining width to zero. This increases the area of the emitter region and increases the current capacity. Also, all areas 37a are converted to areas 40,
Furthermore, it is also possible to make the region 40 extend into the regions 33 and 38.

By configuring the semiconductor integrated circuit as described above, the following advantages can be obtained.

(a) The active region of the power transistor is mainly formed in the second semiconductor region 32, which is the first layer of the double epitaxial region, and is formed in the epitaxial region, which is the second layer of the double epitaxial region, which will eventually become the surface region. It is formed away from the surface of the layer growth layer 37. Therefore, the probability that crystal defects frequently occurring in the epitaxial growth layer 37, particularly in the surface region thereof, will lead to disadvantages such as deterioration of the breakdown voltage of the power transistor and a resulting decrease in manufacturing yield is greatly reduced. As a result, it has become possible to manufacture semiconductor integrated circuits including high-voltage transistors for power use with a high manufacturing yield.

(b) The base width of the base region consisting of the region 33 in the power transistor becomes wider than that of a normal base diffusion type transistor when trying to obtain a constant current amplification factor. When the base width is wide, concentration of current flowing through the base region is less likely to occur, so that the breakdown resistance of the power transistor is improved. This will be explained with reference to FIGS. 12 and 13. In FIGS. 12 and 13, lines E, B, and C show distributions of impurity concentrations corresponding to the absolute values of the differences between donors and acceptors in the emitter region, base region, and collector region.
In FIG. 12 qualitatively showing the impurity concentration distribution of the power transistor according to the present invention, L ₀ is the surface of region 41, L ₁ is the boundary between region 40 and region 33, and L ₂ is the boundary between region 32 and region 37. boundary with, L ₃
is the boundary between area 33 and area 32, and L ₀ ~
_L1 is the emitter area, _L1 to _L3 are the base area, _L3
The area to the right is the collector area. Furthermore, in FIG. 13 showing the impurity concentration distribution of a conventional base diffused power transistor, L ₀ is the surface of the emitter region, L ₁ is the boundary between the emitter region and the base region, and L ₂ is the base region and collector region. Indicates the boundary between In the power transistor according to the present invention shown in FIG. 12, the impurity concentration distribution in the base region is initially as shown by the broken line S, but as a result of the subsequent heat treatment, the impurity diffusion progresses considerably and becomes as shown by the solid line B. That is, due to the redistribution of impurities, the impurity concentration in the base region becomes significantly lower on the emitter region side. On the other hand, in the conventional power transistor shown in FIG. 13, the base region is formed by impurity diffusion from the surface of the semiconductor substrate, so that the distribution changes only slightly due to subsequent heat treatment. Therefore, the impurity concentration in the base region is relatively high.

As shown in FIG. 12, when the impurity concentration in the base region decreases due to redistribution, the injection efficiency and the transport efficiency per unit length increase. Therefore, even if the base widths L ₁ to L ₃ are designed to be wide, the current amplification factor does not decrease and a sufficient current amplification factor can be obtained. Of course,
If the base width is made as narrow as that of a normal base diffusion type transistor, a power transistor with an extremely large current amplification factor can be obtained.

(c) Emitter-base voltage of power transistor
V _EBO can be controlled over a wide range by selecting the remaining width of the N-type region 37a. If necessary,
A power transistor with a large V _EBO can be easily created.

(d) In the manufacturing method explained in FIGS. 5 to 11, regions 33 and 34, regions 38 and 39, and regions 40 and 4
1 at the same time, it becomes possible to rationally manufacture semiconductor integrated circuits.

Although the embodiments have been described above, the present invention is not limited to these embodiments, and various changes can be made without departing from the spirit of the invention. For example, power transistors may have a comb-shaped single-emitter structure, or two
It is also possible to use a single transistor. Alternatively, the region formed by diffusing impurities may be formed by doping impurities by ion implantation or a combination of ion implantation and diffusion. Further, the resistivity, impurity concentration, dimensions, etc. of each region may be varied depending on desired characteristics. In addition, a second semiconductor region 3 which becomes a collector high resistance region of the power transistor
2 is usually formed by epitaxial growth, and in this case the effect of the present invention is significant. However, the first semiconductor region 3 which becomes the collector low resistance region of the power transistor is formed on a high resistivity semiconductor substrate.
Even if the semiconductor region 1 is formed by diffusion and the remaining region is used as the second semiconductor region 32, the effects of the present invention can be sufficiently exhibited.
Furthermore, the order in which the regions are formed may be varied as necessary. It is also applicable to manufacturing only transistors.

[Brief explanation of drawings]

FIG. 1, FIG. 2, FIG. 3, and FIG. 4 are cross-sectional views showing the state of each manufacturing process of a conventional integrated circuit. Figure 5, Figure 6, Figure 7, Figure 8, Figure 9,
10 and 11 are cross-sectional views showing states of each manufacturing process of an integrated circuit according to an embodiment of the present invention. FIG. 12 is an impurity distribution diagram of the power transistor portion of the integrated circuit of FIG. 11. FIG. 13 is an impurity distribution diagram of a conventional base diffusion type power transistor. Figures 14, 15, and 16
The figure is a sectional view showing a modification. In the reference symbols used in the drawings, 31 is the first semiconductor region, 32 is the second semiconductor region, and 3 is the first semiconductor region.
3 is a third semiconductor region, 34 is a fourth semiconductor region, 37 is an epitaxial growth layer, 38 is a fifth semiconductor region, 39 is a sixth semiconductor region, and 40 is a seventh semiconductor region.

Claims (1)

[Scope of Claims] 1. preparing a substrate having a low resistance collector region 31 of a first conductivity type and a high resistance collector region 32 of a first conductivity type adjacent to the low resistance collector region 31; A portion of the base region 33 of the second conductivity type opposite to the high resistance collector region 32
forming an epitaxial layer of first conductivity type and high resistivity so as to cover the main surface of the substrate where the high resistance collector region 32 and the base region 33 are exposed; forming a growth layer 37; a second conductivity type base lead-out region 38 that penetrates the epitaxial growth layer 37 to reach the base region 33 and directly or indirectly surrounds an emitter region 40 (described later); After or before the formation of the base derivation region 38, a conductivity type determining impurity is diffused or implanted from the surface side of the epitaxial growth layer 37 to form a region between the base region 33 and the base region 33. The epitaxial growth layer 37 having a high resistivity does not remain between the base region 33 and the base, and the epitaxial growth layer 37 having a high resistivity remains or does not remain between the base lead-out region 38 and the base region 33 and the base. forming an emitter region 40 of a first conductivity type and low resistivity so as to be surrounded by the lead-out region 38; a collector electrode 45 connected to the low-resistance collector region 31 and a collector electrode 45 connected to the base lead-out region 38; A method of manufacturing a semiconductor device, comprising: forming a base electrode 46 and an emitter electrode 47 connected to the emitter region 40. 2. Manufacturing the semiconductor device according to claim 1, wherein preparing the substrate includes preparing a substrate in which an epitaxial growth layer is provided as the high-resistance collector region 32 in the low-resistance collector region 31. Method. 3. Forming the emitter region 40 is to form a plurality of emitter regions of the first conductivity type and low resistivity separated by the base lead-out region 38. A method for manufacturing a semiconductor device according to section 1. 4 First semiconductor region 3 of first conductivity type and low resistivity
1 and a second semiconductor region 32 of a first conductivity type and high resistivity adjacent to the first semiconductor region 31; The second semiconductor region 32 is arranged such that the semiconductor region 33 of No. 3 is partially surrounded by the second semiconductor region 32.
and at the same time form a fourth semiconductor region 34 of the second conductivity type in a state where a portion thereof is surrounded by the second semiconductor region 32 and separated from the third semiconductor region 33. at least the second semiconductor region 32, the third semiconductor region 33, and the fourth semiconductor region 34.
forming an epitaxial growth layer 37 of a first conductivity type and high resistivity so as to cover the exposed main surface of the substrate; penetrating the epitaxial growth layer 37 to reach the third semiconductor region 33; In addition, a fifth semiconductor region 38 of the second conductivity type is formed so as to directly or indirectly surround a seventh semiconductor region 40 to be described later,
At the same time, a sixth semiconductor region 39 of the second conductivity type is formed to penetrate through the epitaxial growth layer 37 to reach the fourth semiconductor region 34 and to annularly surround a part of the epitaxial growth layer 37. The epitaxial growth layer 3 is formed after or before the formation of the fifth and sixth semiconductor regions 38 and 39.
By diffusing or implanting conductivity type determining impurities from the surface side of 7, the epitaxial growth layer 37 with high resistivity is formed between the third semiconductor region 33 and the third semiconductor region 33.
is in a non-remaining state, and the epitaxial growth layer 37 having a high resistivity remains or does not remain between the fifth semiconductor region 38 and the third and fifth semiconductor regions 33 and 38. A seventh semiconductor region 4 of the first conductivity type and low resistivity is surrounded by the seventh semiconductor region 4.
forming a semiconductor circuit element in a region surrounded by the sixth semiconductor region 39, simultaneously or separately from the formation of the seventh semiconductor region 40; A collector electrode 45 of the power transistor connected to the base electrode 46 of the power transistor connected to the fifth semiconductor region 38 and the seventh semiconductor region 4
forming an emitter electrode 47 of the power transistor connected to 0. 5. The semiconductor device according to claim 4, wherein preparing the substrate includes preparing a substrate in which an epitaxial growth layer is provided as the second semiconductor region 32 in the first semiconductor region 31. manufacturing method. 6 Forming the seventh semiconductor region 40 means forming the first semiconductor region 40 separated by the fifth semiconductor region 38.
6. The method of manufacturing a semiconductor device according to claim 4, wherein a plurality of regions having a conductivity type and a low resistivity are formed.