JPH0425740B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an error counting device in a transmission path, and more particularly to an error counting device that monitors the error state of the transmission path by counting error pulses when monitoring errors in the transmission path.

[Prior art]

As an error counting method in a transmission path, there is a method in which k or more error pulses are counted during a certain period of time T, and an error alarm signal is generated when this state continues N times. Here, the values of T, k, and N are derived from the assumed probability of error occurrence on the transmission path. Note that in the error counting method described above, calculations are required to derive the values of T, k, and N, but a description of the calculation method will be omitted.

FIG. 1 is a block diagram showing a conventional error counting method. A trigger pulse generation circuit 1 generates a trigger pulse with a constant period T and supplies a signal with the constant period T. The error pulse counting circuit 2 counts the error pulses 21 supplied from the trigger pulse generating circuit 1 for a certain period of time T, and the count contents are erased by the trigger pulse. When k error pulses are counted during a certain period of time T, the output signal 24 of the error pulse counting circuit changes and maintains its state. The N-stage shift register circuit 3 uses the output signal 23 of the trigger pulse generation circuit 1 to shift and store the output state of the error pulse counting circuit 2 before erasing. The AND circuit 4 constitutes an AND of the output signals of each stage of the N-stage shift register circuit 3, and the error pulse counting circuit 2 continuously counts k error pulses N times during a fixed time T. and sends out an error alarm signal 22.

In this error counting method, since the N-stage shift register circuit 3 is provided, it is possible to prevent the sending of an error alarm signal due to a sudden error. Error due to pulse Pulse counting circuit 2
In order to shift and store the output state of the error alarm signal, it takes N times T to send out the error alarm signal. When the error rate of the transmission path to be monitored is reduced, the fixed time T required to count k error pulses becomes longer, and as a result, the error rate changes to a state where the error rate is sufficiently large compared to the minimum error rate that can be monitored. Even in this case, there was a drawback that it took N times T to send out the error alarm signal.

[Purpose of the invention]

The present invention eliminates such drawbacks, and has a function of preventing the sending of error alarm signals due to sudden errors in the transmission path, and also prevents the error rate from being sent in a state where the error rate is sufficiently large compared to the minimum error rate that can be monitored. The object of the present invention is to provide a system that can send out an error alarm signal in a shorter time than before when the error occurs.

[Structure of the invention]

According to the present invention, a first trigger pulse signal and a second trigger pulse signal having a shorter cycle than the first trigger pulse signal are generated at a constant period, and the control signal and the contents before input are generated by an external control signal. a trigger pulse generation circuit that erases and returns to the initial state and again starts generating the first trigger pulse signal and the second trigger pulse signal; and the second trigger whose output state returns to the initial state by the control signal. A sending circuit that changes the output state by a pulse signal and then holds this output state for a certain period of time until the control signal is input again, and a sending circuit that counts a certain number of error pulses and changes the output state when a certain number of error pulses are counted. An error pulse counting circuit that maintains this output state and returns to the initial state and starts counting again when the control signal is input, and an error pulse counting circuit that shifts the output state of the error pulse counting circuit by the control signal and starts counting again. a shift register circuit that stores past output states; a first AND circuit that sends an AND of the output signals of each stage of the shift register circuit to the outside as an error alarm signal; and an output signal of the error pulse counting circuit. a second AND circuit that outputs the AND of the output signal of the output circuit for a certain period of time, and a logical sum of the output signal of the second AND circuit and the first trigger pulse signal as the control signal As a result, there is obtained an error counting device in a transmission line, characterized in that it includes the trigger pulse generation circuit, the fixed time sending circuit, the error pulse counting circuit, and an OR circuit that sends out to the shift register circuit.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings. FIG. 2 is a block diagram showing one embodiment of the present invention.

The trigger pulse generation circuit 5 includes a fixed frequency oscillation circuit 51 and a frequency dividing circuit 52, and corresponds to the time T corresponding to the minimum error rate that can be monitored and the maximum error rate derived from the assumed error occurrence probability of the transmission path. A signal regarding the time t is sent out. That is, the control signal 10
Output signal 110 is output after t time from the initial state after 5 is input, and output signal 104 is output after T time. However, if the control signal 105 is input before time T, the frequency division state before the input of this control signal 105 is erased, and frequency division is restarted from the initial state.

The fixed time transmission circuit 6 includes a D flip-flop circuit 61 whose data input is at the "H" level.
The output is erased to "L" level by the control signal 105, and the output signal 110 with a shorter period than the output signal 104 of the frequency dividing circuit 52 is input, that is, the "H" level of the data input signal is changed to the next one at the rising edge of this input pulse. The output continues until the control signal 105 is input.

The error pulse counting circuit 7 has its counted contents erased by the control signal 105, and counts the error pulses 111 until the control signal 105 is inputted again. When the error pulse counting circuit 7 has counted k pieces, the output signal 101 changes to "H" level. Retain state.

The N-stage shift register circuit 8 uses the external control signal 105 as a clock signal to shift and store the output signal 101 of the error pulse counting circuit before the contents of the error pulse counting circuit 7 are erased by the control signal 105.

The AND circuit 9 constitutes an AND of the output signals of each stage of the N-stage shift register circuit, and generates an error alarm signal 109 when the error pulse counting circuit 7 counts k error pulses N times in succession. Send.

The OR circuit 10 receives the output signal 102 of the sending circuit 6 for a certain period of time and the output signal 10 of the error pulse counting circuit 7.
Constructs a logical product of 1.

The AND circuit 11 receives the output signal 1 of the AND circuit 10.
03 and the output signal 104 of the trigger pulse generation circuit 5
The output signal, that is, the control signal 1
05 is an erase signal for erasing counting contents, etc.
Trigger pulse generation circuit 5 and fixed time transmission circuit 6
Then, it is sent to the error pulse counting circuit 7, and then sent to the N-stage shift register circuit 8 as a clock signal.

Next, the operation of this embodiment will be explained. FIG. 3 shows a timing chart when the error occurrence on the transmission path changes to a state where the error rate is sufficiently larger than the minimum error rate that can be monitored. Note that the N-stage shift register circuit has three stages in this figure and in FIGS. 4 and 5.

The error pulse counting circuit 7 receives the output signal 10 for a certain period of time t, that is, the output signal 10 is sent out from the sending circuit 6 for a certain period of time.
If k error pulses are counted while 2 is at the "L" level, the output signal 10 is as shown in Figure 3a.
1 changes to "H" level and maintains the state. The output signal 102 of the fixed time sending circuit 6 is transmitted to the frequency dividing circuit 52.
When the output signal 110 sent from the AND circuit changes to "H" level as shown in FIG. 3b, the output signal 103 of the AND circuit 10 becomes "H" level as shown in FIG. The control signal 105 of the summation circuit 11 changes from the "L" level to the "H" level as shown in FIG. 3e, and the control signal 105 changes the output signal 101 of the error pulse counting circuit 7 as shown in FIG. 3f. It shifts to the N-stage shift register circuit 8, erases the contents of the frequency divider circuit 52, fixed time sending circuit 6, and error pulse counting circuit 7, returns to the initial state, and starts counting again. The output 109 of the product circuit 9 changes as shown in FIG. 3i.

Next, FIG. 4 shows a timing chart when k error pulses are not input during the fixed time period t sent out from the fixed time sending circuit 6. The output signal 102 of the sending circuit 6 for a certain period of time is initially erased by the control signal 105 and becomes "L" as shown in FIG.
Although it is in the "H" level state, it changes to the "H" level by the output signal 110 from the frequency divider circuit 52, which is generated t time after erasing. However, the AND circuit 1
Since it is inhibited by 0, it continues to hold the "H" level. When the pulse counting circuit 7 counts k error pulses after a certain period of time t has elapsed, the output signal 101 becomes "H" as shown in FIG.
Change in level. Therefore, the output signal 103 of the AND circuit 10 goes to the "H" level as shown in FIG. Changes to As explained above, f, g, h in the same figure
As shown in the figure, the output 101 is shifted to the N-stage shift register circuit 8 and stored. When the control signal 105 becomes "H" level, the contents of the sending circuit 6 and the error pulse counting circuit 7 are erased for a certain period of time and return to the initial state, so that the output signals 101 and 102 become "L" level. Then, with a slight delay, the output signal 103 of the AND circuit 10 and the control signal 105 themselves become "L" level. That is, figure a,
As shown in b, c, and e, each signal becomes "L" level in preparation for the next count (details of timing are not shown). Incidentally, when the control signal 105 becomes "H" level, the frequency dividing circuit 52 also erases the frequency division contents and restarts counting, but after t time it outputs the output signal 110 and outputs the output signal 102 of the sending circuit 6 for a certain period of time b. The signal is set to "H" level again as shown in FIG. Therefore, at least
False alarm signals can be sent in a shorter time than NT.

Next, during the time T during which an error pulse is sent out from the trigger pulse generation circuit 5, the error pulse is sent to the error pulse counting circuit.
The timing chart for when the number is not input is shown in the fifth section.
As shown in the figure. Output signal 10 of error pulse counting circuit 7
1 is at the "L" level as shown in FIG.
is at the "L" level. Trigger pulse generation circuit 5
When the output signal 104 of the OR circuit 11 changes to "H" level as shown in d of the same figure, the control signal 10 of the OR circuit 11 changes to "H" level as shown in FIG.
5 and changes to the "H" level as shown in the figure e, and the output signal 101 is stored in the same way as described above, the contents of the frequency dividing circuit etc. are erased, and counting starts again, but the signal 109 remains at the "L" level. Therefore, no alarm signal is sent.

In other words, the circuit is equipped with a circuit that sends out signals related to two types of times in which the measurement starts coincide with a time T corresponding to the error rate to be monitored and a fixed time t shorter than the time T, and an error pulse is generated during the period t from the start of counting. When the counting circuit counts k error pulses, the output changes and maintains the state, and the trigger pulse output after t from the start of counting shifts to the N-stage shift register circuit and at the same time erases the counting state of the error pulse counting circuit, etc. and start counting again. Also, t from the start of counting
If k error pulses are not input during this period, the counting state of the error pulse counting circuit from the start of counting to t is maintained, and the error pulse count is started when k error pulses have been counted between t and T. The output state of the circuit is shifted to the N-stage shift register circuit, and at the same time, the counting state of the error pulse counting circuit, etc. is erased, and counting is started again. Also, if k error pulses are not input from the start of counting to T,
After that, a trigger pulse is output, the output state of the error pulse counting circuit is shifted to the N-stage shift register circuit, and at the same time, the counting state of the error pulse counting circuit etc. is erased and counting is started again.

〔Effect of the invention〕

The present invention has a function of preventing the sending of an error alarm signal in response to a sudden error, and when the transmission path changes to a state where the error rate is higher than the error rate that can be monitored, the error can be detected in a shorter time than before. It has the effect of sending out an alarm signal.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a conventional error counting method, Fig. 2 is a block diagram showing an embodiment of the present invention, Figs. 3 a to i, Figs. 4 a to i, and Figs. 5 a to i.
is a timing chart showing various signals in the above embodiment. 1, 5...Trigger pulse generation circuit, 2, 7...
Error pulse counting circuit, 3, 8... N-stage shift register circuit, 4, 9, 10... AND circuit, 6...
Fixed time sending circuit, 11... OR circuit, 51...
... Fixed frequency oscillation circuit, 52 ... Frequency division circuit, 61
...Flip-flop circuit, 22,109...Error alarm signal, 21,111...Error pulse signal.

Claims (1)

[Claims] 1 Generates a first trigger pulse signal and a second trigger pulse signal with a shorter cycle than the first trigger pulse signal at a constant cycle, erases the contents before the input of the control signal with an external control signal, and performs initialization. state and again the first trigger pulse signal and the second trigger pulse signal
a trigger pulse generation circuit that starts generating a trigger pulse signal, and the output state returns to the initial state by the control signal, the output state changes by the second trigger pulse signal, and from then on until the control signal is input again. A sending circuit that holds this output state for a certain period of time, and a certain number of error pulses are counted, and when a certain number is counted, the output state changes and this output state is held, and when the control signal is input, it returns to the initial state. an error pulse counting circuit that starts counting again;
A shift register circuit that shifts the output state of the error pulse counting circuit according to the control signal and stores the past output state of the error pulse counting circuit, and an error alarm signal that is the logical product of the output signals of each stage of the shift register circuit. a first AND circuit that outputs an AND of the output signal of the error pulse counting circuit and the output signal of the fixed time transmission circuit; a logical sum of the output signal of the product circuit and the first trigger pulse signal, which is sent as the control signal to the trigger pulse generating circuit, the fixed time sending circuit, the error pulse counting circuit, and the shift register circuit; An error counting device in a transmission path, characterized in that it includes a circuit.