JPH0426504B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] In an information processing system in which a predetermined amount of data arriving from a communication line is stored in a plurality of reception buffers, the reception buffer is By providing dedicated means for creating a switching signal for switching the receiving buffer, it is possible to reliably switch the receiving buffer.

[Industrial application field]

The present invention relates to a receive data buffer control method that enables reliable switching between a plurality of receive data buffers that accumulate received data arriving from a communication line.

For example, in a line control device of a packet switch, data arriving from a communication line is sequentially stored in a plurality of reception data buffers in a predetermined amount (for example, in units of one frame) by direct memory access control.

In such a case, if the reception data buffer is not switched reliably, the reception data of the next frame will be stored redundantly in the reception data buffer that has already stored reception data, and the stored data will be destroyed. That will happen.

Therefore, it is desired to realize a means for reliably switching the reception data buffer.

[Conventional technology]

FIG. 5 is a diagram showing an example of a conventional received data buffer control method.

In FIG. 5, the information processing system includes a transmitter/receiver (TR) 2 that transmits and receives data to and from an accommodation communication line 1, and two sets of receive data buffers (BFa) 3a and (BFb) that accumulate data received by the transmitter/receiver 2. 3b, a switching unit (CH) 4 that switches between the receiving data buffer 3a or 3b that stores data, and a processor (MPU) that transfers data between the transmitting/receiving unit 2 and the receiving data buffer 3.
6, and a direct memory access control unit (DMAC) 5 which is controlled under the control of 6.

With the switching unit 4 currently selecting 3a as the receive data buffer for storing received data, when data for one frame arrives from the communication line 1,
Direct memory access control section 5, under the control of processor 6, sequentially stores data received by transmitting/receiving section 2 in reception data buffer 3a. 1
When the data for the frame has been received, the transmitting/receiving section 2 starts sending a reception interrupt signal ri to the switching section 4 and the processor 6.

Switching unit 4 detects the start of transmission of reception interrupt signal ri
3a is the receive data buffer that stores data.
Switch from to 3b.

Also, the processor 6 that received the reception interrupt signal ri
When operating without masking interrupts, the transmitting/receiving section 2 stops transmitting the receiving interrupt signal ri.

In this state, when the next frame of data arrives from the communication line 1, it is sequentially stored in the received data buffer 3b in the same manner as described above. After receiving data for one frame, the transmitting/receiving section 2 sends a reception interrupt signal to the switching section 4 and the processor 6 again.
Start sending ri.

Switching unit 4 detects the start of transmission of reception interrupt signal ri
The reception data buffer that stores data is 3b.
Switch from to 3a.

On the other hand, if short frames arrive in succession and the processor 6 does not have enough time to process the received interrupts, the processor 6 operates with the interrupts masked.

In such a case, the processor 6 does not stop transmitting the reception interrupt signal ri sent by the transmitting/receiving section 2, so that the transmitting/receiving section 2 continuously transmits the receiving interrupt signal ri.

Therefore, even after the next frame of received data is stored in the reception data buffer 3b, the switching unit 4 cannot detect the start of sending out the reception interrupt signal ri, and switches the reception data buffer for storing data from 3b to 3a. This will not happen, and the next data arriving from the communication line 1 will continue to be stored in the received data buffer 3b, and the previously received data will be destroyed.

[Problem that the invention seeks to solve]

As is clear from the above explanation, in the conventional receive data buffer control system, the processor 6
If it operates with interrupts masked, there is a risk that the received data buffer will not be switched and the received data will be destroyed.

[Means for solving problems]

FIG. 1 is a diagram showing the principle of the present invention.

In FIG. 1, reference numeral 100 denotes a switching control means that receives the character detection signal CD and the transfer request signal rq from the transmitting/receiving section 2 and transmits the switching signal ch to the switching section 4. One frame of data has arrived from line 1, and the effective characters that make up the received data
After confirming that Ca is switched to the invalid character Cb, the switching signal ch is configured to be output to the switching section 4.

[Effect]

That is, according to the present invention, since the switching control means 100 transmits the switching signal ch to the switching unit 4 regardless of the state of the processor 6, switching of the reception data buffer 3 is reliably executed.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a diagram showing a reception data buffer control method according to an embodiment of the present invention, and FIG.
FIG. 4 is a diagram illustrating an example of the switching control section in FIG. 3, and FIG. 4 is a diagram illustrating various signal waveforms in FIG. 3. Note that the same reference numerals indicate the same objects throughout the figures.

In FIG. 2, a switching control section (CHC) 7 having a configuration as shown in FIG.
It is set as 00.

In FIGS. 2 to 4, it is assumed that valid characters Ca arrive continuously while data is arriving from the communication line 1, and invalid characters Cb continuously arrive after the data arrives. The transmitting/receiving unit 2 transmits a character detection signal cd (logic “0”) and a transfer request signal rq (logic “1”) to the switching control unit 7 every time it receives the valid character Ca that constitutes the received data. .

In the switching control section 7, the flip-flop 7
1, the character detection signal CD is sent to the inverter 7.
5, the transfer request signal rq is input to the R terminal via the inverter 76, and the character detection signal is input to the flip-flop 72.
CD is input to the CP terminal. On the other hand, flip-flops 73 and 74 contain system clock signals.
ck is input to the CP terminal via the inverter 77.

Therefore, while data arrives from the communication line 1 and the character detection signal CD and transfer request signal rq are transmitted from the transmitter/receiver 2, the flip-flop 71 receives the character detection signal CD at the start time t1.
The output signal q1 is set at
The flip-flop 72 sets the output signal q2 to logic "0" and repeats the state in which it is set at the end time t2 of the transfer request signal rq and sets the output signal q1 to logic "0". keep it in the side.

When one frame of data has been received, invalid characters Cb begin to arrive continuously from the communication line 1.

The transmitter/receiver 2 sends a character detection signal to the switching controller 7 every time it receives the invalid character Cb.
CD is transmitted, but the transfer request signal rq is not transmitted.

In the switching control section 7, the flip-flop 71
is set at the start time t3 of the character detection signal CD, and sets and maintains the output signal q1 output from the Q terminal at logic "1". On the other hand, output signal q1
The flip-flop 72 inputs the following to the D terminal:
It is set at the end time t4 of the character detection signal cd, and sets the output signal q2 to logic "1".

In this state, the flip-flop 73 to which the output signal q2 is input to the D terminal is set at the end time t5 of the system clock signal ck (logic "1") input to the CP terminal via the inverter 77.
Set output signal q3 to logic "1". On the other hand, the flip-flop 74 is set at time t5,
At time t5, since the output signal q3 input to the D terminal is still set to logic "0", it is assumed that the output signal q4 output from the terminal is set to logic "1".

As a result of the above, the gate 78 is connected to the flip-flop 7.
At time t5, when the output signal q3 from the flip-flop 74 and the output signal q4 from the flip-flop 74 are both set to logic "1", the output switching signal ch
is set to logic “1”.

The flip-flop 74 receives the system clock signal input to the CP terminal via the inverter 77.
At the next end time t6 of ck, the output signal q4 output from the terminal is set to logic "0".

As a result, the gate 78 outputs the switching signal ch
is set to logic "0" at time t6.

As described above, the switching control section 7 outputs the switching signal ch (logic "1") between time points t5 and t6, and transmits it to the switching section 4.

The switching unit 4, which has received the switching signal ch, switches the reception data buffer in which data received by the transmission/reception unit 2 from the communication line 1 is stored from 3a to 3b.

As is clear from the above description, according to this embodiment, when the switching control unit 7 switches from the valid character Ca to the invalid character Cb after one frame of data has arrived from the communication line 1, the switching control unit 7 always sends the switching signal ch Therefore, the switching unit 4 reliably switches the reception data buffers 3a and 3b after accumulating one frame's worth of data.

Note that FIGS. 2 to 4 are only one embodiment of the present invention, and the configuration of the switching control means 100 is not limited to that shown in the figures, and many other modifications may be considered. However, the effects of the present invention remain the same in either case. Further, the information processing system to which the present invention is applied is not limited to the one shown in the drawings, and many modifications may be considered, such as providing three or more sets of received data buffers, but the present invention will not apply in any case. The effect remains unchanged.

〔Effect of the invention〕

As described above, according to the present invention, in the information processing system, the switching control means transmits the switching signal to the switching unit regardless of the state of the processor, so that switching of the received data buffer is reliably executed.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing a reception data buffer control method according to an embodiment of the present invention, FIG. 3 is a diagram showing an example of the switching control section in FIG. 2, and FIG. This figure is a diagram illustrating various signal waveforms in FIG. 3, and FIG. 5 is a diagram illustrating an example of a conventional received data buffer control method. In the figure, 1 is a communication line, 2 is a transmitting/receiving unit (TBR), 3a and 3b are reception data buffers (BFa and BFb), 4 is a switching unit (CH), 5 is a direct memory access control unit (DMAC), and 6 is a processor. (MPU), 7 is the switching control unit (CHC),
71 to 74 are flip-flops, 75, 76 and 77 are inverters, 78 is a gate, 100 is a switching control means, Ca is an effective character, Cb is an invalid character, CD is a character detection signal, ch is a switching signal, and ck is a system clock. The signals q1 to q4 are output signals, rq is a transfer request signal, rs is a system reset signal, and t1 to t6 are time points.

Claims (1)

[Scope of Claims] 1. Switching between a transmitter/receiver 2 that transmits and receives data to and from the accommodation communication line 1, a plurality of receive data buffers 3 that accumulate data received by the transmitter/receiver 2, and a receive data buffer 3 that accumulates the data. In an information processing system comprising a switching unit 4 and a direct memory access control unit 5 that controls data transfer between the transmitting and receiving unit 2 and the received data buffer 3 under the control of a processor 6, the transmitting and receiving unit 2 A switching control means 100 is provided which receives a character detection signal CD and a transfer request signal rq from the switching section 4 and transmits a switching signal ch to the switching section 4, and the switching control means 100 allows one frame of data to arrive from the communication line 1. After confirming that the valid character Ca that constitutes the received data is switched to the invalid character Cb, the switching signal ch
A received data buffer control method characterized in that the received data buffer is outputted to the switching unit 4.