JPH0426544B2 - - Google Patents
Info
- Publication number
- JPH0426544B2 JPH0426544B2 JP59248484A JP24848484A JPH0426544B2 JP H0426544 B2 JPH0426544 B2 JP H0426544B2 JP 59248484 A JP59248484 A JP 59248484A JP 24848484 A JP24848484 A JP 24848484A JP H0426544 B2 JPH0426544 B2 JP H0426544B2
- Authority
- JP
- Japan
- Prior art keywords
- posts
- row
- semiconductor element
- wire
- post
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
- H10W72/07554—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in dispositions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/547—Dispositions of multiple bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/581—Auxiliary members, e.g. flow barriers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/59—Bond pads specially adapted therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/932—Plan-view shape, i.e. in top view
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/941—Dispositions of bond pads
- H10W72/944—Dispositions of multiple bond pads
- H10W72/9445—Top-view layouts, e.g. mirror arrays
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
(産業上の利用分野)
この発明は半導体装置特に基板上にダイボンデ
イングされた半導体素子とポストとをワイヤボン
デイングして構成される半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device, and particularly to a semiconductor device constructed by wire bonding a semiconductor element die-bonded onto a substrate and a post.
(従来の技術)
半導体チツプ、集積回路等の半導体素子からな
る半導体装置では、基板上に前記半導体素子をダ
イボンデイングするとともに、基板上のポストと
前記半導体素子のボンデイングパツトとを金線の
ようなワイヤでワイヤボンデイングによつて互い
に接続するようにしたものはよく知られている。(Prior Art) In a semiconductor device consisting of a semiconductor element such as a semiconductor chip or an integrated circuit, the semiconductor element is die-bonded onto a substrate, and the post on the substrate and the bonding pad of the semiconductor element are connected with a wire such as a gold wire. It is well known that wires are connected to each other by wire bonding.
一方この種半導体装置ではその半導体素子の高
密度化のためにボンデイングパツトのピツチを小
さく、場合によつては千鳥状に並べるとともに、
基板上のポストを千鳥状に並べることが行われて
いる(実開昭58−107844号公報参照)。しかしこ
のようにポストを千鳥状に配列した場合は、半導
体素子のダイボンデイングの際に位置ずれを起し
たとき、ワイヤとリードとが接触し合う恐れがあ
る。 On the other hand, in this type of semiconductor device, in order to increase the density of the semiconductor element, the pitch of the bonding pads is small, and in some cases, they are arranged in a staggered manner.
The posts on the board are arranged in a staggered manner (see Japanese Utility Model Application Publication No. 107844/1983). However, when the posts are arranged in a staggered manner as described above, there is a risk that the wires and the leads may come into contact with each other when a positional shift occurs during die bonding of a semiconductor element.
これを図面によつて説明すると、第4図におい
て1は基板、2は半導体素子とし、この半導体素
子には複数のボンデイングパツト3が設置されて
あるものとする。図示するボンデイングパツト3
は千鳥状に配列されてある。4は第1の列のポス
ト、5は第2の列のポストで、前記第1の列のポ
ストは半導体素子2に向い合うように並び、第2
の列は第1の列よりも半導体素子2から離れて並
ぶようにしてある。なお各ポストは基板1上に設
置されてある。 To explain this with reference to the drawings, in FIG. 4, 1 is a substrate, 2 is a semiconductor element, and a plurality of bonding pads 3 are installed on this semiconductor element. Bonding part 3 shown
are arranged in a staggered manner. 4 is a first row of posts; 5 is a second row of posts; the first row of posts are arranged to face the semiconductor element 2;
The columns are arranged further away from the semiconductor element 2 than the first column. Note that each post is installed on the substrate 1.
各列のポストは交互に並ぶことによつて千鳥状
に配列されてある。6は第1の列の各ポスト4に
連なるリード、7は第2の列の各ポスト5に連な
るリード、8は第1の列のポスト4と一方の列の
各ボンデイングパツト3とを接続するワイヤ、9
は第2の列のポスト5と他の列の各ボンデイング
パツトとを接続するワイヤで、いずれもワイヤボ
ンデイングされてある。 The posts in each row are arranged in a staggered manner by alternating each other. 6 is a lead connected to each post 4 in the first row, 7 is a lead connected to each post 5 in the second row, and 8 is a lead connected to each post 4 in the first row and each bonding pad 3 in one row. wire, 9
are wires connecting the posts 5 in the second row and each bonding pad in the other rows, all of which are wire-bonded.
半導体素子2が基板1上の規定の箇所にダイボ
ンデイングされた場合は何等の問題はない。すな
わちこの場合は後記する第1図に示すように各ボ
ンデイングパツト3とこれに接続されるポスト
4,5は互いに正しく向い合うようになり、した
がつてワイヤ9は第1の列のポスト4或いはその
リード6をまたぐようなことはない。 If the semiconductor element 2 is die-bonded to a specified location on the substrate 1, there will be no problem. In other words, in this case, each bonding pad 3 and the posts 4 and 5 connected thereto face each other correctly as shown in FIG. There is no way to cross that lead of 6.
しかし半導体素子2が規定の箇所よりずれてダ
イボンデイングされたとすると、第4図に示すよ
うに第2の列のポスト5に接続されるワイヤ9は
第1の列のポストまたはそのリード6をまたぐよ
うになる。通常この種ワイヤは後記する第2図に
も示すように、ボンデイングパツトとボストとの
間を垂れ下がるようにして張られる。そのため前
記第2の列のポスト5に接続されるワイヤ9はこ
れが垂れ下がることによつてこれがまたいでいる
第1の列のポスト4またはこれに連なるリード6
に接触してしまうことがある。 However, if the semiconductor element 2 is die-bonded at a position shifted from the specified position, the wire 9 connected to the post 5 in the second row will straddle the post or its lead 6 in the first row, as shown in FIG. It becomes like this. Usually, this type of wire is stretched so as to hang down between the bonding pad and the post, as shown in FIG. 2, which will be described later. Therefore, the wire 9 connected to the second row of posts 5 hangs down, and the wire 9 straddles the first row of posts 4 or the lead 6 connected thereto.
may come into contact with.
(発明が解決しようとする問題点)
この発明は半導体素子とポストとを接続するワ
イヤの接触による事故の発生を簡単な構成によつ
て確実に回避することを目的とする。(Problems to be Solved by the Invention) It is an object of the present invention to reliably avoid accidents caused by contact between wires connecting a semiconductor element and a post using a simple configuration.
(問題点を解決するための手段)
この発明は基板上のポストの第1の列と第2の
列との間に、前記第1の列のポストに連なるリー
ドを覆うように絶縁層を設置したことを特徴とす
る。(Means for Solving the Problems) This invention provides an insulating layer between a first row of posts and a second row of posts on a substrate so as to cover the leads connected to the posts of the first row. It is characterized by what it did.
この発明を図によつて説明する。なお第4図と
同じ符号を付した部分は同一または対応する部分
を示す。第1図の構成から理解できるように、こ
の発明では第1のポスト4の列と第2のポスト5
の列との間に絶縁層10を設置する。この絶縁層
10は第1の列のポスト4に連なるリード6を覆
うように設置されてある。 This invention will be explained using figures. Note that parts given the same reference numerals as in FIG. 4 indicate the same or corresponding parts. As can be understood from the configuration of FIG.
An insulating layer 10 is installed between the rows of. This insulating layer 10 is placed so as to cover the leads 6 connected to the posts 4 in the first row.
(作用)
第1図は半導体素子2が基板1上の規定位置に
ダイボンデイングされたときの状態を示し、この
ときは各ワイヤ8,9はそれぞれ互いに平行する
ようにしてある。したがつて各ワイヤはポスト
4,5並びにこれに連なるリード6,7の上方を
通過するようなことは何等ない。(Operation) FIG. 1 shows a state in which the semiconductor element 2 is die-bonded at a prescribed position on the substrate 1, and at this time, the wires 8 and 9 are parallel to each other. Therefore, each wire never passes over the posts 4, 5 and the leads 6, 7 connected thereto.
しかし半導体素子2が第3図に示すように規定
位置よりずれてダイボンデイングされた場合、ワ
イヤ9がポスト4またはこれに連なるリード6の
上方を通過するとしても、、絶縁層10が存在し
ているので、ワイヤ9はこの絶縁層10の表面に
支持され、これをこえて下方に垂れ下がるような
ことはない。そしてこの絶縁層10はポスト4に
連なるリード6を覆つているので、ワイヤ9はポ
スト4にはもちろんリード6にも接触することは
ない。のみならずこのように半導体素子のダイボ
ンデイング位置がずれてもワイヤの接触が防止で
きることから、そのダイボンデイング位置の精度
ゆるくすることもできるようになる。 However, if the semiconductor element 2 is die-bonded at a position shifted from the specified position as shown in FIG. Therefore, the wire 9 is supported by the surface of the insulating layer 10 and does not hang down beyond the surface. Since this insulating layer 10 covers the leads 6 connected to the posts 4, the wires 9 do not come into contact with the posts 4 or even the leads 6. Furthermore, even if the die bonding position of the semiconductor element shifts, contact of the wire can be prevented, so that the accuracy of the die bonding position can be made looser.
(発明の効果)
以上詳述したようにこの発明によれば、第1の
列のポストと第2の列のポストとの間に絶縁層を
設置し、これによつて半導体素子のボンデイング
パツトからポストに向かうワイヤが第2の列のポ
ストまたはこれに連なるリードに接触するのを簡
単に防止することができるし、更に半導体素子の
ダイボンデイング位置を高精度とする必要もな
く、したがつてそれだけ工程管理上、許容基準を
ゆるく認定できるので、工程の歩留まりが向上
し、生産性を高めることができるようになるとい
つた効果を奏する。(Effects of the Invention) As described in detail above, according to the present invention, an insulating layer is provided between the posts of the first row and the posts of the second row, thereby making it possible to separate the bonding pads of the semiconductor element. It is possible to easily prevent the wires heading toward the posts from coming into contact with the posts in the second row or the leads connected thereto, and there is also no need to make the die bonding position of the semiconductor element highly accurate. In terms of process control, the acceptance criteria can be certified more leniently, which has the effect of improving the yield of the process and increasing productivity.
第1図はこの発明の実施例を示す平面図、第2
図は同断面図、第3図は動作状態を示す平面図、
第4図は従来例を示す平面図である。
1……基板、2……半導体素子、3……ボンデ
イングパツト、4……第1の列のポスト、5……
第2の列のポスト、6,7……リード、8,9…
…ワイヤ。
Figure 1 is a plan view showing an embodiment of the invention, Figure 2 is a plan view showing an embodiment of the invention.
The figure is a sectional view of the same, and Figure 3 is a plan view showing the operating state.
FIG. 4 is a plan view showing a conventional example. DESCRIPTION OF SYMBOLS 1... Substrate, 2... Semiconductor element, 3... Bonding pad, 4... First column post, 5...
Second row posts, 6, 7... Leads, 8, 9...
...Wire.
Claims (1)
ポストとをワイヤで接続してなる半導体装置にお
いて、前記ポストを前記半導体素子側に沿つて並
ぶ第1の列と、前記第1の列より前記半導体素子
から離れている位置に並びかつ前記第1の列のポ
ストに対して千鳥状に配置されてある第2の列と
によつて構成し、前記第1のポストと第2の列の
ポストとの間に、前記第1の列のポストに連なる
リードを覆う絶縁層を設置してなる半導体装置。1. In a semiconductor device in which bonding pads of a semiconductor element and posts on a substrate are connected by wires, the posts are arranged in a first row along the semiconductor element side, and the posts are connected from the semiconductor element in the first row. and a second row arranged at a distance from each other and arranged in a staggered manner with respect to the first row of posts, and between the first and second row of posts. and an insulating layer covering the leads connected to the posts in the first row.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59248484A JPS61127140A (en) | 1984-11-24 | 1984-11-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59248484A JPS61127140A (en) | 1984-11-24 | 1984-11-24 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61127140A JPS61127140A (en) | 1986-06-14 |
| JPH0426544B2 true JPH0426544B2 (en) | 1992-05-07 |
Family
ID=17178841
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59248484A Granted JPS61127140A (en) | 1984-11-24 | 1984-11-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61127140A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2598129B2 (en) * | 1989-05-18 | 1997-04-09 | 三菱電機株式会社 | Semiconductor device |
-
1984
- 1984-11-24 JP JP59248484A patent/JPS61127140A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61127140A (en) | 1986-06-14 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |