JPH0426791B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device having an input protection circuit.

CMOS (Complementary MOS) type LSIs have an input protection circuit on the input side to protect the gate. Various types of protection circuits have been proposed, but upon investigation by the present inventor, it has been found that none of them yields satisfactory results. That is,
For example, input pad and CMOS MIS (Metal
Insulator Semiconductor) When a diffused resistor and a clamp diode are connected between the gate of FET, the junction breakdown voltage becomes low because the diffused resistor is formed shallowly due to fine patterning.
When an abnormal voltage is applied from the pad side, the space between the diffusion region and the semiconductor substrate is likely to be destroyed. Furthermore, if a polysilicon film formed on a semiconductor substrate is used as a protective resistor instead of the above-mentioned diffused resistor, this polysilicon resistor cannot allow current to flow to the semiconductor substrate, so the area of the clamp diode must be increased accordingly. Therefore, it becomes necessary to provide a breakdown voltage, which is disadvantageous for fine patterning (high integration).

Therefore, the present invention is based on the above recognition,
Semiconductor devices with built-in protection circuits that occupy a small area but have sufficient protection functions, such as CMOS type
The purpose is to provide LSI.

To achieve this objective, according to the invention:
By not only providing a deep well region in the part of the semiconductor region that serves as a protective resistor to which high voltage is applied (particularly the connection region with the input pad), but also by expanding the area of the contact in that part, the junction breakdown voltage there can be increased. The aim is to increase the

Hereinafter, an embodiment in which the present invention is applied to a CMOS type LSI will be described in detail with reference to the drawings.

Figures 1 to 3 show the first stage of CMOS type LSI.
It shows a CMOS inverter and its input protection circuit section.

That is, on one main surface side of the common N-type silicon substrate 1, there are arranged a P-channel MISFETQ ₁ and an N-channel MISFETQ ₂ constituting a CMOS, a clamp diode _D1 and a diffusion resistor R constituting a gate protection circuit for these FETs. are provided for each. The diffused resistor R consists of a shallow, small-area P ⁺ type region 2 and a relatively deep P ^- type well region 3 connected thereto. The depth of P ⁺ type region 2 is about 0.5 μm and the width is 6 μm.
The well region 3 has a depth of about 4 μm and an area of 24 μm×24 μm. Therefore,
In the region where the aluminum wiring 4 extending from the input pad is connected to the diffused resistor R, the area of the junction with the substrate 1 is considerably expanded due to the presence of the well region 3. In other words, the PN junction diode _D2 formed by this junction has a large junction area, and even if it is integrated with the protective resistor R, it is installed at the position where the highest voltage is most likely to be applied (easily destroyed). This is extremely important. Resistor R is a clamp diode by aluminum wiring 5.
It is connected to the N ⁺ type diffusion region 6 of D ₁ , and this diffusion region is also commonly connected to each gate electrode 7 and 8 of FET Q ₁ and Q ₂ . Well region 3 of resistor R and P ^- type well region 9 of clamp diode _D1.
The P ^- type well region 10 of FETQ ₂ was formed at the same time in the same diffusion process, and the resistor R
P ⁺ type region 2 and P ⁺ type diffusion regions 11 and 12 of FETQ ₁ ,
N ⁺ type region 6 of clamp diode D ₁ and FETQ ₂
N ⁺ type diffusion regions 13 and 14 were also formed in the same process. In addition, 15, 16 and 17 are
Each aluminum wiring or electrode of CMOS,
18 is a field SiO ₂ film, 19 is a gate oxide film,
20 is a SiO ₂ film grown on the surface of a polysilicon gate electrode, and 21 is a phosphorus silicate glass film.

What should be noted here is that, as shown in FIG.
is in contact with the input side of the resistor over an area that is sufficiently larger than the area of contact through the contact hole 29. As a result, when a surge voltage is applied to the input pad 4, the contact part on the input side of the resistor 2 has a large area, so the surge current is evenly distributed and supplied to the PN junction on the input side of the resistor. This can improve the breaking strength of the resistor 2. Of course, from the input pad to the diffused resistor 2
The area of the PN junction in the region where the PN junction falls into the This is extremely effective in that it can supply surge current evenly.

Therefore, sufficient gate protection (electrostatic breakdown strength) can be achieved. Specifically, due to the use of large-area contacts, when a positive abnormal input enters the diffused resistor R, the diode _D2 becomes forward and current flows to the substrate 1, and when a negative abnormal input occurs, Surge current can be passed evenly across the large junction area of diode _D2 . Therefore, no matter which abnormal voltage is applied, the input protection circuit according to this example exhibits sufficient breakdown strength.

Next, a method for creating the structure shown in FIG. 1 will be explained with reference to FIG.

First, as shown in FIG. 4A, an N-type silicon substrate 1
Using the SiO ₂ film 22 formed on one main surface as a mask,
Impurities for each well region mentioned above (e.g. boron)
The introduction of the P - type well regions 3, 9, and 10 are carried out by, for example, ion implantation or diffusion techniques, and are formed by stretch diffusion in relatively deep P ^- type well regions 3, 9, and 10, respectively.

After removing the mask 22, as shown in FIG. 4B, a field SiO ₂ film 18 is grown in a predetermined pattern by a known selective oxidation technique using the silicon nitride film 23 as a mask to isolate each element region.

Next, after removing the silicon nitride film 23 and the underlying SiO ₂ film 24 by sequential etching, a gate oxide film 19 is formed by heat treatment in an oxidizing atmosphere, as shown in FIG. 4C, and then by chemical vapor deposition. (CVD)
Polysilicon is deposited on the entire surface. After this polysilicon film is subjected to a known phosphorus treatment, a known photoetching process is performed to form polysilicon films 7 and 8 in the shape of gate electrodes.

Next, after thermally oxidizing the surfaces of the polysilicon films 7 and 8 to form a thin SiO ₂ film 20, only the well regions 9 and 10 are covered with a mask 24, as shown in FIG. 4D.
For example, it is coated with photoresist, and in this state, the entire surface is irradiated with an ion beam 25 of boron or the like. As a result, impurities in the substrate 1 are implanted through the gate oxide film 19 in the region where the mask 24, the polysilicon film 7, and the field SiO ₂ film 18 are not present.
Through annealing, P ⁺ type regions 2, 11, and 12 are formed, respectively. Of these, the P ⁺ type region 2 is formed to overlap the well region 3, and together constitute the above-mentioned protective resistor R and diode _D2 .

Next, as shown in Figure 4E, from now on, P ⁺ type region 2
Then, only the area of FETQ ₁ is covered with a mask 26, for example, a photoresist, and the entire surface is irradiated with a phosphorus or arsenic _ion beam 27. Ion implantation is performed through gate oxide film 19 and annealing is performed to form N ⁺ type regions 6, 13, and 14 in each well region 9 and 10, respectively.

Next, as shown in Figure 4F, after removing only the gate oxide film in the protection circuit area by etching, CVD
A phosphosilicate glass film 21 is applied to the entire surface,
This was photo-etched and contact holes 28, 29, 30, 31, 32,
33 and 34 are formed, respectively. Next, aluminum is deposited on the entire surface using vacuum evaporation technology, for example.
This was patterned by photo etching and the first
Each aluminum wiring or electrode 4, 5, 15,
16 and 17 are formed. Contact holes 28 are formed at four locations on region 3 (see FIG. 2) to ensure sufficient contact. Although not shown, an interlayer insulating film, a second layer of aluminum wiring, a final packaging film, etc. are further applied to complete the IC.

Although the present invention has been illustrated above, the embodiments described above can be further modified based on the technical idea of the present invention. For example, the shape of the well region 3 described above may be changed in various ways. Further, the conductivity type of each semiconductor region described above may be converted to an opposite conductivity type. Note that the present invention
It can also be applied to protection circuits for next-stage circuits other than CMOS.

[Brief explanation of drawings]

The drawings show an embodiment in which the present invention is applied to a CMOS type LSI. Fig. 1 is a cross-sectional view of the CMOS and gate protection circuit section, and Fig. 2 is a plan view of the gate protection circuit section (its X- (The X-ray cross section corresponds to FIG. 1), FIG. 3 is an equivalent circuit diagram of FIG. 1, and FIGS. 4A to 4F are cross-sectional views showing the method of manufacturing the structure of FIG. 1 in order of steps. In addition, in the symbols used in the drawings, 3
is a P ^- type well region, 4 and 5 are aluminum wiring, R is an input protection resistor, D ₁ is a clamp diode, D ₂ is a junction diode, Q ₁ and Q ₂ are each MISFET that constitutes CMOS, 28 and 29 are through holes. Each contact portion provided with a hole is shown.

Claims (1)

[Scope of Claims] 1. A complementary MISFET formed on one main surface of a semiconductor substrate, and an electrical connection between the gate and an input pad for protecting the gate of the MISFET, and a complementary MISFET formed on one main surface of the semiconductor substrate. In a semiconductor device having a semiconductor resistance region formed in
A MISFET indicating one conductivity type channel of the complementary MISFET is formed in a well region exhibiting a predetermined conductivity type, and the semiconductor resistance region has a first region having the same conductivity type and the same depth as the well region; The semiconductor has a second region of the same conductivity type as the first region and is shallowly formed with a higher impurity concentration than the first region, and is in contact with a metal wiring electrically connected to the input pad. At one end of the resistance region, the second region is located below the first region, and the contact area with the metal wiring at one end is larger than the contact area of the metal wiring that is in contact with the other end on the gate side of the semiconductor resistance region. A semiconductor device characterized by being made larger. 2. The semiconductor device according to claim 1, wherein the contact portion at one end of the semiconductor resistance region is divided into a plurality of parts.