JPH04280422A - Manufacturing method of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to LDD (Light
The present invention relates to a method for manufacturing a semiconductor device in which a source/drain region in a MOS transistor having a doped drain structure is formed using an oblique ion implantation method.

0002

2. Description of the Related Art Conventionally, in Hi-CMOS, NMOS and PMOS whose gate length is 1.2 .mu.m or less have different drain structures in order to reduce short channel effects. For example, LDD (Lightly
Doped Drain) structure, etc. The LDD structure has a high concentration (n
+ ) at the drain end between the impurity region and the drain,
By forming a low concentration (n-) impurity region, the structure is such that it is not necessary to increase the electric field of the depletion layer formed at the end of the drain. Furthermore, as devices become smaller due to scaling laws, the depth of diffusion layers such as sources and drains also needs to be made shallower, but this LDD structure does not increase the depth of the diffusion layers and instead Since the length can be increased, it is mainly used in the Hi-CMOS.

As a method for forming the source/drain regions of such an LDD structure, there is a method of rotational implantation using oblique ion implantation. This method is a convenient method in which a source/drain region and a low concentration impurity region can be formed at the same time.

0004

[Problems to be Solved by the Invention] Generally, 1015-1
When performing ion implantation of about 0.016 cm-2, a large current ion implanter is used. However, if this large current ion implanter is used for the above-mentioned oblique ion implantation method, the implantation angle cannot be changed with this large current ion implanter. It can only be changed within the range of 0 degrees to 10 degrees, for example 30 degrees to 60 degrees.
A disadvantage arises in that it is not possible to obtain a desired angle within a degree range.

In addition, when trying to increase the beam current in a medium current ion implanter, with a normal resist,
A beam current of 00 μA or more also causes problems such as resist damage.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that solves the above-mentioned problems, allows oblique implantation with a large beam current at a desired implantation angle, and does not damage the resist or the like. There is something to do.

[0007]

[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention has a gate electrode and a high concentration impurity region for source/drain, and has a structure in which the high concentration impurity region and the gate electrode are connected to each other. In manufacturing an LDD structure MOS transistor with a low concentration impurity region between the source and
Before performing ion implantation to form the drain region,
A semiconductor device characterized in that after a resist used as a mask is hardened, ions are implanted at a predetermined beam current using a medium current ion implantation device at an angle of 30 degrees to 60 degrees with respect to the substrate surface. Provides a manufacturing method.

[0008]

[Function] The manufacturing method of the present invention makes it easy to adjust the implantation angle, since when the source/drain regions of an LDD structure MOS transistor are manufactured using a high-current ion implantation device, the number of steps increases due to sidewall formation. This is particularly effective when performing oblique ion implantation using a medium current ion implanter.

The medium current ion implantation device can hold a wafer with a gate formed thereon by tilting the implantation angle at about 30 to 60 degrees with respect to the substrate surface, and then inserts a resist onto this held wafer as a mask. A low concentration impurity region is formed using the source/drain region and the gate as a mask. The reason why the implantation angle is about 30 to 60 degrees with respect to the substrate surface is that this angle is necessary for using the thickness of the gate as a mask.

[0010] The wafer is held in the implantation chamber such that the beam forms a predetermined angle within 30 to 60 degrees with respect to the substrate surface.

The medium current ion implantation apparatus is generally used at a beam current of 400 .mu.A or less when the dose is 5.times.10.sup.14 cm.sup.-2 or less. However, in this invention, when the ion species is arsenic as a special condition of use, the dose is set to 1015 to 1016.
/cm2, and the beam current is in the range of 900 to 1000 μA.

[0012] Further, the resist used as a mask is hardened by UV curing or the like and then ion implanted.

[0013]

[Examples] Examples of the present invention will be described in more detail below.

The ion implantation method practiced in accordance with the present invention is performed using a medium current ion implanter.

The beam current varies depending on the type of ion to be implanted. For example, boron (B-) has a high diffusion coefficient, so the maximum beam current is about 600 μA, and there is no need to consider that high energy, so it is excluded from this study, but phosphorus (P+) and arsenic (As+) are not considered.
), the maximum beam current is about 1500 μA even in a medium current ion implanter, so the beam current is 9
It can be implemented in the range of 00 to 1000 μA. Further, when manufacturing a semiconductor device having an LDD structure, As ions are preferably used as the ion species implanted into the low concentration (n-) region.

When the beam current is increased, the mask material (
Since the problem of deterioration of the resist (resist), that is, resist damage occurs, a conventionally known resist curing method or other resist damage prevention measures are required. For example, after applying a resist, exposing it to light, developing it, and patterning it, the resist may be cured by irradiating it with ultraviolet light. In this case, an ultraviolet curing resist is used as the resist.

LD using a medium current ion implanter
A method for forming a D-structure MOS transistor will be explained.

First, for example, a UV-curable resist is patterned with windows opened in the region where ions are to be implanted.
After curing treatment by irradiating ultraviolet rays, the wafer or ion beam is tilted at an implantation angle of 30 to 60 degrees with respect to the vertical direction of the wafer, and a predetermined amount, for example, a dose of 5 x 1015 is first implanted from one direction. Inject at about /cm2,
Oblique ion implantation is then performed by reversing the orientation of the wafer 180 degrees and implanting at the same implant angle and dose. As shown in FIGS. 1 and 2, after the gate electrode 1 formed on the gate oxide film 2 is hardened, an ion beam is implanted at a low dose to obliquely ion the ion beam as shown by the dotted line in FIG. A low concentration impurity region 3 is formed by implantation. Next, as shown by the solid line in FIG. 2, an ion beam is implanted using the thickness of the gate electrode 1 as a mask to form a high concentration impurity region 4.

In addition, when inverting the wafer four times and performing oblique ion implantation, the same operation is performed by changing the position to 0 degrees, 90 degrees, 180 degrees, and 270 degrees with respect to the initial position of the wafer, and implanting the ions respectively. You can also tilt the beam.

In addition, when a rotating motor and a rotating disk are provided on a support, ions are implanted while the wafer is rotated relative to the ion beam, and a low concentration impurity region and a high concentration impurity region are separated. are formed simultaneously to form source/drain regions.

According to this semiconductor device manufacturing method, the LD
The source/drain regions of the D structure can be formed by one ion implantation. By increasing the beam current, the processing time is shortened and the processing speed is increased. For example, when comparing a 6-inch wafer per wafer, when implanting 5 x 1015 ions/cm-2, conventional implantation time was about 8 minutes with a beam current of 400 μA or less, whereas with the present invention, When implanting with a beam current of 900 to 1000 μA, it can be implanted in 3 to 3.5 minutes, so when comparing the number of wafers with 25, it takes 3 hours and 20 minutes with the conventional method, but with the present invention, it takes 1 hour and 20 minutes.
It was confirmed that ion implantation could be performed in 15 to 30 minutes.

The above comparison was simply a comparison of ion implantation, but if it is used to form source and drain regions at once by oblique ion implantation with an implantation angle of 30 to 60 degrees to the substrate surface, automated production is possible. This is an effective method because it greatly increases throughput.

As described above, the embodiments of the present invention are as follows:
General MOS transistors are manufactured using a medium current ion implanter that can be beam deflected or mechanically supported obliquely as an ion implanter so that oblique ion implantation can be performed at a wide angle of 0 to 60 degrees. Although the present invention has been described for the case of manufacturing NMOS or PMOS transistors, it can also be applied to CMOS transistors.

[0024]

According to the present invention, a wafer on which a gate material layer has been formed is held by tilting the implantation angle at about 30 to 60 degrees with respect to the substrate surface, and a resist is applied to the held wafer as a mask. forming source/drain regions;
In addition, since a low concentration diffusion layer is formed using the gate as a mask, if this method is used to form the source/drain regions of an LDD structure, it can be achieved with a single ion implantation, increasing the processing speed. It gets faster. Therefore, throughput increases during automated production.

[Brief explanation of the drawing]

FIG. 1 is a conceptual diagram showing how a low concentration impurity region is formed by oblique ion implantation.

FIG. 2 is a conceptual diagram showing how a high concentration impurity region is formed by oblique ion implantation.

[Explanation of symbols]

1 Gate electrode, 2 Gate oxide film, 3 Low concentration impurity region, 4 High concentration impurity region, 5　Substrate

Claims (1)

[Claims] 1. An LDD having a gate electrode, a high concentration impurity region for source/drain, and a low concentration impurity region between the high concentration impurity region and the gate electrode.
In manufacturing a MOS transistor with this structure, in order to form source/drain regions, before performing ion implantation, the resist used as a mask is hardened, and then a predetermined beam current is applied using a medium current ion implantation device. A method of manufacturing a semiconductor device, characterized in that ion implantation is performed at an angle of 30 degrees to 60 degrees with respect to the substrate surface.