JPH0428192B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a vertical deflection circuit for deflecting an electron beam of a picture tube.

(Prior Art) A capacitor that generates a sawtooth voltage between its terminals when charging and discharging is performed, and a capacitor that rapidly a charging circuit that charges the capacitor; a discharging circuit that discharges the capacitor at a constant rate when the terminal voltage of the capacitor reaches a second reference potential higher than the first reference potential; A reference potential generation circuit that generates a first reference potential and a second reference potential, and the first
and a vertical deflection circuit which amplifies the sawtooth wave voltage generated in the capacitor and causes a sawtooth wave current to flow through the deflection coil in addition to the deflection coil of the picture tube. An example of a conventional circuit is shown in FIG.

In Fig. 9, 31 is an input terminal for the synchronizing signal 4Ps, 1 is a coupling capacitor, and 2, 3
is a bleeder resistor for determining the first reference potential V1, and the bleeder resistors 2 and 3 are connected between the operating power supply Vcc and the ground, and the connection point of the resistors 2 and 3 is connected between the operating power supply Vcc and the ground. A is connected to the inverting input terminal of the comparator 6, and the electronic switch 1
It is connected to one contact of 0. The other contact of the electronic switch 10 described above is connected to the power supply Vcc via a resistor 8 (oscillation acceleration resistor 8).

The non-inverting input terminal of the comparator 6 is connected to one contact of the electronic switch 9, and the non-inverting input terminal of the comparator 6 is connected between the terminals due to charging and discharging. A capacitor 4 that generates a sawtooth voltage (hereinafter simply referred to as capacitor 4), a constant current source 5, and a vertical deflection circuit 11
is also connected.

The other contact of the electronic switch 9 described above is connected to the power supply Vcc via the charging resistor 7. A vertical deflection coil 12 is connected to the output side of the vertical deflection circuit 11 .

In the conventional vertical deflection circuit shown in FIG. 9, since there is no charge in capacitor 4 when the power is turned on, the terminal voltage of capacitor 4 is zero, and the voltage at the non-inverting input terminal of comparator 6 is zero. The voltage is also zero. On the other hand, the voltage at the connection point A of the bleeder resistors 2 and 3 connected to the inverting input terminal of the comparator 6 is
When the power is turned on, the first reference voltage V1 is reached, so the output of the comparator 6 in this state turns on the electronic switches 9 and 10, and the capacitor 4 is connected to the power supply Vcc→resistor 7→electronic switch 9. →
Charging is started by the charging circuit connecting the capacitor 4 to the ground, and the electronic switch 10, which is turned on together with the electronic switch 9 described above,
By connecting the resistor 8 in parallel to the bleeder resistor 2 described above, the voltage at point A is equal to the first reference potential V.
1, the voltage rises to a second reference potential V2 having a relationship of V1<V2. Time t1 in FIG. 10 is the time when the power is turned on.

When the terminal voltage of the capacitor 4 charged by the charging circuit described above, that is, the voltage at the non-inverting input terminal, reaches the voltage at the inverting input terminal, which is set as the second reference potential V2, the output of the comparator 6 is reversed and both electronic switches 9 and 10 are turned off, so that the potential at point A becomes the first reference potential V determined by the bleeder resistors 2 and 3.
1, and the voltage at the inverting input terminal of the comparator 6 is brought to the first reference potential V1. In FIG. 10, time t2 is the point in time when the potential at point A changes from the second reference potential V2 to the second reference potential V2.

On the other hand, the accumulated charge of the capacitor 4, which has been charged by the charging circuit described above until the terminal voltage reaches the second reference potential V2, is transferred to the electronic switch 9 as described above.
Since it is discharged at a constant rate by the constant current source 5 from the time t2 when the capacitor 4 is turned off, the terminal voltage of the capacitor 4 becomes as shown in the period from time t2 to t3 in Fig. 10. decreases linearly with a constant slope.

The terminal voltage of capacitor 4, that is, comparator 6
When the voltage at the non-inverting input terminal of the comparator 6 reaches the voltage at the inverting input terminal of the comparator 6, that is, the first reference potential V1 at time t3, the output of the comparator 6 is inverted at the time t3, and the electronic switch 9, 10 both change to the on state at time t3.

The on/off operation of the electronic switches 9 and 10 after time t3 is the same as that described for the period from time t1 to t3, and the terminal voltage of the capacitor 4 is a sawtooth wave voltage as shown in FIG.
Vs and is supplied to the vertical deflection circuit 11, causing a sawtooth wave current Is to flow through the deflection coil 12 connected to the output side of the vertical deflection circuit 11.

The period Tf of free-running oscillation in the circuit described above is
As can be seen from FIG. 10, it changes depending on the magnitude of the first reference potential V1, and therefore,
The period of the sawtooth voltage in this type of circuit is usually adjusted by changing the resistance values of the bleeder resistors 2 and 3.

Next, the operation when the synchronizing signal Ps is supplied to the input terminal 31 for the synchronizing signal Ps in the vertical deflection circuit shown in FIG. 9 will be described.

Period of synchronization signal Ps supplied to input terminal 31
When the synchronizing signal Ps of Ts is applied to point A via the coupling capacitor 1, the potential at point A changes to the above-mentioned first
The reference potential V1 and the synchronizing signal Ps having a period of Ts are superimposed.

Now, the period Tf of free-running oscillation in the vertical deflection circuit
is made slightly shorter than the period Ts of the synchronizing signal Ps, the period of the sawtooth wave voltage Vs generated in the vertical deflection circuit is As is well known, this is done to match the period Ts of the synchronizing signal Ps supplied to point A.

That is, if the period Tf of free-running oscillation in the vertical deflection circuit is made slightly shorter than the period Ts of the synchronizing signal Ps, as shown in FIG. Oscillation period Tf
When the voltage of the sawtooth wave voltage Vs generated in the vertical deflection circuit reaches the voltage value obtained by adding the peak value of the synchronizing signal Ps to the first reference potential V1, the output of the comparator 6 is inverted. The period of the sawtooth wave voltage Vs output from the input terminal 31 of the synchronization signal Ps is
The period Ts of the synchronizing signal Ps supplied from the coupling capacitor 1 to the point A is made to match the period Ts.

However, if the period Ts of the synchronizing signal Ps is too long or too short compared to the free-running oscillation period Tf in the vertical deflection circuit, the sawtooth wave voltage generated in the vertical deflection circuit The period of Vs cannot be made to match the period Ts of the synchronizing signal Ps supplied from the input terminal 31 of the synchronizing signal Ps to the point A via the coupling capacitor 1.

That is, the period Tf of free-running oscillation in the vertical deflection circuit is, for example, as shown in FIG.
If the period is too long compared to the period Ts of the synchronization signal Ps, the voltage at the inverting input terminal of the comparator 6 indicates a voltage value obtained by adding the peak value of the synchronization signal Ps to the first reference potential V1. The sawtooth wave voltage generated in the vertical deflection circuit with the free-running oscillation period Tf.
Since the voltage of Vs is higher than the voltage value of the inverting input terminal of the comparator 6, that is, the voltage value obtained by adding the peak value of the synchronizing signal Ps to the first reference potential V1, the comparator 6 is never inverted, and the period of the sawtooth wave voltage Vs output from the vertical deflection circuit remains the original free-running oscillation period Tf.

Also, contrary to the above case, when the period Tf of free-running oscillation in the vertical deflection circuit is too short compared to the period Ts of the synchronizing signal Ps, as shown in FIG. , occurs at the free-running oscillation period Tf in the vertical deflection circuit in a state where the voltage at the inverting input terminal of the comparator 6 indicates the voltage value obtained by adding the peak value of the synchronizing signal Ps to the first reference potential V1. The voltage of the sawtooth wave voltage Vs is higher than the voltage value of the inverting input terminal of the comparator 6, that is, the voltage value obtained by adding the peak value of the synchronizing signal Ps to the first reference potential V1. Therefore, the output of the comparator 6 is never inverted, and the period of the sawtooth wave voltage Vs output from the vertical deflection circuit remains the original free-running oscillation period Tf.

Therefore, the period Ts of the synchronizing signal Ps supplied from the input terminal 31 of the synchronizing signal Ps to point A via the coupling capacitor 1 is equal to the period Tf of free-running oscillation of the sawtooth wave voltage generated in the vertical deflection circuit. If it is too long or too short compared to
It is necessary to make the period close to Ts, and for this purpose, usually either resistor 2 or 3 in Fig. 9 is a variable resistor, and it is used as a vertical synchronization regulator. 1 reference potential V1 is changed.

(Problem to be Solved by the Invention) The above-described solution is such that when the vertical scanning period is fixed at a specific value, for example, the system operates in accordance with a specific standard television system. When applied to a television receiver configured in When the vertical scanning frequency of the display device in computer-related equipment, which has become extremely popular over the years, uses various frequencies within a wide frequency range, for example, from 50Hz to 90Hz, the above-mentioned Even if one tries to adjust the free-running oscillation frequency in the vertical deflection circuit by applying the above-mentioned solution to a wide frequency range, it becomes difficult to adjust within the variable range, so it is difficult to Therefore, when producing the above-mentioned equipment, it is necessary to set different circuit constants depending on the vertical scanning frequency required by the equipment. The company had no choice but to manufacture the equipment by adopting a different format, which inevitably led to higher costs.

(Means for Solving the Problems) The present invention provides a capacitor that generates a sawtooth voltage between terminals when charging and discharging is performed, and a voltage between the terminals of the capacitor that reaches a first reference potential. and a charging circuit that rapidly charges the capacitor when the capacitor is charged at a certain rate when the terminal voltage of the capacitor reaches a second reference potential higher than the first reference potential. a discharging circuit for discharging the voltage, a reference potential generation circuit for generating the first reference potential and the second reference potential, and a sawtooth wave voltage generated in the capacitor for matching the phase with the synchronization signal. , a means for superimposing a synchronizing signal on the first reference potential, and a means for amplifying the sawtooth wave voltage generated in the capacitor and causing a sawtooth wave current to flow through the deflection coil in addition to the deflection coil of the picture tube. The vertical deflection circuit includes at least a frequency-voltage conversion circuit and a voltage generating means for generating a voltage proportional to the period of the synchronizing signal, and a voltage generating means for generating a voltage proportional to the period of the synchronizing signal generated by the voltage generating means. means for changing the average value of the first reference potential according to the applied voltage, so that the phase of the sawtooth wave voltage generated in the capacitor always matches the synchronizing signal. It provides a deflection circuit.

(Example) Hereinafter, specific contents of the vertical deflection circuit of the present invention will be explained in detail with reference to the accompanying drawings. FIG. 1 is a block diagram of an embodiment of the vertical deflection circuit of the present invention.
The same drawing numerals as those used in FIG. 9 are used for each component corresponding to each component in the conventional vertical deflection circuit described with reference to the figures.

In FIG. 1, 31 is an input terminal for the synchronization signal Ps, 1 is a coupling capacitor, and 2 and 3 are bleeder resistors, which are the bleeder resistors 2, 3, and 3, respectively.
3 is connected between the operating power supply Vcc and ground, and the ground points A of the resistors 2 and 3 are connected to the inverting input terminal of the comparator 6, and also to the buffer amplifier 14, which will be described later. It is also connected to the output side and one contact of the electronic switch 10. The other contact of the electronic switch 10 described above is connected to the power supply Vcc via a resistor 8 (oscillation acceleration resistor 8).

Further, the non-inverting input terminal of the comparator 6 described above is connected to one contact of the electronic switch 9, and the non-inverting input terminal of the comparator 6 described above is connected to the non-inverting input terminal of the comparator 6.
A capacitor 4 (hereinafter simply referred to as capacitor 4) that generates a sawtooth wave voltage between terminals by charging and discharging, a constant power source 5, and a vertical deflection circuit 11.
is also connected. The other contact of the electronic switch 9 is connected to the power supply via the charging resistor 7.
Connected to Vcc. A vertical deflection coil 12 is connected to the output side of the vertical deflection circuit 11 .

In FIG. 1, 13 is a frequency-voltage conversion circuit, and this frequency-voltage conversion circuit 13 receives a synchronizing signal.
A synchronizing signal Ps is supplied from an input terminal 31 of Ps, and an output signal from the frequency-voltage conversion circuit 13 is given to a buffer amplifier 14.
The output signal from the buffer amplifier 14 is supplied to the connection point A between the bleeder resistors 2 and 3 as described above.

As can be readily understood by comparing the vertical deflection circuit of the present invention shown in FIG. 1 with the conventional vertical deflection circuit described with reference to FIG. Connection point A between bleeder resistors 2 and 3 in the vertical deflection circuit and synchronization signal Ps
The frequency-voltage conversion circuit 1 is connected between the input terminal 31 of the
However, in the vertical deflection circuit of the present invention, the connection point A between the bleeder resistors 2 and 3 is connected to the buffer amplifier 14.
and a frequency-voltage conversion circuit 13 and a buffer amplifier 14 connected between the input terminal 31 of the synchronization signal Ps and
By superimposing a voltage proportional to the period Ts of the synchronizing signal Ps generated in the cascade connection circuit with the voltage generated at the connection point A between the bleeder resistors 2 and 3, the synchronizing signal The average value of the reference voltage is changed according to the period of Ps, and the period of the synchronization signal Ps supplied to the input terminal 31 of the synchronization signal Ps of the vertical deflection circuit is changed over a considerable predetermined range. Also, the sawtooth wave voltage Vs generated by the vertical deflection circuit is automatically synchronized with the synchronization signal Ps.

That is, in the conventional vertical deflection circuit shown in FIG.
Whereas the reference potentials V1 and V2 of the reference potentials V1 and V2 were respectively set to predetermined specific voltages, in the vertical deflection circuit of the present invention shown in FIG. Of the second reference potentials V1 and V2, the first reference potential V1 is automatically selected in accordance with the cycle Ts of the synchronization signal Ps supplied to the input terminal 31 of the synchronization signal Ps of the vertical deflection circuit. I'm trying to change it. However, in both the vertical deflection circuit shown in FIG. 1 and the vertical deflection circuit shown in FIG.
There is no change in the fact that the charging/discharging operation of the capacitor 4 is controlled according to the comparison result between the reference potential of and the terminal voltage of the capacitor 4, and the sawtooth wave voltage Vs is generated. A general description of the operation of generating the sawtooth wave voltage Vs in the illustrated vertical deflection circuit of the present invention will be omitted.

Figure 2 shows the period of free-running oscillation in the vertical deflection circuit.
When Tf is approximately equal to the period Ts of the synchronization signal Ps supplied to the input terminal 31 of the synchronization signal Ps,
Similarly to the conventional vertical deflection circuit shown in FIG. 9, which was explained with reference to FIG.
FIG. 3 shows the conventional vertical deflection circuit shown in FIG. Running oscillation period
As explained with reference to FIGS. 12 and 13, when Tf is too long or too short compared to the period Ts of the synchronization signal Ps supplied to the input terminal 31 of the synchronization signal Ps, The period of the sawtooth wave voltage Vs output from the vertical deflection circuit is independent of the period Ts of the synchronization signal Ps supplied to the input terminal 31 of the synchronization signal Ps, and the period Tf of the free-running oscillation in the vertical deflection circuit. The period Tf of free-running oscillation in the vertical deflection circuit is determined by the synchronization signal
Synchronous signal Ps supplied to input terminal 31 of Ps
This is described for comparison with FIG. 4, which is shown to explain the operating principle of the vertical deflection circuit of the present invention, by taking as an example a case where the period is too long compared to the period Ts' (same as the case in FIG. 12). This is what we are doing.

FIGS. 5 and 7 are circuit diagrams showing different configuration examples of the frequency-voltage conversion circuit 13 and the buffer amplifier 14, respectively. In the frequency-voltage conversion circuit 13 and buffer amplifier 14 shown in FIG. 5, 15 is a coupling capacitor, 16 is a bias resistor, 17 is a switching transistor, 18 is a load resistor, and 1
9 is a charging/discharging capacitor, 20 is a smoothing resistor, 21
is a smoothing capacitor, 22 is an emitter follower stage transistor, 23 is an emitter resistor, 24 is a next stage input resistor, 25 is an inverting stage transistor, and 32 is a resistor.

Frequency-voltage conversion circuit 1 shown in FIG.
3, a synchronizing signal Ps is connected to the base of the switching transistor 17 via a coupling capacitor 15.
is supplied, the switching transistor 17 becomes conductive during the period of the synchronizing signal Ps,
The charge accumulated in the charge/discharge capacitor 19 connected between the collector and the ground is discharged by the conducting switching transistor 17, and the potential of the collector of the switching transistor 17, that is, the voltage at point B, is reduced. becomes almost zero.

When the synchronization signal Ps period has passed, the charging/discharging capacitor 19 is connected to the power supply Vcc via the resistor 18.
is charged according to a time constant determined by the resistor 18 and the charging/discharging capacitor 19, and the voltage at point B gradually rises as shown at a in FIG. The voltage at point B mentioned above is the following synchronization signal
When Ps is supplied to the frequency-voltage conversion circuit 13 and the switching transistor 17 becomes conductive, it is made approximately zero as described above.

Therefore, the potential of the collector of the switching transistor 17, that is, the voltage at point B, is the synchronization signal Ps input to the frequency-voltage conversion circuit 13.
It becomes a sawtooth wave voltage with the same repetition period as the repetition period Ts.

Switching transistor 1 as described above
The sawtooth wave voltage shown in a of FIG. 6 generated at the collector of 7 has the same repetition period as the repetition period Ts of the synchronizing signal Ps input to the frequency-voltage conversion circuit 13 as described above. Since the voltage is a sawtooth wave voltage, when the synchronizing signal Ps with the repetition period Ts shown in FIG. The sawtooth wave voltage generated in this case is as shown by the solid line in a of FIG. When the synchronizing signal Ps' is input, the sawtooth wave voltage generated at the collector of the switching transistor 17 becomes as shown by the dotted line in a of FIG.

Switching transistor 1 as described above
The sawtooth wave voltage generated at the collector of No. 7 is smoothed by a smoothing circuit constituted by a smoothing resistor 20 and a smoothing capacitor 21, so that the above-mentioned switch is applied to point C on the output side of the smoothing circuit. A DC voltage Vf corresponding to the average value of the sawtooth wave voltage generated at the collector of the switching transistor 17 is generated.

The DC voltage Vf generated at the point C mentioned above is a synchronization signal supplied to the frequency-voltage conversion circuit 13.
It has a voltage value that is inversely proportional to the repetition period of Ps.
Therefore, the buffer amplifier 14 in FIG. 5 is constructed so that it can invert the polarity of the voltage Vf appearing at the point C and output it.

That is, the buffer amplifier 14 in FIG.
an emitter follower stage formed by a transistor 22;
A voltage of the same polarity is generated at the emitter of the transistor 22 of the emitter follower stage, that is, a voltage of the same polarity at the point D. A voltage whose polarity is inverted from the voltage at point D appears on the collector side of transistor 25, and is supplied to point A.

In this way, the voltage generated by the circuit arrangement shown in FIG. 5 has a voltage value proportional to the repetition period of the synchronization signal Ps supplied to the frequency-voltage conversion circuit 13.

Next, in the frequency-voltage conversion circuit 13 and buffer amplifier 14 shown in FIG. 7, 26 is a monostable multivibrator, 27 is a smoothing resistor, 28 is a smoothing capacitor, 29 is an emitter fluoro stage transistor, and 30 is an emitter resistor. In the frequency-voltage conversion circuit 13 shown in FIG. 7, the monostable multivibrator 26 receives a synchronizing signal
An output pulse with a predetermined pulse width is generated every time Ps is supplied.

The pulse width of the output pulse from the monostable multivibrator 26 is set so that the pulse width of the output pulse from the monostable multivibrator 26 is shorter than the shortest period among the periods of the synchronization signal input to the vertical deflection circuit. A constant is set.

For the frequency-voltage conversion circuit 13 shown in FIG.
When a synchronizing signal Ps having a repetition period of the synchronizing signal Ps as shown in FIG.
Ps is triggered every time, and as shown in FIG. A pulse Pd with a pulse width Td is output at a repetition period of , and always has a constant pulse width Td.

Monostable multivibrator 2 as described above
The pulse Pd of pulse width Td generated at point E on the output side of
By being smoothed by the smoothing circuit configured by Moreover, a DC voltage Vf corresponding to the average value of the voltage of the pulse Pd always having a constant pulse width Td is generated.

The DC voltage Vf generated at the point F mentioned above is a synchronization signal supplied to the frequency-voltage conversion circuit 13.
It has a voltage value proportional to the repetition period Ts of Ps.
The buffer amplifier 14 in FIG. 7 amplifies the voltage Vf appearing at the point F using the transistor 29 in the emitter follower stage and supplies the amplified voltage to the point A.

In this way, the voltage generated by the circuit arrangement shown in FIG. 7 has a voltage value proportional to the repetition period of the synchronization signal Ps supplied to the frequency-voltage conversion circuit 13.

(Effects) As is clear from the detailed explanation above, the vertical deflection circuit of the present invention includes a capacitor that generates a sawtooth voltage between the terminals when charging and discharging, and a capacitor that generates a sawtooth voltage between the terminals of the capacitor. a charging circuit that rapidly charges the capacitor when the voltage of the capacitor reaches a first reference potential; and a charging circuit that rapidly charges the capacitor when the voltage of the capacitor reaches a second reference potential that is higher than the first reference potential. a discharge circuit that discharges the capacitor at a constant rate when the
A reference potential generation circuit that generates the first reference potential and the second reference potential described above, and the first reference potential described above for matching the phase of the sawtooth wave voltage generated in the capacitor with the synchronization signal. and a vertical deflection circuit that amplifies the sawtooth wave voltage generated in the capacitor and causes a sawtooth wave current to flow through the deflection coil in addition to the deflection coil of the picture tube. A voltage generating means configured to include a voltage conversion circuit and generating a voltage proportional to the period of the synchronizing signal, and a voltage proportional to the period of the synchronizing signal generated by the voltage generating means described above. Since the vertical deflection circuit is characterized in that the vertical deflection circuit is characterized in that it includes means for changing the average value of the reference potential of the capacitor, so that the phase of the sawtooth wave voltage generated in the capacitor always matches the synchronization signal, In the vertical deflection circuit, it is possible to automatically synchronize without adjustment even to a synchronization signal whose period changes over a wide range, and according to the present invention, the above-mentioned conventional problems can be satisfactorily solved. can.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram of one embodiment of the vertical deflection circuit of the present invention, FIGS. 2 to 4, FIGS. 6 and 8, and FIGS. 10 to 13 are waveform diagrams for explaining the operation. 5 and 7 are block diagrams of frequency-voltage conversion circuits, and FIG. 9 is a block diagram of a conventional vertical deflection circuit. 1... Coupling capacitor, 2, 3... Bleeder resistor, Vcc... Operating power supply, 6... Comparator, 14...
...Buffer amplifier, 9,10...Electronic switch,
8... Resistor 8 (oscillation acceleration resistor 8), 4... Capacitor that generates a sawtooth wave voltage between terminals when charging and discharging is performed, 7... Charging resistor, 11
... Vertical deflection circuit, 12 ... Vertical deflection coil, 1
3... Frequency voltage conversion circuit, 14... Buffer amplifier, V1, V2... First and second reference potentials, 1
5...Coupling capacitor, 16...Bias resistor, 17...Switching transistor, 18...
...Load resistance, 19...Charge/discharge capacitor, 20...
...Smoothing resistor, 21...Smoothing capacitor, 22...
... Emitter follower stage transistor, 23...
Emitter resistor, 24...Next stage input resistor, 25
...Inverting step-up transistor, 26... Monostable multivibrator, 27... Smoothing resistor, 28...
Smoothing capacitor, 29... Emitter follower stage transistor, 30... Emitter resistor, 31... Input terminal for synchronizing signal Ps, 32... Resistor.

Claims (1)

[Claims] 1. A capacitor that generates a sawtooth voltage between terminals when charging and discharging is performed, and a charging circuit that rapidly charges the capacitor when the voltage between the terminals of the capacitor reaches a first reference potential. and a discharge circuit that discharges the capacitor at a constant rate when the terminal voltage of the capacitor reaches a second reference potential higher than the first reference potential, and the first reference potential. A reference potential generation circuit that generates a potential and a second reference potential, and a synchronization signal superimposed on the first reference potential in order to match the phase of the sawtooth wave voltage generated in the capacitor with the synchronization signal. and a vertical deflection circuit configured to amplify the sawtooth wave voltage generated in the capacitor and cause a sawtooth wave current to flow through the deflection coil in addition to the deflection coil of the picture tube, comprising at least a frequency-voltage conversion circuit. voltage generation means for generating a voltage proportional to the period of the synchronization signal; and voltage generation means for generating a voltage proportional to the period of the synchronization signal generated by the voltage generation means; 1. A vertical deflection circuit, comprising means for changing a value so that the phase of a sawtooth wave voltage generated in a capacitor always matches a synchronizing signal.