JPH0428370B2 - - Google Patents

Description

Claim 1 Each cardiac cycle is a P wave, a Q wave, and an R wave.
In a heart rate sensing device responsive to a wide range of incoming ECG signals over the duration of a number of cardiac cycles, each wave group representing one heartbeat, including wave groups of wave, S wave and T wave, comprising: 1 When one wave group is detected, the slope of the R wave of the wave group is detected by differentiating the ECG signal and taking the absolute value of the differentiated signal to produce one first output signal per cardiac cycle. When the one wave group is detected, a second detection means detects the amplitude of the R wave of the wave group and provides a second output signal; output means for receiving an output signal and a second output signal of the detector to determine the total number of the first output signal and the second output signal received per unit time; coupled between a detection means and the output means, selectively selecting only one of the first detection means and the second detection means at any time based on the rate at which the first output signal is received; coupling means for coupling to the output means, the coupling means comparing the value of the first output signal with a certain threshold value, and determining whether the value of the first output signal is within the threshold value. comprising comparison means for coupling said first detection means to said output means when said value is exceeded, and for coupling said second detection means to said output means otherwise; A heart rate detection device, wherein the total number of the first output signal and the second output signal received during the pulse represents the heart rate.

TECHNICAL FIELD This invention relates to a heart rate detection system, and more particularly, to an improved heart rate detection system for use with an implantable defibrillator to defibrillate a patient's heart in the event of a life-threatening arrhythmia. Related to equipment.

BACKGROUND OF THE INVENTION In recent years, there has been considerable progress in the development of defibrillation techniques that provide medically effective treatment for a variety of cardiac conditions or arrhythmias. Early efforts led to the development of standby electronic defibrillators, which respond to detection of cardiac rhythm abnormalities by delivering sufficient energy through electrodes connected to the heart to depolarize the heart. This is done to restore normal heart rhythm. Such standby electronic defibrillators are disclosed, for example, in U.S. Pat.
No. 3614955 (subsequently reissued Patent No. 27757).

Previous efforts in this field have also led to the development of implantable electrodes for use in ventricular defibrillation (and other corrective techniques). Such techniques include (for example) providing an apex electrode on the inner or outer pericardial surface of the heart, as disclosed in U.S. Pat. No. 4,030,509 to Heilman et al. Alternatively, it acts on a base electrode in the form of a catheter within a blood vessel.
Such known electrode arrangements, as disclosed in the Heilman et al. patent, allow the use of individual pacing tips in combination with the base electrode or the apex electrode, or both.

Recent efforts have also developed techniques to monitor cardiac activity (to determine when defibrillation or cardioversion is required), which can be used to monitor cardiac activity when ventricular fibrillation occurs. A probability density function is used to determine. Such a technique using a probability density function is described in US Patent No. 1 by Langer et al.
No. 4184493 and No. 4202340.

According to this latter known technique, fibrillation of the heart is indicated when the probability density function is satisfied. However, recent experiments have shown that when some abnormal ECG patterns occur, known probability density function detection devices can be "triggered" by actual ventricular fibrillation if not properly calibrated. Not only will you be
It has been found that certain types of high-frequency and low-frequency ventricular tachycardias can also be "triggered", especially when the ventricular status is abnormal. It is permissible to be triggered in this way when a high frequency tachycardia occurs. This is because tachycardia of such high frequency that the blood pumping action is no longer sufficient is often life-threatening. However, the problem is that it is triggered during low-frequency tachycardia that is not life-threatening. Therefore, there is a need for an apparatus and method for differentiating between ventricular fibrillation and high frequency tachycardia from low frequency tachycardia.

One solution to the above need was introduced in 1982.
It is disclosed in British Patent No. 2083363A of 24 May. In that patent, the differentiated
A probability density function circuit responsive to the ECG signal is used in conjunction with the heart rate circuit such that the probability density function circuit activates the defibrillation pulse generator only when the probability density function circuit is enabled by the heart rate circuit. It is being done. The probability density function circuit is activated when the heart rate becomes greater than a predetermined value that is considered a dangerous tachycardia.

The success of this system depends primarily on the reliability and accuracy of the heart rate detection circuit. Heart rate detection devices themselves are well known.
Such heart rate detection devices are typically designed to respond to input ECG waveforms of a predetermined type. For example, it is known to detect heart rate by using a zero-crossing detector. In such a detector, the zero crossing points of the ECG waveform represent periodic events in the cardiac cycle. However, when the ECG waveform is steep, e.g. when the rate of change of the R-wave voltage is rapid and resembles a voltage spike, the accuracy of detecting zero crossings using such a system suffers. .
Steep R-wave group - with its Q and S divisions -
This results in a large number of counts per heart cycle, making heart rate readings artificially high, and in some cases severe.

It is also known in the art to provide heart rate sensing devices that are responsive to ECG signals that have steep or "spike-like" slopes. Some such detection devices are responsive to ECG signals and provide outputs responsive to such steep signals. This output is provided by a slew rate detector that compares the slope or slew rate to a slew rate threshold and forms an output signal representing the number of high slew rate signals detected. do. An inherent problem with such systems is detecting heart rate when the ECG signal is sinusoidal rather than spike-like. In such a case, the slew rate characteristic, ie, the rate of change of the ECG voltage over time, is small. This detector will therefore not pick up such a signal and will detect an inaccurate low heart rate.

In very sick patients, it is not uncommon for ECG waveforms to change over time.
The ECG can present itself as a spike-like waveform at certain times and then become more sinusoidal, or vice versa. Both types of heart rate detection devices mentioned above are
It is not flexible enough to respond effectively to ECG waveforms.

It is therefore clear that known heart rate detection devices do not provide the flexibility needed when monitoring ECG signals that have the characteristics of both spiky and more sinusoidal ECG waveforms. be. Known detection devices can be designed to work very effectively with one or the other of these waveforms, but not with both. Therefore, there is a need to provide a flexible, accurate, and reliable heart rate detection device that operates over a wide range of detected ECG waveforms.

According to the present invention, a heart rate detection device is provided that very accurately measures heart rate for various monitored ECG signal waveforms. Such heart rate detection devices are particularly used in implantable automatic defibrillation systems in which the heart rate detection device is used in conjunction with probability density function circuits, such combinations being described in the patent application of Langer et al. is also disclosed. It should be noted, however, that the heart rate detection device of the present invention also has significant utility in cardiac pacing systems and other environments where heart rate must be measured reliably, effectively and accurately.

The heart rate detection device of the present invention is responsive to an input ECG signal having a series of waveforms, each waveform group including P waves, Q waves, R waves, S waves, and T waves as defined in the art. include. The heart rate detection device includes two mutually exclusive detection circuits that respond to input ECG waves with different characteristics. These detection circuits are connected to an output circuit. Based on the characteristics of the input ECG wave,
The coupling circuit automatically and selectively connects one of the two detection circuits to the output circuit so that an accurate count of heart rate is provided.

Specifically, two mutually exclusive detection circuits of the present invention include a high slew rate detector and an amplitude threshold detector. incoming ECG
When the wave is a high slew rate spike wave, a high slew rate detector is connected to the output circuit. The incoming ECG wave has a small slope.
When the ECG signal is a sinusoidal ECG signal,
A threshold amplitude detector is connected to the output circuit.

In particular, if the slew rate of the incoming ECG wave is higher than a predetermined level, and such "high"
The slew rate detection circuit provides an accurate measurement of heart rate when the slew rate signal occurs at a predetermined frequency for a predetermined period of time, as described below. However, the incoming ECG wave
If the rate is below a predetermined level and such "low" slew rate signals occur at a predetermined rate, the amplitude threshold detection circuit provides an accurate measurement of heart rate.

In a preferred embodiment of the invention, input means are provided for receiving an ECG signal. A slew rate output circuit is connected to this input means to output an ECG whose slew rate is greater than a predetermined threshold.
Detects waveforms and provides an output signal for each waveform detected. An amplitude threshold detection circuit is also connected to the input means, and this circuit detects an ECG waveform having a predetermined amplitude and provides an output signal each time each waveform is detected. An output circuit is provided to receive the two detection output signals. The coupling circuit selectively connects only one or the other of the detection circuits to the output circuit. A high slew rate detection circuit is connected to the output circuit when a predetermined number of high slew rate signals are produced therefrom at a substantially constant frequency over a first predetermined period of time. When such a condition occurs, the high slew rate detector remains connected to the output circuit as long as the high slew rate signal occurs within at least the second predetermined time period. At other times, the output circuit is connected to an amplitude threshold detector.

It is an object of the present invention to provide a heart rate detection device, in particular a heart rate detection device that is accurate, reliable and flexible for a wide range of detected ECG waveforms.

Yet another object of the present invention is to provide a heart rate sensing device that can be implanted within the body for use with implantable electronic devices such as defibrillators or pacers.

Yet another object of the invention is a heart rate detection device particularly suitable for use with an implantable defibrillation circuit using probability density function circuits, which detects the heart rate only during fibrillation or during high frequency ventricular tachycardia. It is an object of the present invention to provide a heart rate detection device that enables a probability density function circuit to operate such that a defibrillation shock occurs.

In particular, it is an object of the present invention to
It is an object of the present invention to provide a heart rate detection device that is responsive to signals and to provide a means to reliably and accurately measure heart rate regardless of which type of ECG waveform is present.

Yet another object of the present invention is to provide a high slew rate detector and an amplitude threshold detector.
It is an object of the present invention to provide a heart rate detection circuit having means for selectively and automatically switching between these two detection circuits based on the characteristics of the ECG input.

Yet another object of the invention is to provide a heart rate detection circuit including an output circuit for providing instantaneous heart rate readings and comparing this instantaneous heart rate reading with a predetermined or programmed heart rate. It is to provide.

These and other objects of the invention will be apparent from the following description:
A clearer understanding may be obtained by reference to the claims and accompanying drawings.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the heart rate detection device of the present invention installed in a defibrillation circuit, and FIG. 2 is a block diagram of the double duty delay circuit shown in FIG. 1.

BEST MODE FOR CARRYING OUT THE INVENTION The heart rate detection device 2 of the present invention has an amplified input.
Responsive to the ECG waveform, the detection device includes a slew rate detector 4 and an amplitude threshold detector 6, each detector connected to an input circuit 8 for forming an amplified ECG waveform. It is connected. Depending on the characteristics of the ECG waveform, one or the other of these detectors 4 and 6 is connected via a coupling circuit 10 to a digital heart rate comparison output circuit 12. The comparison output circuit 12 processes the total number of signals received from the slew rate detector 4 and the amplitude threshold detector 6 (the total number of signals represents the heart rate) and determines whether the heart rate has increased over a predetermined period of time. A detection output signal is provided (on line 14) above a predetermined or preprogrammed heart rate.

The heart rate detection device 2 can be used in a wide range of applications such as implantable defibrillators or pacers and external monitoring devices. A heart rate detection device is shown in the defibrillation circuit. In particular, the probability density function (PDF)
A circuit 16 is provided, the input of which is responsive to the amplified and differentiated ECG signal. logic circuit 18
connects the output of the PDF circuit to the output of the heart rate sensing device such that the PDF circuit 16 is connected to the defibrillation pulse generator (not shown) only when a detected output signal indicative of high frequency tachycardia occurs. interconnect. The details of the circuit will be explained below.

ECG input terminal 20 is connected to a suitable cardiac electrode (not shown) via an interface device (not shown) to receive an ECG input signal.
The cardiac electrodes include a superior vena cava electrode (base electrode) and a pointed cup electrode (patch electrode) that are associated with the patient's heart. Such electrodes are shown schematically in the Langer et al. patent application, which is incorporated herein by reference.

The incoming ECG signal includes a series of waves representative of heartbeats, each wave including a P wave, a Q wave, an R wave, an S wave, and a T wave, as is known in the art. Each wave group defines the term cardiac cycle as used herein.

Input terminal 20 is connected to a conventional ECG amplifier 22 having an automatic gain control (AGC) circuit 24 . In this way, input signals with different amplifications can be processed by the entire circuit, as is well known.

Connected to the ECG amplifier 22 are two detection circuits 4 and 6 of the invention. The slew rate detector 4 comprises a differential and absolute value circuit 26 which extracts the absolute value of the first derivative of the amplified input ECG signal. This absolute value of the first derivative is defined as the slew rate, which is the rate of instantaneous voltage change per unit time. In the present invention, this slew rate can be conveniently measured in microvolts per millisecond. Differential/absolute value circuit 26 is of a general type and is well known to those skilled in the art.

The slew rate value from the differential-magnitude circuit 26 is provided as an input to a conventional threshold comparator 28. Here, the slew rate is compared to a predetermined slew rate threshold value. When the slew rate is greater than this slew rate threshold, a slew rate output signal is provided to the comparator output line 30. The slew rate threshold is predetermined prior to unit implantation and is determined by comparator 2.
A variable resistor 32 connected to the negative input terminal 34 of 8
is set by adjusting the (Also note that the slew rate can be set or programmed externally by telemetry or other suitable techniques.) The slew rate threshold is set based on the ECG characteristics of a particular patient. , typically must be set to provide a slew rate output signal only for relatively high slew rates, ie, slew rates resulting from relatively spikey or high slope ECG signals.

The slew rate output signal is sent via line 30 to a variable refractory time monostable multivibrator 36. As is well known, this monostable multivibrator 36 is
Provide uniform output pulses on line 38. This output pulse is here either wave detection or through detection.
Defined as rate detection output signal or pulse.

For proper operation of the device, it is desirable to provide one wave detector output signal during a cardiac cycle so that the wave detector output signal adequately represents the heart rate. As mentioned above, each cardiac cycle includes the following waves: P, Q, R, S, and T waves. Generally, R is high enough to provide a slew rate output signal from comparator 28 to monostable multivibrator 36.
It's just the wave slew rate. However, for some patients, one of the other waveforms in the wave group,
In particular, P waves or T waves may also have a high slew rate that exceeds the slew rate threshold value set by variable resistor 32. Therefore, more than one slew rate output signal may be provided as input to a monostable multivibrator per heart cycle, allowing multiple wave detection output signals to be applied to the line for only one heartbeat. It will be sent to 38th.

To avoid the potential problems described above, the refractory time of monostable multivibrator 36 is adjusted via input terminal 40 so that monostable multivibrator 36 is triggered by the slew rate output signal from comparator 28. The multivibrator is prevented from further triggering by subsequent slew rate output signals occurring within a predetermined refractory time. The refractory time is set such that multivibrator 36 is triggered by only one slew rate output signal within one wave group or cardiac cycle. Once the multivibrator is triggered, the multivibrator trigger point is inhibited for a typical 100-200 millisecond refractory time. This time can be set based on the patient's normal heart rate. If the patient's heart rate is relatively low, the refractory time must be set higher than for a patient with a high heart rate. Similarly, if the patient's heart rate is high, set the refractory time low and
Ensures that each slew rate output signal from slew rate threshold comparator 28 is counted.

Generally, the refractory time is preset for a particular patient prior to implantation. However,
An automatic variable refractory time adjustment mechanism can also be implanted to change the refractory time in response to changes in heart rate.

The monostable multivibrator 36 of the present invention is a conventional circuit whose design is well known to those skilled in the art. Multivibrator 36 provides a uniform pulse output (wave detection output signal or pulse) on line 38. The width of this output pulse must not be so wide that monostable multivibrator 36 does not reset in time to receipt of a slew rate output signal from comparator 28 representing the next heartbeat. Similarly, the width of this output pulse must not be so narrow that the multivibrator will be retriggered upon receipt of the next slew rate output signal in the same wave group.

The wave detection output signal from monostable multivibrator 36 is provided to monostable multivibrator output line 38, which is connected to AND gate 42 of coupling circuit 10, which will be described below.

The second detection circuit of the present invention is the amplitude threshold detector 6. This threshold detector 6 is equipped with a general high gain amplifier 44,
One input 46 is grounded and the other input 48 is passed through a low pass filter 47.
Connected to ECG amplifier. Low-pass filter 47 removes ECG waveforms with "spike-like" characteristics and passes only more sinusoidal ECG waveforms.
Amplifier 44 is responsive to an amplified ECG signal in which the R-wave is greater than a predetermined value. When this amplified ECG signal is greater than a threshold - which is arbitrarily chosen as the ground level,
Amplifier 44 provides a zero crossing output signal, which is connected to AND gate 50 of combination circuit 10. Therefore, the threshold detector 6, with the negative input of the amplifier 44 being grounded, acts as a zero crossing detector.

The coupling circuit 10 will be explained below. The coupling circuit 10 here includes AND gates 42 and 5
0, OR gates 52 and 54, a double duty delay circuit 56, and inverters 58 and 60. These circuit elements are interconnected such that the output of the slew rate detection circuit 4 and the output of the amplitude threshold or zero crossing detector 6 are connected to a digital heart rate comparison output circuit 12. AND gate 42 receives the wave detection output signal via line 38. The output line 62 of AND gate 42 is connected to the input of OR gate 54. Similarly, the output of amplitude threshold or zero crossing detector 6 is connected via line 64 to the input of AND gate 50. Output line 6 of AND gate 50
6 is connected to the OR gate 54. As discussed below, only one of the AND gates 42 and 50 is enabled at a given time, so the OR gate 54 crosses zero based on which of the AND gates 42 and 50 is enabled. Either the output signal (via line 66) or the wave detection output signal (via line 62) is received. The output of OR gate 54 is sent via line 68 to digital heart rate comparison output circuit 12. The signal from the output of OR gate 54 represents the detected heart rate.

AND gate 42 has three inputs 70, 72, 7
It has 4. Input 72 is connected to output line 38 from monostable multivibrator 36 and receives a wave or slew rate detection output signal. Input 70 of AND gate 42 is connected to slew rate detector inhibit line 76. If, under certain conditions, it is desired to monitor the ECG signal using only zero-crossing detector 6, a zero input is provided to AND gate 42 via line 76 to disable AND gate 42. be made into This inhibition of the slew rate detector is determined based on the particular patient's ECG waveform. When the operation of the slew rate detection circuit 4 is to be maintained, the input terminal 70 of the AND gate 42 is set to a high level state, that is, a "1" state. A third input terminal 74 of AND gate 42 is connected to double duty delay circuit 56 via inverter 60 .

The double duty delay circuit 56 has its output 8
0 is normally designed to be a high level state, ie, a "1" state. This "1" state is inverted by the inverter 60, and the terminal 7 of the AND gate
4 is placed in a low or "0" state, and AND gate 42 is disabled. The output of delay circuit 56 is also connected to OR gate 52 and its output line 78 is connected to AND gate 50. When double duty delay output 80 is in a high or "1" state, a "1" signal is transferred via OR gate 52 and line 78 to input terminal 82 of AND gate 50, thereby enabling AND gate 50. , the zero-crossing output signal from zero-crossing detector 6 is passed to OR gate 54 and to digital heart rate comparator 12. On the other hand, when the output 80 of the double duty delay circuit is in a low level state, that is, in a "0" state, the AND gate 4
The third terminal 74 of AND gate 50 is enabled and terminal 82 of AND gate 50 is disabled. Therefore, the wave detection output signal or slew rate detection output signal from the monostable multivibrator 36 is connected to the OR gate 54 via the AND gate 42.
It is then sent to a digital heart rate comparison output circuit 12. Therefore, the double duty delay circuit 5
6 enables one of AND gates 42 and 50 such that either zero crossing detector 6 or slew rate detector 4 is connected to digital heart rate comparison output circuit 12; should be obvious.

Double duty delay circuit 56 is shown in detail in FIG. This circuit includes an input 84 which is connected to the output line 38 of the monostable multivibrator 36 and is therefore a wave detection circuit or through-
Receives wave detection output pulses from rate detection circuit 4. These wave detection output pulses are typically provided to input 202 of digital counter 200. A second input 204 of this counter 200 receives a clock pulse, such as a 32 Hz clock signal. Counter 200 counts these clock pulses and provides a high level or "1" signal on counter output line 206 when a predetermined number of clock pulses have been counted consecutively. For example, when the clock pulse applied to the input 204 is counted for a predetermined period of time, eg, 2 seconds, the output of the counter 200 becomes a high level state, ie, a "1" state. However, the counter is 200.
is reset upon receiving each wave detection output pulse at input 202. When counter 200 is reset, its output goes to a low level or "0" state. Therefore, the wave detector output signal from the slew rate detection circuit 4 is
As long as it occurs within seconds, the output of counter 200 will be "0", and if no wave detector output signal arrives during such a two second interval, the output of counter 200 will be "1".

The output line 206 of the counter is connected to the input 20 of a conventional set-reset flip-flop 210.
Connected to 8. This flip-flop 210
has a second input 212 and an output 80.
Output 80 is connected to inverter 60 and OR gate 52 as described with respect to FIG.

Flip-flop 210 has the following characteristics. When a high or "1" signal is applied to input 208, output 80 is in a high or "1" state. As will be described later, when a high level signal, ie "1", is applied to input 212,
Output 80 is in a low or "0" state.
Flip-flop 210 has inputs 208 and 21
The state is controlled only by applying a "1" signal to one of the two.

Output line 80 is further connected to input 214 of AND gate 216. The other input 218 of AND gate 216 is connected to input 84 to receive pulses from slew rate detection circuit 4. Thus, when output 80 is in the "1" state, AND gate 216 is enabled to pass the wave detection output pulse from slew rate detection circuit 4. These wave detection output pulses are sent to RC circuit 220 by AND gate 216.

RC circuit 220 includes a capacitor 222 and a resistor 224 connected in parallel. RC circuit 2
The output of 20 is connected to an inverter 226. The output of inverter 226 is connected to a reset terminal 228 of a counter 230, which is substantially similar in operation to counter 200 described above, and whose second input 232 is connected to a predetermined clock signal source, e.g.
Connected to a 32Hz clock signal source.

The wave detection output pulse from the slew rate detection circuit 4 passes through the AND gate 216 to the RC circuit 22.
When sent to 0, capacitor 222 is immediately charged and begins to gradually decay exponentially as is well known. The decay time depends on the RC characteristics. In the case shown here, the RC characteristic causes the capacitor 22 to rise to a voltage level greater than the threshold required for the inverter 226 to change its state when receiving the wave detection output pulse.
2 is such that it is charged virtually immediately. The capacitor then gradually decays until the voltage drops below the threshold. If the second wave detection output pulse is received by the RC circuit before the voltage falls below the threshold, inverter 226 will remain in its altered state until the voltage falls below the threshold. Therefore, if a predetermined number of wave detection output pulses are received by RC circuit 220 and these output signals are separated for a predetermined time, the threshold voltage level at which inverter 226 is activated will be exceeded. It is clear that this will continue. this
The RC characteristic is correlated with a predetermined time period of the counter 230, as described below.

Now assume that the output 80 is in the "1" state. (As discussed with respect to FIG. 1, when output 80 is in the "1" state, zero crossing detector 6 is connected to digital heart rate comparator 12.) - Can pass wave detection output pulses received from rate detection circuit 4; If no wave detection output pulses are received (indicating that the input ECG is of a low slew rate type), no voltage is applied to inverter 226. Therefore, the input of inverter 226 is at a low level (below the threshold), ie, "0". This "0" signal is inverted and a "1" signal is given to the output of the inverter 226, so that the counter 230
A "1" signal is applied to the reset terminal 228 of the. Therefore, the output of the counter 230 is "0", which is the input 21 of the flip-flop 210.
given to 2. A "0" signal applied to input 212 does not change the state of the flip-flop, as described above.

Now, here, a signal with a high slew rate is detected by the slew rate detector, and the wave detection output pulse is sent to the multivibrator 36 (FIG. 1).
Suppose that input 84 is provided by . This signal is passed to the RC circuit 222 by the AND gate 216.
be passed to. (This signal is also sent to the reset input 202 of the counter 200, which then provides a "0" signal via line 206 to the input terminal 208 of the flip-flop.
As mentioned above, even when a ``0'' signal is applied to input 208, the state of flip-flop 210 does not change and output 80 remains in the ``1'' state. )
Capacitor 222 is immediately charged to a level above the inverter's threshold voltage level, and inverter 226 now "sees" a "1" input. This "1" input to inverter 226 is inverted to provide a "0" output, which is sent to the reset terminal 228 of counter 230. Therefore, counter 230 is enabled and begins counting the 32 Hz signal applied to the other input 232.

Now, if the wave detection output signal sent to terminal 84 is abnormal, and the next output signal is applied within the time (approximately 2 seconds) before capacitor 222 decays below the threshold voltage level. Let's assume that it doesn't happen. That is, before the capacitor 222 attenuates to a level lower than the threshold level, the RC circuit 22 passes through the AND gate 216.
Suppose that 0 is not given the next pulse. Under such conditions, the input voltage to inverter 226 falls below the threshold, ie, to the "0" state, and the output of inverter 226 returns to the "1" state, thus resetting the counter ( at terminal 228). This reset operation occurs before counter 230 has counted its predetermined number of clock pulses, ie, before a predetermined time interval (2 seconds). Therefore,
The output of counter 230 does not change its state to "1", counter 230 remains in the "0" state and flip-flop 210 is not reset. Flip-flop 210 remains in the "1" state.

Now consider the situation in which the second pulse from slew rate detection circuit 4 is received by AND gate 216 before capacitor 222 decays below the threshold voltage level. This second pulse is applied to capacitor 2
22 to its fully charged state, thus
The capacitor maintains a voltage above the inverter threshold level for a time greater than the predetermined time interval of counter 230, thereby keeping counter 230 in its enabled state and causing the output of counter 230 to switch to the "1" state. The count is a sufficient number of clock pulses. As previously discussed, this "1" signal applied from counter 230 to input 212 of flip-flop 210 changes flip-flop 210 to a "0" state. AND gate 216 is now disabled. Similarly, since output 80 is a "0", slew rate detection circuit 4 is connected to digital heart rate comparator 12 (FIG. 1). Yet another high slew rate signal is applied to terminal 8 at least every 2 seconds.
4, the output 80 remains in the "0" state.

From the above explanation, the input voltage to the inverter 226 is thresholded (by disconnecting the zero crossing detector 6 from the digital heart rate comparator 12 and connecting the slew rate detection circuit 4 to this comparator 12). In order to keep the counter 230 above the level and thus keep the counter 230 in the high level state, the through
It is clear that the wave detection output pulses from the rate detection circuit 4 must occur at or above a certain rate and must occur at substantially equal intervals. For example, assume that the predetermined time of counter 230 is 2 seconds, and further assume that when two consecutive wave detection output pulses are received,
Let us assume that it is desired to "switch" to rate detection circuit 4. The first wave detection output pulse is RC
Once received by circuit 220, the capacitor substantially instantaneously charges above the threshold voltage of inverter 226 and then begins to decay. If a second consecutive wave detection output pulse occurs 1/2 second later, and no further pulses are received within a 2 second span, then the counter 230
The voltage to inverter 226 drops below the threshold level before the second period is complete. The counter 230 indicates that the voltage of the capacitor is the inverter 22
It is reset at the "instant" when the voltage drops below the threshold of 6, and therefore does not change from the "0" state and maintains the output 80 in the "1" state, i.e., the "switching" to the slew rate detection circuit 4 is Does not occur.

Similarly, if the second wave detection output pulse occurs 1.5 seconds after the first output pulse, the voltage to inverter 226 will decay below the threshold before receiving the second pulse. In this case too,
Even though counter 230 is enabled by the first pulse, at the "instant" the voltage on the capacitor falls below the threshold of inverter 226 (i.e., counter 230 falls below the threshold during a two-second period). ), the counter 230 is reset and therefore the counter 23
0 does not change from the "0" state.

Referring to FIG. 1, the double duty delay circuit 56 operates as follows. First of all, the zero crossing detector 6 is connected to the digital heart rate comparison output circuit 1.
2. The output 80 of the double duty delay circuit is in the "1" state. A wave detection output signal from slew rate detection circuit 4 is now received. Double duty delay circuit 56 counts the number of relatively constant frequency wave detection output signal pulses over a first predetermined period of time. If the number of constant frequency or substantially uniformly spaced pulses exceeds a predetermined number within a first predetermined time period, the double duty delay output line 80
It is shifted from its normal high level state to a low level or "0" state. It is maintained in this "0" state during at least a second predetermined period of time. The second predetermined time is the first
The length may be the same as the predetermined time period. If the next wave detection output pulse occurs within the second predetermined time period, the output 80 of the delay circuit remains in the "0" state. However, if the time between successive wave detection output signal pulses increases, that is, if no wave detection output signal pulse occurs within the second predetermined time period, the output 80 of the delay circuit 56 will change from the "0" state. It switches to a high level state, ie, a "1" state.

Therefore, as long as a predetermined number and frequency of high slew rate output pulses are received by delay circuit 56, zero crossing detector 6 will be disconnected from digital heart rate comparison output circuit 12 and slew rate detector 4 will be disconnected from digital heart rate comparison output circuit 12. is connected to this comparison output circuit 12. However, high through-
If the number of rate output signals falls below a predetermined level within a predetermined period of time, a coupling circuit 10 connects the zero crossing detector 6 to a digital heart rate comparison output circuit 12. This zero crossing detector 6 remains connected to the output circuit 12 until the double duty delay circuit 56 changes state again as described above.

Accordingly, the combination circuit 10 of the present invention uses the slew rate detector 4 to monitor the ECG signal when the ECG signal is "spiky" or has a high slew rate waveform. On the other hand, if the slew rate of the incoming ECG signal is sinusoidal, the coupling circuit 10 couples the zero crossing detector 6 to the output circuit 12. This alternating switching between detectors 4 and 6 ensures reliable and accurate counting of heart beats.

It is clear that some heartbeat signals may be missing. For example, multivibrator 3
The first wave detection output signal provided from 6 to double duty delay circuit 56 may not be passed to OR gate 54 by AND gate 42.
This is because AND gate 42 is not enabled until the first predetermined time period has expired.
Generally, the first predetermined time period is set between 1 and 5 seconds, and preferably between 2 and 5 seconds. (Such high slew rate signals may not be counted as slews, but
If these signals pass through the low pass filter 47, they can be counted by the zero crossing detector 6. ) Similarly, if AND gate 42 is enabled after a first predetermined time and no further high slew rate signals are received, zero crossing detector
is disabled for a predetermined period of time, causing the low slew rate heartbeat signal to be dropped. However, as a practical matter, the number of heartbeats missed by the heart rate detection circuit 2 is relatively small. This is because the double duty delay circuit 56 is designed such that the first and second predetermined times are not so long that a missed heartbeat would have a significant effect. Furthermore, as a practical matter, it is unlikely that a patient's ECG waveform will change so rapidly between high and low slew rates that a significant number of heartbeat signals are missing.

The output circuit 12 is a digital heart rate comparator 86
It is equipped with The digital heart rate comparator is of general design (such as including a digital magnitude comparator, latch and counter) and its input 88 is connected to the output line 68 of the OR gate 54 from the combination circuit 10. has been done. The signal appearing at input 88 represents the beat rate from zero crossing detector 6 or slew rate detector 4. Digital heart rate comparator 86 includes a programmed heart rate input terminal 90 for loading a predetermined or preprogrammed heart rate into the digital heart rate comparator. A digital heart rate comparator 86 receives the heartbeat signal and determines the actual heart rate on a beat-by-beat basis. This heart rate is compared to the programmed heart rate and when the heart rate is greater than the programmed heart rate, a comparator output signal is provided on the comparator output line 92. Delay circuit 9 which is a well-known integrator
3 integrates the output signal of the comparator over a predetermined time, and provides a detected output signal to line 14 when the number of comparator output heart rate signals exceeds a predetermined number within a predetermined time. Generally, delay circuit 93 performs a security function to prevent spurious signals from initiating activation of the defibrillation pulse generator. Delay circuit 93
provides an output signal if two comparator output pulses are received within a 4 second interval.

The digital heart rate comparator 86 also includes a readout terminal 94 for reading out the actual heart rate. Although this actual heart rate readout is not required for defibrillator or pacer operation, actual heart rate may be desired. If the device is implanted in a human body, this readout may be performed by telemetry or similar means.

When heart rate detection device 2 is used in a defibrillation circuit as shown in FIG. 1, the detection output signal appearing on line 14 is applied to the inputs of two AND gates 96 and 98. AND gate 96 receives the output from probability density function circuit 16 as the other input. The output of AND gate 96 is connected to OR gate 100, which in turn is connected to a defibrillation pulse generator (not shown) to begin delivering a defibrillation shock. Therefore, when the characteristics of the probability density function circuit are satisfied and the heart rate output exceeds a predetermined value, AND gate 96 is enabled and the probability density function circuit is connected to the defibrillation pulse generator.

Under certain conditions, defibrillation shocks are desired based solely on heart rate abnormalities. Under these conditions, a high level or "1" input is sent to terminal 102 of AND gate 98, allowing the defibrillation pulse generator to be activated solely by output 14 of the heart rate detection circuit. Do it like this. If such functionality is not required, terminal 1 of AND gate 98
A prohibited input, that is, a "0" input is sent to 02.

While the preferred embodiments and configurations of the invention have been illustrated and described, it will be clearly apparent that various changes may be made in detail and configuration without departing from the spirit and scope of the invention.