JPH0429096B2 - - Google Patents

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems (Fig. 1) Working Examples (Fig. 2) Effects of the Invention [Summary] The present invention provides a processor that reads an interrupt vector from lower bits of a data bus in response to an interrupt request signal.
When there is a cause for an interrupt to the CPU, the interrupt request section outputs it to the upper bits of the data bus, encodes this, and generates an interrupt vector on the lower bits of the data bus.

[Industrial application field]

The present invention relates to an interrupt vector generation system, and particularly to one in which there is no need to increase the number of signal lines to an interrupt vector generation circuit even if there are a large number of interrupt cause generation units.

[Conventional technology]

When an interrupt occurs in a data processing device, the processor CPU determines the cause of the interrupt.
Since the interrupt is detected by hardware and processing such as a jump is performed in another routine, the cause of the interrupt may be captured by an identification signal from the data bus. Therefore, it is necessary to place an identification signal for each cause of interrupt on the data bus using an interrupt vector.

[Problem that the invention seeks to solve]

Conventionally, interrupt vector generation notification is performed in local mode from the source of the interrupt cause, so the circuit that generates the interrupt vector, that is, the interrupt vector generation circuit, and the interrupt cause generation circuit are printed separately. If the interrupt cause exists on the board, a signal for each interrupt cause is output onto the bus and input from the interrupt cause generating circuit to the interrupt vector generating circuit.

This conventional system requires a signal line on the bus for each cause of interrupt, and therefore has problems such as an increase in the number of connector pins on the printed circuit board.

SUMMARY OF THE INVENTION An object of the present invention is to provide an interrupt vector generation method that improves the above-mentioned problems.

[Means for solving problems]

In order to achieve this objective, the present invention provides the first
As shown in the figure, it is possible to determine which of the plurality of interrupt cause generation circuits 2... which generates interrupts to the CPU 1 and the plurality of interrupt cause generation circuits 2... generates the interrupt.
In a system equipped with an interrupt vector generation circuit 3 that sends signals to the CPU 1, an interrupt request signal line S ₁ and an interrupt vector read cycle signal line S 2 are connected to the CPU 1, and an open collector signal line S ₂ is connected to the interrupt cause generation circuit 2. A signal output section 2-1 such as the above, and a gate 2-2 such as a tri-state gate are provided, and the interrupt vector generation circuit 3 is provided with an encoder 3-1 and a gate 3-2.

[Effect]

Now, when an interrupt cause occurs in the interrupt cause generation circuit 2 among the plurality of interrupt cause generation circuits, a positive logic signal is output to the signal output section 2-1 and the gate 2-2. -1 outputs a low level signal to the interrupt request signal line _S1 . CPU1 detects this low-level interrupt request signal on _S1 , which was pulled up to +5V, recognizes that an interrupt request has occurred, and outputs a low-level signal to the interrupt vector read cycle signal line _S2 . do. This allows gate 2
-2 is turned on, and the interrupt cause generation circuit 2 outputs a signal to the upper bit of the data bus. in this case,
If the data bus of the CPU 1 is, for example, 16 bits, the upper 8 bits of the data bus are assigned, for example, 1 bit each to the 8 interrupt cause generation circuits 2..., so the encoder 3-1 is able to control the upper bits of this data bus. By decoding the signal position, the interrupt cause generation circuit 2 determines that an interrupt cause has occurred and generates a signal indicating this. When these occur simultaneously, the priority order is determined, so the encoder 3-1 outputs accordingly. This discrimination signal is
When CPU 1 outputs an interrupt vector read request signal to _S1 , gate 3-2 turns on and the signal is sent to the lower 8 bits of the data bus. I can recognize that it has occurred.

〔Example〕

An embodiment of the present invention will be described based on FIG.

In FIG. 2, 10 is a CPU, 11 is an encoder, 12 is a decoder, 13 is an interrupt vector generation circuit, 14 is a NAND circuit, 15 is an OR circuit, 21-
1, 21-2... are signal output parts such as inverters,
22-1, 22-2, . . . are gates such as tri-state gates.

The CPU 10 corresponds to the CPU 1 in FIG. 1, and performs various processing when an interrupt cause occurs. For example, it detects an interrupt level, and outputs an address signal corresponding to the detected level. It performs operations such as outputting data, decoding the lower 8 bits of the data bus, and recognizing the cause of the interrupt.

The encoder 11 discriminates between level 1 and level 7 interrupts and sends an output according to the level to the CPU 10. When the interrupt request *iRQ1 is input, the encoder 11 outputs the 3-bit output signal *iPL0 to *iPL2. It outputs a level 1 signal (001 inverted signal 110 due to negative logic), and similarly outputs a level 7 signal when *iRQ7 is input.

The decoder 12 receives a 3-bit level indication signal on the address bus AB output from the CPU 10.
It decodes A01 to A03 and selectively outputs signals to terminals 0 to 8, and the CPU 10 uses the address bus.
When outputting data indicating level 1 on AB,
Decipher this and output a signal to terminal 1, gate 2
Turn on 2-1, 22-2...

The interrupt vector generation circuit 13 corresponds to the interrupt vector generation circuit 3 in FIG.
The encoder 1 outputs an interrupt vector to the lower data bus DB2 of the CPU 10 based on the level instruction signals A01 to A03 outputted from the encoder 1 and the interrupt cause signal outputted to the upper data bus DB1.
3-1, Inverting 3-state gate 1
3-2 etc. are equipped. Encoder 13-1
This determines which of the upper data buses 08 to 15 the bit that caused the interrupt sent on the upper data bus DB1 is located in, and sends out a 3-bit output signal that instructs it. Yes, the inverting 3-state gate 13-2 uses the 3-bit output signal sent from the encoder 13-1, the 3-bit level indication signals A01 to A03 output from the CPU 10, and the 2 fixed bits. Create an 8-bit interrupt vector and
0 to its lower data bus DB2.

The NAND circuit 14 outputs an L-level strobe signal indicating an interrupt recognition cycle when all input signals FC0 to FC2 are at H-level.

Next, the operation of the present invention will be explained.

In FIG. 2, when an interrupt of interrupt cause 1 occurs and an H level signal is applied to the connection between the signal output section 21-1 and the gate 22-1, the signal output section 21-1 becomes a low level signal. As a result, -low level *iRQ1 is input to encoder 11, encoder 11 recognizes that a level 1 interrupt has occurred, and outputs level 1 by 3-bit output signals *iPL0 to *iPL2. Outputs a signal indicating.

The CPU 10 thereby learns that a level 1 interrupt request has occurred, and executes a level 1 interrupt vector read cycle.

CPU 10 outputs to NAND circuit 14
FC0 to FC2 are all set to H, and *AS is output at low level. This causes the OR circuit 15 to output a low level interrupt vector read cycle signal.
iACK is output, and the inverting 3-state gate 13-2 and decoder 12 become active. Furthermore, by executing the level 1 interrupt vector read cycle, the CPU 10 sends a 3-bit signal A01 indicating level 1 to the address bus AB.
Output ~A03. The decoder 12 decodes the signal indicating level 1 on this address bus,
Outputs a low level signal to terminal 1.

When a low level signal is output to terminal 1 of decoder 12, gate 22-1 is turned on and drives bit D08 in upper data bus DB1 of CPU 10 low.

Encoder 13- of interrupt vector generation circuit 13
1 decodes that this bit D08 has been driven to low level and inverts the 3-bit signal indicating the occurrence of interrupt cause 1 to a 3-state state.
Output to gate 13-2, and separate 0V and
Outputs a fixed 5V signal. At this time, the inverting 3-state gate 13-2 has
A01~ indicating level 1 output from CPU10
Since the A03 signal is also being transmitted, based on these signals, an 8-bit interrupt vector indicating that interrupt cause 1 has occurred is sent to the lower data bus.
Output to DB2. The CPU 10 decodes this and recognizes that interrupt cause 1 has occurred.

By the way, when interrupt cause 2 occurs, a low level signal is output to terminal 1 of the decoder 12 in the same way as in the case described above, which turns on the gate 22-2 and connects the upper data bus.
Since bit D09 in DB1 is driven low, encoder 13-1 decodes this and outputs a 3-bit signal indicating the occurrence of interrupt cause 2. Inverting 3-state gate 13
-2 indicates this and the fixed signal and level 1
Based on the signals A01 to A03, an interrupt vector indicating the occurrence of interrupt cause 2 is output onto lower data bus DB2, and the CPU 10 decodes this to recognize the occurrence of interrupt cause 2.

Also, when a level 7 interrupt cause (not shown) occurs, *iRQ7 becomes low level in the same way as in the previous case, so the encoder 11 changes the 3 bits *iPL0 to * which indicate level 7.
Output iPL2 to CPU 10, CPU 10 outputs A01 to A03 indicating level 7 to the address bus,
Since bits D08 to D15 become low level depending on the cause of the interrupt, the interrupt vector is similarly sent onto the lower data bus DB2.

Note that in the above embodiment, the data bus is used as the CPU.
Although a 16-bit format has been described, the present invention is of course not limited to this, and can also be used with 32-bit format or other formats.

〔Effect of the invention〕

According to the present invention, a signal indicating the interrupt type can be output to the upper level of the data bus during the interrupt vector read cycle, so that the signal for each interrupt cause can be output onto the bus and the interrupt vector generation circuit can send the interrupt cause to the interrupt vector generation circuit. There is no need for input from the generation circuit, and therefore, signal lines on the bus for each interrupt cause can be eliminated.

[Brief explanation of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention, and FIG. 2 is a diagram illustrating the configuration of an embodiment of the present invention. 10...CPU, 11...Encoder, 12...
...Decoder, 13...Interrupt vector generation circuit.

Claims (1)

[Scope of Claims] 1. A CPU 1 that reads an interrupt vector from the lower bits of a data bus in response to an interrupt request signal, and a CPU 1 that outputs an interrupt request signal when there are multiple interrupt causes and generates an interrupt during an interrupt vector read cycle. An interrupt request unit 2 that outputs a type signal to one of the upper bits of the data bus, and an interrupt vector generation circuit 3 that encodes the upper bits of the data bus and generates an interrupt vector during an interrupt vector read cycle. An interrupt vector generation method characterized by comprising: