JPH0429272B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for generating intermittent tone in a telephone exchange.

Conventional telephone exchanges use various audible signal tones (hereinafter simply referred to as tones), such as the dial tone (DT) generated when a telephone picks up the handset, the ring back tone (RBT) generated when calling the other party after dialing, and the other party's tone. Busy tone (BT), which occurs when someone is busy, is used.
By the way, these tones are also used in exchanges that have time-division communication channels (hereinafter simply referred to as digital exchanges) that treat voice signals as digital signal sequences, but the tones are handled in digital form within the digital exchange. Therefore, it is more advantageous to generate tones directly from digital signals than from analog signals.

Incidentally, a tone is a continuous sound or periodically interrupted sound of a single frequency or a multifrequency (specifically, two-frequency) mixed wave. An example of this tone is shown in FIG.
FIG. 1a shows the waveform of tone A, and FIG. 1b shows the waveform of tone B. It is clear that tones A and B are different in frequency, intermittent period, and amplitude. Furthermore, in the digital encoding of tones as described above, generally, as shown in Fig. 2, the analog tone shown in Fig. 2a is sampled as shown in Fig. 2b to create a large number of sample values _S0 ... _S11 , and these samples are It is expressed by the process of converting the value into a digital code string, as shown in c of the same figure. A time division multiplexed signal is a combination of digital code strings as described above into one serial signal string.
One frame is divided into a large number of time slots, with the sample value time being one frame, and one digital code string is made to correspond to a time slot at a fixed position in one frame, as shown in FIG.

In a digital exchange, the above-mentioned time-division multiplexed signals are input to the time-division communication path and the necessary subscriber terminals are
Distribute to SUB ₁ and SUB ₂ . That is, as shown in FIG. 3, the above-mentioned tones generated by the tone generator 2 are transmitted to the subscriber terminals SUB ₁ and SUB _{2 at different times t 1 and 2 via} the digital exchange 1 having a time-division communication path. It is distributed at time _t2 .

FIG. 4 shows a conventional example of the tone generator as described above. In the figure, a memory 20 stores digital values for one period each of a plurality of types of tones, and includes tone types for one period (for example, tones A to tone D shown in FIG. 6 and silence as described later). The specified tones are sequentially output by sequentially giving each frame an upper address that specifies the upper address and a lower address that specifies the sample value of the tone for one cycle. This output will hereinafter be referred to as a multiplexed tone signal.

FIG. 6 shows the contents stored in the memory 20, which is divided into four tone areas A to D and silence pattern data, one area is designated by the upper address and one area is designated by the lower address.
One piece of data in one area is specified. Since the silent pattern is composed of a fixed pattern, one piece of data is designated by the upper and lower addresses.

The selector 21 selects a lower address of the memory 20, and this lower address corresponds to each tone type (tone A to tone D) or silence pattern designation, and counters 22a to 22d that increment every frame. Select one of the lower addresses of the output or silent pattern. This selector 2
The selection information 1 specifies the sample value of one tone by both the upper address of the memory 20 (indicating tone type or silence pattern designation).

The counter 23 is a time slot counter that increments at a cycle of one frame for each time slot. The decoder 24 decodes the time slot for outputting a tone, selects a selector 25 that selects an upper address according to the tone type, and selects counters 26a to 26c according to the intermittent type (for example, inter 1 to inter 3). Selector 2
The time information of the above-mentioned time slot is supplied to the time slot 7 via the coder 28. Counters 26a to 26c selected by the selector 27 to correspond to the output tone
The output of is given to the selector 29 and the memory 20
Decide whether to specify a tone signal pattern or a no-signal pattern for the upper address of , that is, whether to turn the tone ON or OFF. This operation is performed for each time slot, and different tones and corresponding output patterns and inters are output one after another. As described above, when the upper and lower addresses of the memory 20 are given, a multiplexed tone signal with intermittent signals is obtained at the output of the memory 20.

A circuit for controlling each selector with the output of the counter 23 is shown in FIG. 5, and the quantity of metal objects will be discussed. Each lead of the decoder 24 obtains an output when the output of the counter 23 becomes a specific pattern, and mainly functions as a multi-input AND gate.
Therefore, if a configuration is adopted in which the count value of the counter 23 increases, the number of output leads of the counter 23 increases, so the number of input leads of the AND gate also increases, and one AND gate is required for one tone type. . This is because the output of the decoder 24 corresponds to the tone type, and becomes information exclusively for selection by the selector 25. The coder 28 distributes the output of the decoder 24 according to the type of inter, and when two or more tones are the same inter, they are aggregated by an OR gate function to obtain information exclusively for selection by the selector 27. Therefore, as the number of tone types increases, the number of input leads for the coder 28 increases.
As the number of gates or the size of the gates increases, the amount of metal objects increases. The amount of metal in the selector 27 increases almost in proportion to the type of interface.

In this way, in the tone generator as described above, as the types of tones and the types of inters increase, the hardware components of the counters 22a to 22d, counters 26a to 26c, memory 20, selector 21, decoder 24, selector 27, and coder 28 increase. The amount increases and the overall scale becomes large.

In summary, the conventional intermittent tone generation system has drawbacks in the following cases.

(1) When the multiplicity is high, the number of time slots per frame is large, and the number of tone types is large, the amount of hardware for the decoder increases. In the same case, the amount of metal in the coder also increases.

(2) The mutual correspondence between time slots, tone types, and interfaces is based on fixed wire logic using a decoder or coder, so there is little flexibility in changing it.

In view of the above-mentioned drawbacks of the conventional art, the present invention provides time-division multiplexing of audible signal tones by periodically and repeatedly reading out digital waveform data or digital silence data sequentially from memory for each of a plurality of signal channels. In a tone generator that generates a tone signal, data is stored as multiple types of digital tone waveform data and digital silence patterns, and the tone type or silence pattern area is specified in the upper address of the input terminal, and the area of the tone type or silence pattern is specified in the lower address. a first memory means for outputting a multiplexed tone signal by specifying one piece of data in one area; and a first memory means for specifying intermittent information of the tone at an upper address of an input terminal, and time-division multiplexing at a lower address. and a second memory means for outputting upper address information of the first memory by specifying time slot number information of the signal, the second memory means outputting upper address information of the first memory according to the time slot number of the time division multiplexed signal. specifying the address of the means, and further specifying the address of the first means.
is configured to obtain a multiplexed intermittent tone signal by specifying the address of the memory means of the
The purpose is to provide an economical and flexible intermittent tone generator that reduces the amount of hardware and facilitates hardware changes.

The present invention will be explained in detail below.

FIG. 7 shows an embodiment of the present invention, in which 200 is a first memory, 201 is a second memory, 202a to 202d are first counters, 20
3 is the second counter, 204a to 204c are the third counters, and 204a to 204c are the third counters.
205 is a selector. The above counters 202a to 202d, 203, 204a to
Among the counters 204c, the one that operates at the highest speed is the counter 203, which increments every time slot. One period of time during which the counter 203 reaches a full count from 0 corresponds to one frame, and the counters 202a to 202d advance by one step in one frame. The counters 202a to 202d correspond to the type of tone, similar to the counters 22a to 22d in FIG. 4 showing the conventional example, and their outputs correspond to the sample time (the suffix value of S in FIG. 2c). The full count value is different for each. Also, the time it takes for these counters 202a to 202d to advance one step is one frame, and in a digital exchange
125μs is common.

The steps of the counters 204a to 204c are even slower than this, and the period of intermittent signal tones is about 0.1 to about 10 seconds, so the number of stages of the input counter of each counter is set so that it is about 0.1 to about 10 seconds.

In addition, the counters 204a to 204c have a one-to-one correspondence with the type of intermittent signal (meaning intermittent signal tone, etc.).
Since the intermittent period differs depending on the type, the increment intervals of the counters 204a to 204c are set to be different. For example, the busy tone may be interrupted 60 times per minute (this is called 60 inters), or it may be connected for 2 seconds and disconnected for 4 seconds (this is called 10 inters).

The memory 201 inputs the outputs of the counter 203 and counters 204a to 204c as addresses, and outputs information specifying tone type or silence pattern. The output of the counter 203 is the lower address, and the outputs of the counters 204a to 204c are the upper address. The output of the memory 201 is a signal indicating the tone type or silent pattern designation, such as a mixed frequency of 440 Hz and 350 Hz, a single frequency of 440 Hz, or a silent pattern.

Here, considering the output of the memory 201 at a certain time, when the output of the memory 201 indicates that there is a signal tone, the upper address of the memory 200 corresponding to the tone type is output, and when it indicates that there is no signal tone, there is no sound. Memory 200 corresponding to the pattern
The upper address of is output.

As shown in FIG. 8, the storage contents of the memory 201 are areas corresponding to the same number of time slots as the count value of the counter 203 (32 slots from TS0 to TS31 in the figure).
The counters 204a to 204a take one pattern as one pattern.
There are eight patterns, which is the number of output combinations of 04c. That is, when the types of interfaces, in other words, the number of counters connected to the upper addresses of the memory 201 are three, counters 204a to 204c, the number of combinations of outputs of the counters 204a to 204c, that is, 2 ³ =8. There's a pattern. In the example shown in FIG. 8, the storage capacity of the memory 201 is 1 word (upper address information of the memory 200) x 32 (number of time slots) x 8 (number of inter combinations) = 256 words, and the upper address of the memory 200 is 8 In terms of bits, one commercially available 256-word, 8-bit read-only memory (ROM) can satisfy the function.

By the way, from the perspective of various tones, the same time slot corresponds to the same tone, but depending on the counter that specifies the inter, there are cases where there is a tone and cases where there is no tone (silence).

In this embodiment, as described above, the memory 201 is provided which inputs the outputs of the time slot counter 203 and the counters 204a to 204c for specifying the inter type and outputs the tone type or silence information for each time slot. The decoder 24, coder 28, selector 27, selector 25, and selector 29 in the configuration shown in FIG. 4, which is an example, are no longer necessary. That is, since these parts are replaced with one memory, the amount of hardware is small and the configuration is highly flexible.

The memory 200 stores digital values of tone waveforms, holds several tens to hundreds of words of waveform data for each tone type, and outputs one word of the tone specified by the address as a digital signal. The output timing is one word per one time slot. The number of bits in one output word is normally 8 bits, and when looking at one tone, waveform values of several tens to several hundred words are sequentially and repeatedly output.

The selector 205 selects the counters 202a to 202.
The output of d is selected and given to the lower address of the memory 200, and this memory 200 selects the output of 1 and gives it to the lower address of the memory 200.
It is like selecting word waveform data.

Next, the operation of this circuit will be explained in chronological order.
First, consider one frame time. counter 2
02a to 202d, counters 204a to 204c
The increment of is always performed at the break of frame time, and the count values of these counters are held for one frame. Counter 203 counts time slots during one frame and counts one period. Now, if the counter 204a is set to a count value of 0, the counter 204b is set to a count value of 0, and the counter 204c is set to a count value of 1, pattern 001 of the memory 201 is selected and data from addresses 32 to 63 in FIG. 8 are output. The contents of this data are as follows.

The output of the counter 203 changes for each time slot, but when considering a certain time slot time, the memory 201 is set so that one tone corresponding to that time slot is selected. Therefore, for example, the pattern of the memory 201 is
001, no sound is selected when the counter 204a or 204b is selected, one tone is selected when the counter 204c is selected, and the memory 20
Output from 1.

This output is the upper address of memory 200.

This output is first input to the selector 205 and then is input to the counter 2 corresponding to the tone type or silence pattern.
Specify one of 02a to 202d or the lower address (fixed value) of the silent pattern. memory 2
The upper address of 00 specifies the tone type, and the lower address specifies the address of one output of the counters 202a to 202d or a silent pattern, so the memory 20 is used for one time slot time.
One address of 0 is specified and the digital value of the tone waveform is read out. At the same time slot number of the next frame, the counters 202a to 202d
Since the count value increases by one count, the digital value of the tone waveform of the address increased by one is read out.

In this way, the memory 200 sequentially outputs the digital tones of the corresponding channels according to the time slots, and for one channel, the sample values of the tones are sequentially and periodically outputted.

Next, the operation of addressing the memory 200 that stores each tone waveform, the operation of allocating time slots to various tones, and the operation of intermittent tones at the intervals of the counters 204a to 204c will be described in more detail.

As mentioned above, the upper address of the memory 201 is composed of the outputs of the counters 204a to 204c,
This combination of outputs corresponds to a pattern in the contents stored in the memory 201 in FIG. For example, in the first frame, the count value of the counter 204a is 1, the count value of the counter 204b is 1, and the count value of the counter 204a is 1.
When the count value of 04c is 0, the pattern is expressed as "110".

The lower address of the memory 201 is the output of a counter that increments by one step in one time slot. Here, as shown in FIG. 8, an example will be explained in which the counter increments from 0 to 31 in one frame.

By specifying the upper and lower addresses of the memory 201, TS0 of the pattern "110" area in FIG.
One piece of data is specified from ~TS31.

The output of the memory 201 represents tone type data such as tones A to D or silence for each time slot.

When the upper address of the memory 201 is the same as in the first frame and the second frame, the value of the lower address of the memory 201 repeats in one frame period, so the output of the memory 201, that is, the tone type data, also repeats in one frame period.

As described above, the selector 205 selects one of the outputs of the counters 202a to 202d that increments every frame or the silent pattern address (lower address of the memory 200), so the change point of the input data of the selector 205 is data for each frame.

As shown in FIG. 7, the lower address of the memory 200 is the output of the selector 205, and is the one data selected by the selector 205 based on the output of the memory 201. The output of the memory 201 is so-called tone type data, and the addresses of the counters 202a to 202d or silent patterns correspond to each tone type.

For example, if the first time slot of the first frame at the upper address of the memory 200 is tone B, the selector 205 selects the corresponding counter value l at the lower address of the memory 200.

The stored contents of the memory 200 are the same as the memory 20 shown in FIG. 4 showing the conventional example, and the upper address specifies the tones A to D or silence pattern data in FIG. 6, and the lower address specifies the tone data of each tone data. One data value is specified. In this embodiment, the output of the memory 200 is also addressed in the same way, with the tone type being specified by the upper address and one piece of corresponding tone data being specified by the lower address by the output of a counter that increments every frame. .

Therefore, the multiplexed tone signal output from the memory 200 is one in which various tone signals are multiplexed in one frame for the number of time slots.
Regarding time slots of the same phase (position) in each frame, one tone signal is output in the order of addresses.

For example, considering the first time slot of each frame output from the memory 200, the tone signal is
Bl, Bl+1, Bl+2... are output.

Further, an example in which tone intermittent occurs is that when the output of the counter 204c at the upper address of the memory 201 is "0", the second time slot of each of the first and second frames of the output of the memory 201 is a "silent" tone. The counter 204 is specified in the third frame.
One tone of the multiplexed tone signal output from the memory 200 is specified such that when the output of the memory 201 is "1", "tone D" is specified in the second time slot of the third frame of the output of the memory 201. If we pay attention to the signal, the intermittent tone signal is always caused by the counter 204.
It is controlled by switching the pattern of the address area of the memory 201 using one output (inter) of a to 204c.

According to the above embodiment, the conventional logic circuit configuration, that is, a circuit that creates a tone type including a silence pattern designation corresponding to a time slot from a counter output for counting time slots and an output of an inter counter, is implemented by a decoder and a coder. What used to be composed of seed selectors can be consolidated into the memory 201. If this memory 201 has a large capacity and allows data to be written externally, it is possible to
It can be aggregated into individual parts. In addition, by taking advantage of the characteristics of memory that allows external writing when necessary,
Tone types, inters and channels can be easily changed.

In the embodiment shown in FIG. 7, there are three counters 204a to 204c as inter counters, and four counters 202a to 202d provided for each tone type.
The output of the memory 201 is four tone types and one tone type.
represents a total of 5 pieces of silence pattern specification information,
Since the selector 205 has five inputs and selects one of them, the input/output ratio is 5:1, and the present invention has been explained using this configuration. However, even if these numbers are different, the effects of the present invention can be sufficiently achieved.

In other words, for example, if there are 6 inter types and a total of 8 tone types including silence pattern designation,
There are six counters 204, seven counters 202 corresponding to tone types (assuming no counters are needed for silent patterns), and the output of the memory 201 is eight types of designation information. At this time, assuming that the counter 203 has 32 counts (32 time slots), the storage capacity of the memory 201 is 32 x 2 ⁶ = 2048 words (1 word = 3 bits), and the input/output ratio of the selector 205 is 8:1. .

In this way, even when the inter or tone type becomes large, in the method of the present invention, the counters 204a to 204c and the counters 202a to 2
By increasing the scale of 02d and selector 205, and increasing the capacity of memory 201, the necessary multiplexed tone signal can be obtained, and the amount of hardware can be reduced. Incidentally, according to the conventional example, such an expansion in scale would require correspondingly larger decoders and other selectors in addition to the memory, counter, and selector, resulting in a greater degree of increase in the amount of hardware.

As described above, according to the present invention, since the amount of hardware can be reduced, a tone generator that generates a large number of different intermittent tones can be constructed economically.
Further, since the hardware can be easily changed, there is an advantage that this type of tone generator can be constructed with great flexibility.

[Brief explanation of drawings]

Figures 1a and b are waveform diagrams showing examples of audible signal tones (tones), Figures 2a to d are diagrams explaining digital encoding of tones, Figure 3 is an illustration of a digital exchange, and Figure 4 is a block diagram of a conventional tone generator, No. 5
6 is a detailed circuit diagram of a part of a conventional tone generator, FIG. 6 is an explanatory diagram of the contents of the memory 20, FIG. 7 is a block diagram of a tone generator showing an embodiment of the present invention, and FIG.
The figure is an explanatory diagram of the contents of the memory 201. 200...First memory, 201...Second memory, 202a-202d, 203, 204a-2
04c...Counter, 205...Selector.

Claims (1)

[Claims] 1. A time division multiplexed signal of audible signal tones (tones) is generated by periodically and repeatedly reading out digital waveform data or digital silence data sequentially from memory for each of a plurality of signal channels. In the tone generator, multiple types of digital tone waveform data and digital silence pattern data are stored, and the tone type or silence pattern area is specified in the upper address of the input terminal, and one of the areas in one area is specified in the lower address. a first memory means for outputting a multiplexed tone signal by specifying data of the input terminal; and a first memory means for specifying intermittent information of the tone in the upper address of the input terminal, and time slot number information of the time division multiplexed signal in the lower address. a second memory means for outputting upper address information of the first memory by specifying a time slot number of the time division multiplexed signal; , further comprising the step of obtaining a multiplexed intermittent tone signal by specifying an address in said first memory means.